1 //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the declaration of the MachineInstr class, which is the 10 // basic representation for all target dependent machine instructions used by 11 // the back end. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_CODEGEN_MACHINEINSTR_H 16 #define LLVM_CODEGEN_MACHINEINSTR_H 17 18 #include "llvm/ADT/DenseMapInfo.h" 19 #include "llvm/ADT/PointerSumType.h" 20 #include "llvm/ADT/SmallSet.h" 21 #include "llvm/ADT/ilist.h" 22 #include "llvm/ADT/ilist_node.h" 23 #include "llvm/ADT/iterator_range.h" 24 #include "llvm/CodeGen/MachineMemOperand.h" 25 #include "llvm/CodeGen/MachineOperand.h" 26 #include "llvm/CodeGen/TargetOpcodes.h" 27 #include "llvm/IR/DebugLoc.h" 28 #include "llvm/IR/InlineAsm.h" 29 #include "llvm/IR/PseudoProbe.h" 30 #include "llvm/MC/MCInstrDesc.h" 31 #include "llvm/MC/MCSymbol.h" 32 #include "llvm/Support/ArrayRecycler.h" 33 #include "llvm/Support/TrailingObjects.h" 34 #include <algorithm> 35 #include <cassert> 36 #include <cstdint> 37 #include <utility> 38 39 namespace llvm { 40 41 class AAResults; 42 template <typename T> class ArrayRef; 43 class DIExpression; 44 class DILocalVariable; 45 class MachineBasicBlock; 46 class MachineFunction; 47 class MachineRegisterInfo; 48 class ModuleSlotTracker; 49 class raw_ostream; 50 template <typename T> class SmallVectorImpl; 51 class SmallBitVector; 52 class StringRef; 53 class TargetInstrInfo; 54 class TargetRegisterClass; 55 class TargetRegisterInfo; 56 57 //===----------------------------------------------------------------------===// 58 /// Representation of each machine instruction. 59 /// 60 /// This class isn't a POD type, but it must have a trivial destructor. When a 61 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated 62 /// without having their destructor called. 63 /// 64 class MachineInstr 65 : public ilist_node_with_parent<MachineInstr, MachineBasicBlock, 66 ilist_sentinel_tracking<true>> { 67 public: 68 using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator; 69 70 /// Flags to specify different kinds of comments to output in 71 /// assembly code. These flags carry semantic information not 72 /// otherwise easily derivable from the IR text. 73 /// 74 enum CommentFlag { 75 ReloadReuse = 0x1, // higher bits are reserved for target dep comments. 76 NoSchedComment = 0x2, 77 TAsmComments = 0x4 // Target Asm comments should start from this value. 78 }; 79 80 enum MIFlag { 81 NoFlags = 0, 82 FrameSetup = 1 << 0, // Instruction is used as a part of 83 // function frame setup code. 84 FrameDestroy = 1 << 1, // Instruction is used as a part of 85 // function frame destruction code. 86 BundledPred = 1 << 2, // Instruction has bundled predecessors. 87 BundledSucc = 1 << 3, // Instruction has bundled successors. 88 FmNoNans = 1 << 4, // Instruction does not support Fast 89 // math nan values. 90 FmNoInfs = 1 << 5, // Instruction does not support Fast 91 // math infinity values. 92 FmNsz = 1 << 6, // Instruction is not required to retain 93 // signed zero values. 94 FmArcp = 1 << 7, // Instruction supports Fast math 95 // reciprocal approximations. 96 FmContract = 1 << 8, // Instruction supports Fast math 97 // contraction operations like fma. 98 FmAfn = 1 << 9, // Instruction may map to Fast math 99 // instrinsic approximation. 100 FmReassoc = 1 << 10, // Instruction supports Fast math 101 // reassociation of operand order. 102 NoUWrap = 1 << 11, // Instruction supports binary operator 103 // no unsigned wrap. 104 NoSWrap = 1 << 12, // Instruction supports binary operator 105 // no signed wrap. 106 IsExact = 1 << 13, // Instruction supports division is 107 // known to be exact. 108 NoFPExcept = 1 << 14, // Instruction does not raise 109 // floatint-point exceptions. 110 NoMerge = 1 << 15, // Passes that drop source location info 111 // (e.g. branch folding) should skip 112 // this instruction. 113 }; 114 115 private: 116 const MCInstrDesc *MCID; // Instruction descriptor. 117 MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block. 118 119 // Operands are allocated by an ArrayRecycler. 120 MachineOperand *Operands = nullptr; // Pointer to the first operand. 121 unsigned NumOperands = 0; // Number of operands on instruction. 122 123 uint16_t Flags = 0; // Various bits of additional 124 // information about machine 125 // instruction. 126 127 uint8_t AsmPrinterFlags = 0; // Various bits of information used by 128 // the AsmPrinter to emit helpful 129 // comments. This is *not* semantic 130 // information. Do not use this for 131 // anything other than to convey comment 132 // information to AsmPrinter. 133 134 // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags 135 // to properly pack. 136 using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity; 137 OperandCapacity CapOperands; // Capacity of the Operands array. 138 139 /// Internal implementation detail class that provides out-of-line storage for 140 /// extra info used by the machine instruction when this info cannot be stored 141 /// in-line within the instruction itself. 142 /// 143 /// This has to be defined eagerly due to the implementation constraints of 144 /// `PointerSumType` where it is used. 145 class ExtraInfo final 146 : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> { 147 public: 148 static ExtraInfo *create(BumpPtrAllocator &Allocator, 149 ArrayRef<MachineMemOperand *> MMOs, 150 MCSymbol *PreInstrSymbol = nullptr, 151 MCSymbol *PostInstrSymbol = nullptr, 152 MDNode *HeapAllocMarker = nullptr) { 153 bool HasPreInstrSymbol = PreInstrSymbol != nullptr; 154 bool HasPostInstrSymbol = PostInstrSymbol != nullptr; 155 bool HasHeapAllocMarker = HeapAllocMarker != nullptr; 156 auto *Result = new (Allocator.Allocate( 157 totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>( 158 MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol, 159 HasHeapAllocMarker), 160 alignof(ExtraInfo))) 161 ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol, 162 HasHeapAllocMarker); 163 164 // Copy the actual data into the trailing objects. 165 std::copy(MMOs.begin(), MMOs.end(), 166 Result->getTrailingObjects<MachineMemOperand *>()); 167 168 if (HasPreInstrSymbol) 169 Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol; 170 if (HasPostInstrSymbol) 171 Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] = 172 PostInstrSymbol; 173 if (HasHeapAllocMarker) 174 Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker; 175 176 return Result; 177 } 178 getMMOs()179 ArrayRef<MachineMemOperand *> getMMOs() const { 180 return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs); 181 } 182 getPreInstrSymbol()183 MCSymbol *getPreInstrSymbol() const { 184 return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr; 185 } 186 getPostInstrSymbol()187 MCSymbol *getPostInstrSymbol() const { 188 return HasPostInstrSymbol 189 ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] 190 : nullptr; 191 } 192 getHeapAllocMarker()193 MDNode *getHeapAllocMarker() const { 194 return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr; 195 } 196 197 private: 198 friend TrailingObjects; 199 200 // Description of the extra info, used to interpret the actual optional 201 // data appended. 202 // 203 // Note that this is not terribly space optimized. This leaves a great deal 204 // of flexibility to fit more in here later. 205 const int NumMMOs; 206 const bool HasPreInstrSymbol; 207 const bool HasPostInstrSymbol; 208 const bool HasHeapAllocMarker; 209 210 // Implement the `TrailingObjects` internal API. numTrailingObjects(OverloadToken<MachineMemOperand * >)211 size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const { 212 return NumMMOs; 213 } numTrailingObjects(OverloadToken<MCSymbol * >)214 size_t numTrailingObjects(OverloadToken<MCSymbol *>) const { 215 return HasPreInstrSymbol + HasPostInstrSymbol; 216 } numTrailingObjects(OverloadToken<MDNode * >)217 size_t numTrailingObjects(OverloadToken<MDNode *>) const { 218 return HasHeapAllocMarker; 219 } 220 221 // Just a boring constructor to allow us to initialize the sizes. Always use 222 // the `create` routine above. ExtraInfo(int NumMMOs,bool HasPreInstrSymbol,bool HasPostInstrSymbol,bool HasHeapAllocMarker)223 ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol, 224 bool HasHeapAllocMarker) 225 : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol), 226 HasPostInstrSymbol(HasPostInstrSymbol), 227 HasHeapAllocMarker(HasHeapAllocMarker) {} 228 }; 229 230 /// Enumeration of the kinds of inline extra info available. It is important 231 /// that the `MachineMemOperand` inline kind has a tag value of zero to make 232 /// it accessible as an `ArrayRef`. 233 enum ExtraInfoInlineKinds { 234 EIIK_MMO = 0, 235 EIIK_PreInstrSymbol, 236 EIIK_PostInstrSymbol, 237 EIIK_OutOfLine 238 }; 239 240 // We store extra information about the instruction here. The common case is 241 // expected to be nothing or a single pointer (typically a MMO or a symbol). 242 // We work to optimize this common case by storing it inline here rather than 243 // requiring a separate allocation, but we fall back to an allocation when 244 // multiple pointers are needed. 245 PointerSumType<ExtraInfoInlineKinds, 246 PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>, 247 PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>, 248 PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>, 249 PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>> 250 Info; 251 252 DebugLoc debugLoc; // Source line information. 253 254 /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values 255 /// defined by this instruction. 256 unsigned DebugInstrNum; 257 258 // Intrusive list support 259 friend struct ilist_traits<MachineInstr>; 260 friend struct ilist_callback_traits<MachineBasicBlock>; 261 void setParent(MachineBasicBlock *P) { Parent = P; } 262 263 /// This constructor creates a copy of the given 264 /// MachineInstr in the given MachineFunction. 265 MachineInstr(MachineFunction &, const MachineInstr &); 266 267 /// This constructor create a MachineInstr and add the implicit operands. 268 /// It reserves space for number of operands specified by 269 /// MCInstrDesc. An explicit DebugLoc is supplied. 270 MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl, 271 bool NoImp = false); 272 273 // MachineInstrs are pool-allocated and owned by MachineFunction. 274 friend class MachineFunction; 275 276 void 277 dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth, 278 SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const; 279 280 public: 281 MachineInstr(const MachineInstr &) = delete; 282 MachineInstr &operator=(const MachineInstr &) = delete; 283 // Use MachineFunction::DeleteMachineInstr() instead. 284 ~MachineInstr() = delete; 285 286 const MachineBasicBlock* getParent() const { return Parent; } 287 MachineBasicBlock* getParent() { return Parent; } 288 289 /// Move the instruction before \p MovePos. 290 void moveBefore(MachineInstr *MovePos); 291 292 /// Return the function that contains the basic block that this instruction 293 /// belongs to. 294 /// 295 /// Note: this is undefined behaviour if the instruction does not have a 296 /// parent. 297 const MachineFunction *getMF() const; 298 MachineFunction *getMF() { 299 return const_cast<MachineFunction *>( 300 static_cast<const MachineInstr *>(this)->getMF()); 301 } 302 303 /// Return the asm printer flags bitvector. 304 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } 305 306 /// Clear the AsmPrinter bitvector. 307 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } 308 309 /// Return whether an AsmPrinter flag is set. 310 bool getAsmPrinterFlag(CommentFlag Flag) const { 311 return AsmPrinterFlags & Flag; 312 } 313 314 /// Set a flag for the AsmPrinter. 315 void setAsmPrinterFlag(uint8_t Flag) { 316 AsmPrinterFlags |= Flag; 317 } 318 319 /// Clear specific AsmPrinter flags. 320 void clearAsmPrinterFlag(CommentFlag Flag) { 321 AsmPrinterFlags &= ~Flag; 322 } 323 324 /// Return the MI flags bitvector. 325 uint16_t getFlags() const { 326 return Flags; 327 } 328 329 /// Return whether an MI flag is set. 330 bool getFlag(MIFlag Flag) const { 331 return Flags & Flag; 332 } 333 334 /// Set a MI flag. 335 void setFlag(MIFlag Flag) { 336 Flags |= (uint16_t)Flag; 337 } 338 339 void setFlags(unsigned flags) { 340 // Filter out the automatically maintained flags. 341 unsigned Mask = BundledPred | BundledSucc; 342 Flags = (Flags & Mask) | (flags & ~Mask); 343 } 344 345 /// clearFlag - Clear a MI flag. 346 void clearFlag(MIFlag Flag) { 347 Flags &= ~((uint16_t)Flag); 348 } 349 350 /// Return true if MI is in a bundle (but not the first MI in a bundle). 351 /// 352 /// A bundle looks like this before it's finalized: 353 /// ---------------- 354 /// | MI | 355 /// ---------------- 356 /// | 357 /// ---------------- 358 /// | MI * | 359 /// ---------------- 360 /// | 361 /// ---------------- 362 /// | MI * | 363 /// ---------------- 364 /// In this case, the first MI starts a bundle but is not inside a bundle, the 365 /// next 2 MIs are considered "inside" the bundle. 366 /// 367 /// After a bundle is finalized, it looks like this: 368 /// ---------------- 369 /// | Bundle | 370 /// ---------------- 371 /// | 372 /// ---------------- 373 /// | MI * | 374 /// ---------------- 375 /// | 376 /// ---------------- 377 /// | MI * | 378 /// ---------------- 379 /// | 380 /// ---------------- 381 /// | MI * | 382 /// ---------------- 383 /// The first instruction has the special opcode "BUNDLE". It's not "inside" 384 /// a bundle, but the next three MIs are. 385 bool isInsideBundle() const { 386 return getFlag(BundledPred); 387 } 388 389 /// Return true if this instruction part of a bundle. This is true 390 /// if either itself or its following instruction is marked "InsideBundle". 391 bool isBundled() const { 392 return isBundledWithPred() || isBundledWithSucc(); 393 } 394 395 /// Return true if this instruction is part of a bundle, and it is not the 396 /// first instruction in the bundle. 397 bool isBundledWithPred() const { return getFlag(BundledPred); } 398 399 /// Return true if this instruction is part of a bundle, and it is not the 400 /// last instruction in the bundle. 401 bool isBundledWithSucc() const { return getFlag(BundledSucc); } 402 403 /// Bundle this instruction with its predecessor. This can be an unbundled 404 /// instruction, or it can be the first instruction in a bundle. 405 void bundleWithPred(); 406 407 /// Bundle this instruction with its successor. This can be an unbundled 408 /// instruction, or it can be the last instruction in a bundle. 409 void bundleWithSucc(); 410 411 /// Break bundle above this instruction. 412 void unbundleFromPred(); 413 414 /// Break bundle below this instruction. 415 void unbundleFromSucc(); 416 417 /// Returns the debug location id of this MachineInstr. 418 const DebugLoc &getDebugLoc() const { return debugLoc; } 419 420 /// Return the operand containing the offset to be used if this DBG_VALUE 421 /// instruction is indirect; will be an invalid register if this value is 422 /// not indirect, and an immediate with value 0 otherwise. 423 const MachineOperand &getDebugOffset() const { 424 assert(isNonListDebugValue() && "not a DBG_VALUE"); 425 return getOperand(1); 426 } 427 MachineOperand &getDebugOffset() { 428 assert(isNonListDebugValue() && "not a DBG_VALUE"); 429 return getOperand(1); 430 } 431 432 /// Return the operand for the debug variable referenced by 433 /// this DBG_VALUE instruction. 434 const MachineOperand &getDebugVariableOp() const; 435 MachineOperand &getDebugVariableOp(); 436 437 /// Return the debug variable referenced by 438 /// this DBG_VALUE instruction. 439 const DILocalVariable *getDebugVariable() const; 440 441 /// Return the operand for the complex address expression referenced by 442 /// this DBG_VALUE instruction. 443 const MachineOperand &getDebugExpressionOp() const; 444 MachineOperand &getDebugExpressionOp(); 445 446 /// Return the complex address expression referenced by 447 /// this DBG_VALUE instruction. 448 const DIExpression *getDebugExpression() const; 449 450 /// Return the debug label referenced by 451 /// this DBG_LABEL instruction. 452 const DILabel *getDebugLabel() const; 453 454 /// Fetch the instruction number of this MachineInstr. If it does not have 455 /// one already, a new and unique number will be assigned. 456 unsigned getDebugInstrNum(); 457 458 /// Fetch instruction number of this MachineInstr -- but before it's inserted 459 /// into \p MF. Needed for transformations that create an instruction but 460 /// don't immediately insert them. 461 unsigned getDebugInstrNum(MachineFunction &MF); 462 463 /// Examine the instruction number of this MachineInstr. May be zero if 464 /// it hasn't been assigned a number yet. 465 unsigned peekDebugInstrNum() const { return DebugInstrNum; } 466 467 /// Set instruction number of this MachineInstr. Avoid using unless you're 468 /// deserializing this information. 469 void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; } 470 471 /// Drop any variable location debugging information associated with this 472 /// instruction. Use when an instruction is modified in such a way that it no 473 /// longer defines the value it used to. Variable locations using that value 474 /// will be dropped. 475 void dropDebugNumber() { DebugInstrNum = 0; } 476 477 /// Emit an error referring to the source location of this instruction. 478 /// This should only be used for inline assembly that is somehow 479 /// impossible to compile. Other errors should have been handled much 480 /// earlier. 481 /// 482 /// If this method returns, the caller should try to recover from the error. 483 void emitError(StringRef Msg) const; 484 485 /// Returns the target instruction descriptor of this MachineInstr. 486 const MCInstrDesc &getDesc() const { return *MCID; } 487 488 /// Returns the opcode of this MachineInstr. 489 unsigned getOpcode() const { return MCID->Opcode; } 490 491 /// Retuns the total number of operands. 492 unsigned getNumOperands() const { return NumOperands; } 493 494 /// Returns the total number of operands which are debug locations. 495 unsigned getNumDebugOperands() const { 496 return std::distance(debug_operands().begin(), debug_operands().end()); 497 } 498 499 const MachineOperand& getOperand(unsigned i) const { 500 assert(i < getNumOperands() && "getOperand() out of range!"); 501 return Operands[i]; 502 } 503 MachineOperand& getOperand(unsigned i) { 504 assert(i < getNumOperands() && "getOperand() out of range!"); 505 return Operands[i]; 506 } 507 508 MachineOperand &getDebugOperand(unsigned Index) { 509 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!"); 510 return *(debug_operands().begin() + Index); 511 } 512 const MachineOperand &getDebugOperand(unsigned Index) const { 513 assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!"); 514 return *(debug_operands().begin() + Index); 515 } 516 517 SmallSet<Register, 4> getUsedDebugRegs() const { 518 assert(isDebugValue() && "not a DBG_VALUE*"); 519 SmallSet<Register, 4> UsedRegs; 520 for (auto MO : debug_operands()) 521 if (MO.isReg() && MO.getReg()) 522 UsedRegs.insert(MO.getReg()); 523 return UsedRegs; 524 } 525 526 /// Returns whether this debug value has at least one debug operand with the 527 /// register \p Reg. 528 bool hasDebugOperandForReg(Register Reg) const { 529 return any_of(debug_operands(), [Reg](const MachineOperand &Op) { 530 return Op.isReg() && Op.getReg() == Reg; 531 }); 532 } 533 534 /// Returns a range of all of the operands that correspond to a debug use of 535 /// \p Reg. 536 template <typename Operand, typename Instruction> 537 static iterator_range< 538 filter_iterator<Operand *, std::function<bool(Operand &Op)>>> 539 getDebugOperandsForReg(Instruction *MI, Register Reg) { 540 std::function<bool(Operand & Op)> OpUsesReg( 541 [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; }); 542 return make_filter_range(MI->debug_operands(), OpUsesReg); 543 } 544 iterator_range<filter_iterator<const MachineOperand *, 545 std::function<bool(const MachineOperand &Op)>>> 546 getDebugOperandsForReg(Register Reg) const { 547 return MachineInstr::getDebugOperandsForReg<const MachineOperand, 548 const MachineInstr>(this, Reg); 549 } 550 iterator_range<filter_iterator<MachineOperand *, 551 std::function<bool(MachineOperand &Op)>>> 552 getDebugOperandsForReg(Register Reg) { 553 return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>( 554 this, Reg); 555 } 556 557 bool isDebugOperand(const MachineOperand *Op) const { 558 return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands()); 559 } 560 561 unsigned getDebugOperandIndex(const MachineOperand *Op) const { 562 assert(isDebugOperand(Op) && "Expected a debug operand."); 563 return std::distance(adl_begin(debug_operands()), Op); 564 } 565 566 /// Returns the total number of definitions. 567 unsigned getNumDefs() const { 568 return getNumExplicitDefs() + MCID->getNumImplicitDefs(); 569 } 570 571 /// Returns true if the instruction has implicit definition. 572 bool hasImplicitDef() const { 573 for (unsigned I = getNumExplicitOperands(), E = getNumOperands(); 574 I != E; ++I) { 575 const MachineOperand &MO = getOperand(I); 576 if (MO.isDef() && MO.isImplicit()) 577 return true; 578 } 579 return false; 580 } 581 582 /// Returns the implicit operands number. 583 unsigned getNumImplicitOperands() const { 584 return getNumOperands() - getNumExplicitOperands(); 585 } 586 587 /// Return true if operand \p OpIdx is a subregister index. 588 bool isOperandSubregIdx(unsigned OpIdx) const { 589 assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate && 590 "Expected MO_Immediate operand type."); 591 if (isExtractSubreg() && OpIdx == 2) 592 return true; 593 if (isInsertSubreg() && OpIdx == 3) 594 return true; 595 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) 596 return true; 597 if (isSubregToReg() && OpIdx == 3) 598 return true; 599 return false; 600 } 601 602 /// Returns the number of non-implicit operands. 603 unsigned getNumExplicitOperands() const; 604 605 /// Returns the number of non-implicit definitions. 606 unsigned getNumExplicitDefs() const; 607 608 /// iterator/begin/end - Iterate over all operands of a machine instruction. 609 using mop_iterator = MachineOperand *; 610 using const_mop_iterator = const MachineOperand *; 611 612 mop_iterator operands_begin() { return Operands; } 613 mop_iterator operands_end() { return Operands + NumOperands; } 614 615 const_mop_iterator operands_begin() const { return Operands; } 616 const_mop_iterator operands_end() const { return Operands + NumOperands; } 617 618 iterator_range<mop_iterator> operands() { 619 return make_range(operands_begin(), operands_end()); 620 } 621 iterator_range<const_mop_iterator> operands() const { 622 return make_range(operands_begin(), operands_end()); 623 } 624 iterator_range<mop_iterator> explicit_operands() { 625 return make_range(operands_begin(), 626 operands_begin() + getNumExplicitOperands()); 627 } 628 iterator_range<const_mop_iterator> explicit_operands() const { 629 return make_range(operands_begin(), 630 operands_begin() + getNumExplicitOperands()); 631 } 632 iterator_range<mop_iterator> implicit_operands() { 633 return make_range(explicit_operands().end(), operands_end()); 634 } 635 iterator_range<const_mop_iterator> implicit_operands() const { 636 return make_range(explicit_operands().end(), operands_end()); 637 } 638 /// Returns a range over all operands that are used to determine the variable 639 /// location for this DBG_VALUE instruction. 640 iterator_range<mop_iterator> debug_operands() { 641 assert(isDebugValue() && "Must be a debug value instruction."); 642 return isDebugValueList() 643 ? make_range(operands_begin() + 2, operands_end()) 644 : make_range(operands_begin(), operands_begin() + 1); 645 } 646 /// \copydoc debug_operands() 647 iterator_range<const_mop_iterator> debug_operands() const { 648 assert(isDebugValue() && "Must be a debug value instruction."); 649 return isDebugValueList() 650 ? make_range(operands_begin() + 2, operands_end()) 651 : make_range(operands_begin(), operands_begin() + 1); 652 } 653 /// Returns a range over all explicit operands that are register definitions. 654 /// Implicit definition are not included! 655 iterator_range<mop_iterator> defs() { 656 return make_range(operands_begin(), 657 operands_begin() + getNumExplicitDefs()); 658 } 659 /// \copydoc defs() 660 iterator_range<const_mop_iterator> defs() const { 661 return make_range(operands_begin(), 662 operands_begin() + getNumExplicitDefs()); 663 } 664 /// Returns a range that includes all operands that are register uses. 665 /// This may include unrelated operands which are not register uses. 666 iterator_range<mop_iterator> uses() { 667 return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); 668 } 669 /// \copydoc uses() 670 iterator_range<const_mop_iterator> uses() const { 671 return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); 672 } 673 iterator_range<mop_iterator> explicit_uses() { 674 return make_range(operands_begin() + getNumExplicitDefs(), 675 operands_begin() + getNumExplicitOperands()); 676 } 677 iterator_range<const_mop_iterator> explicit_uses() const { 678 return make_range(operands_begin() + getNumExplicitDefs(), 679 operands_begin() + getNumExplicitOperands()); 680 } 681 682 /// Returns the number of the operand iterator \p I points to. 683 unsigned getOperandNo(const_mop_iterator I) const { 684 return I - operands_begin(); 685 } 686 687 /// Access to memory operands of the instruction. If there are none, that does 688 /// not imply anything about whether the function accesses memory. Instead, 689 /// the caller must behave conservatively. 690 ArrayRef<MachineMemOperand *> memoperands() const { 691 if (!Info) 692 return {}; 693 694 if (Info.is<EIIK_MMO>()) 695 return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1); 696 697 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 698 return EI->getMMOs(); 699 700 return {}; 701 } 702 703 /// Access to memory operands of the instruction. 704 /// 705 /// If `memoperands_begin() == memoperands_end()`, that does not imply 706 /// anything about whether the function accesses memory. Instead, the caller 707 /// must behave conservatively. 708 mmo_iterator memoperands_begin() const { return memoperands().begin(); } 709 710 /// Access to memory operands of the instruction. 711 /// 712 /// If `memoperands_begin() == memoperands_end()`, that does not imply 713 /// anything about whether the function accesses memory. Instead, the caller 714 /// must behave conservatively. 715 mmo_iterator memoperands_end() const { return memoperands().end(); } 716 717 /// Return true if we don't have any memory operands which described the 718 /// memory access done by this instruction. If this is true, calling code 719 /// must be conservative. 720 bool memoperands_empty() const { return memoperands().empty(); } 721 722 /// Return true if this instruction has exactly one MachineMemOperand. 723 bool hasOneMemOperand() const { return memoperands().size() == 1; } 724 725 /// Return the number of memory operands. 726 unsigned getNumMemOperands() const { return memoperands().size(); } 727 728 /// Helper to extract a pre-instruction symbol if one has been added. 729 MCSymbol *getPreInstrSymbol() const { 730 if (!Info) 731 return nullptr; 732 if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>()) 733 return S; 734 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 735 return EI->getPreInstrSymbol(); 736 737 return nullptr; 738 } 739 740 /// Helper to extract a post-instruction symbol if one has been added. 741 MCSymbol *getPostInstrSymbol() const { 742 if (!Info) 743 return nullptr; 744 if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>()) 745 return S; 746 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 747 return EI->getPostInstrSymbol(); 748 749 return nullptr; 750 } 751 752 /// Helper to extract a heap alloc marker if one has been added. 753 MDNode *getHeapAllocMarker() const { 754 if (!Info) 755 return nullptr; 756 if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) 757 return EI->getHeapAllocMarker(); 758 759 return nullptr; 760 } 761 762 /// API for querying MachineInstr properties. They are the same as MCInstrDesc 763 /// queries but they are bundle aware. 764 765 enum QueryType { 766 IgnoreBundle, // Ignore bundles 767 AnyInBundle, // Return true if any instruction in bundle has property 768 AllInBundle // Return true if all instructions in bundle have property 769 }; 770 771 /// Return true if the instruction (or in the case of a bundle, 772 /// the instructions inside the bundle) has the specified property. 773 /// The first argument is the property being queried. 774 /// The second argument indicates whether the query should look inside 775 /// instruction bundles. 776 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { 777 assert(MCFlag < 64 && 778 "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle."); 779 // Inline the fast path for unbundled or bundle-internal instructions. 780 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) 781 return getDesc().getFlags() & (1ULL << MCFlag); 782 783 // If this is the first instruction in a bundle, take the slow path. 784 return hasPropertyInBundle(1ULL << MCFlag, Type); 785 } 786 787 /// Return true if this is an instruction that should go through the usual 788 /// legalization steps. 789 bool isPreISelOpcode(QueryType Type = IgnoreBundle) const { 790 return hasProperty(MCID::PreISelOpcode, Type); 791 } 792 793 /// Return true if this instruction can have a variable number of operands. 794 /// In this case, the variable operands will be after the normal 795 /// operands but before the implicit definitions and uses (if any are 796 /// present). 797 bool isVariadic(QueryType Type = IgnoreBundle) const { 798 return hasProperty(MCID::Variadic, Type); 799 } 800 801 /// Set if this instruction has an optional definition, e.g. 802 /// ARM instructions which can set condition code if 's' bit is set. 803 bool hasOptionalDef(QueryType Type = IgnoreBundle) const { 804 return hasProperty(MCID::HasOptionalDef, Type); 805 } 806 807 /// Return true if this is a pseudo instruction that doesn't 808 /// correspond to a real machine instruction. 809 bool isPseudo(QueryType Type = IgnoreBundle) const { 810 return hasProperty(MCID::Pseudo, Type); 811 } 812 813 bool isReturn(QueryType Type = AnyInBundle) const { 814 return hasProperty(MCID::Return, Type); 815 } 816 817 /// Return true if this is an instruction that marks the end of an EH scope, 818 /// i.e., a catchpad or a cleanuppad instruction. 819 bool isEHScopeReturn(QueryType Type = AnyInBundle) const { 820 return hasProperty(MCID::EHScopeReturn, Type); 821 } 822 823 bool isCall(QueryType Type = AnyInBundle) const { 824 return hasProperty(MCID::Call, Type); 825 } 826 827 /// Return true if this is a call instruction that may have an associated 828 /// call site entry in the debug info. 829 bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const; 830 /// Return true if copying, moving, or erasing this instruction requires 831 /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo, 832 /// \ref eraseCallSiteInfo). 833 bool shouldUpdateCallSiteInfo() const; 834 835 /// Returns true if the specified instruction stops control flow 836 /// from executing the instruction immediately following it. Examples include 837 /// unconditional branches and return instructions. 838 bool isBarrier(QueryType Type = AnyInBundle) const { 839 return hasProperty(MCID::Barrier, Type); 840 } 841 842 /// Returns true if this instruction part of the terminator for a basic block. 843 /// Typically this is things like return and branch instructions. 844 /// 845 /// Various passes use this to insert code into the bottom of a basic block, 846 /// but before control flow occurs. 847 bool isTerminator(QueryType Type = AnyInBundle) const { 848 return hasProperty(MCID::Terminator, Type); 849 } 850 851 /// Returns true if this is a conditional, unconditional, or indirect branch. 852 /// Predicates below can be used to discriminate between 853 /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to 854 /// get more information. 855 bool isBranch(QueryType Type = AnyInBundle) const { 856 return hasProperty(MCID::Branch, Type); 857 } 858 859 /// Return true if this is an indirect branch, such as a 860 /// branch through a register. 861 bool isIndirectBranch(QueryType Type = AnyInBundle) const { 862 return hasProperty(MCID::IndirectBranch, Type); 863 } 864 865 /// Return true if this is a branch which may fall 866 /// through to the next instruction or may transfer control flow to some other 867 /// block. The TargetInstrInfo::analyzeBranch method can be used to get more 868 /// information about this branch. 869 bool isConditionalBranch(QueryType Type = AnyInBundle) const { 870 return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type); 871 } 872 873 /// Return true if this is a branch which always 874 /// transfers control flow to some other block. The 875 /// TargetInstrInfo::analyzeBranch method can be used to get more information 876 /// about this branch. 877 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { 878 return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type); 879 } 880 881 /// Return true if this instruction has a predicate operand that 882 /// controls execution. It may be set to 'always', or may be set to other 883 /// values. There are various methods in TargetInstrInfo that can be used to 884 /// control and modify the predicate in this instruction. 885 bool isPredicable(QueryType Type = AllInBundle) const { 886 // If it's a bundle than all bundled instructions must be predicable for this 887 // to return true. 888 return hasProperty(MCID::Predicable, Type); 889 } 890 891 /// Return true if this instruction is a comparison. 892 bool isCompare(QueryType Type = IgnoreBundle) const { 893 return hasProperty(MCID::Compare, Type); 894 } 895 896 /// Return true if this instruction is a move immediate 897 /// (including conditional moves) instruction. 898 bool isMoveImmediate(QueryType Type = IgnoreBundle) const { 899 return hasProperty(MCID::MoveImm, Type); 900 } 901 902 /// Return true if this instruction is a register move. 903 /// (including moving values from subreg to reg) 904 bool isMoveReg(QueryType Type = IgnoreBundle) const { 905 return hasProperty(MCID::MoveReg, Type); 906 } 907 908 /// Return true if this instruction is a bitcast instruction. 909 bool isBitcast(QueryType Type = IgnoreBundle) const { 910 return hasProperty(MCID::Bitcast, Type); 911 } 912 913 /// Return true if this instruction is a select instruction. 914 bool isSelect(QueryType Type = IgnoreBundle) const { 915 return hasProperty(MCID::Select, Type); 916 } 917 918 /// Return true if this instruction cannot be safely duplicated. 919 /// For example, if the instruction has a unique labels attached 920 /// to it, duplicating it would cause multiple definition errors. 921 bool isNotDuplicable(QueryType Type = AnyInBundle) const { 922 return hasProperty(MCID::NotDuplicable, Type); 923 } 924 925 /// Return true if this instruction is convergent. 926 /// Convergent instructions can not be made control-dependent on any 927 /// additional values. 928 bool isConvergent(QueryType Type = AnyInBundle) const { 929 if (isInlineAsm()) { 930 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 931 if (ExtraInfo & InlineAsm::Extra_IsConvergent) 932 return true; 933 } 934 return hasProperty(MCID::Convergent, Type); 935 } 936 937 /// Returns true if the specified instruction has a delay slot 938 /// which must be filled by the code generator. 939 bool hasDelaySlot(QueryType Type = AnyInBundle) const { 940 return hasProperty(MCID::DelaySlot, Type); 941 } 942 943 /// Return true for instructions that can be folded as 944 /// memory operands in other instructions. The most common use for this 945 /// is instructions that are simple loads from memory that don't modify 946 /// the loaded value in any way, but it can also be used for instructions 947 /// that can be expressed as constant-pool loads, such as V_SETALLONES 948 /// on x86, to allow them to be folded when it is beneficial. 949 /// This should only be set on instructions that return a value in their 950 /// only virtual register definition. 951 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const { 952 return hasProperty(MCID::FoldableAsLoad, Type); 953 } 954 955 /// Return true if this instruction behaves 956 /// the same way as the generic REG_SEQUENCE instructions. 957 /// E.g., on ARM, 958 /// dX VMOVDRR rY, rZ 959 /// is equivalent to 960 /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. 961 /// 962 /// Note that for the optimizers to be able to take advantage of 963 /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be 964 /// override accordingly. 965 bool isRegSequenceLike(QueryType Type = IgnoreBundle) const { 966 return hasProperty(MCID::RegSequence, Type); 967 } 968 969 /// Return true if this instruction behaves 970 /// the same way as the generic EXTRACT_SUBREG instructions. 971 /// E.g., on ARM, 972 /// rX, rY VMOVRRD dZ 973 /// is equivalent to two EXTRACT_SUBREG: 974 /// rX = EXTRACT_SUBREG dZ, ssub_0 975 /// rY = EXTRACT_SUBREG dZ, ssub_1 976 /// 977 /// Note that for the optimizers to be able to take advantage of 978 /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be 979 /// override accordingly. 980 bool isExtractSubregLike(QueryType Type = IgnoreBundle) const { 981 return hasProperty(MCID::ExtractSubreg, Type); 982 } 983 984 /// Return true if this instruction behaves 985 /// the same way as the generic INSERT_SUBREG instructions. 986 /// E.g., on ARM, 987 /// dX = VSETLNi32 dY, rZ, Imm 988 /// is equivalent to a INSERT_SUBREG: 989 /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) 990 /// 991 /// Note that for the optimizers to be able to take advantage of 992 /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be 993 /// override accordingly. 994 bool isInsertSubregLike(QueryType Type = IgnoreBundle) const { 995 return hasProperty(MCID::InsertSubreg, Type); 996 } 997 998 //===--------------------------------------------------------------------===// 999 // Side Effect Analysis 1000 //===--------------------------------------------------------------------===// 1001 1002 /// Return true if this instruction could possibly read memory. 1003 /// Instructions with this flag set are not necessarily simple load 1004 /// instructions, they may load a value and modify it, for example. 1005 bool mayLoad(QueryType Type = AnyInBundle) const { 1006 if (isInlineAsm()) { 1007 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1008 if (ExtraInfo & InlineAsm::Extra_MayLoad) 1009 return true; 1010 } 1011 return hasProperty(MCID::MayLoad, Type); 1012 } 1013 1014 /// Return true if this instruction could possibly modify memory. 1015 /// Instructions with this flag set are not necessarily simple store 1016 /// instructions, they may store a modified value based on their operands, or 1017 /// may not actually modify anything, for example. 1018 bool mayStore(QueryType Type = AnyInBundle) const { 1019 if (isInlineAsm()) { 1020 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); 1021 if (ExtraInfo & InlineAsm::Extra_MayStore) 1022 return true; 1023 } 1024 return hasProperty(MCID::MayStore, Type); 1025 } 1026 1027 /// Return true if this instruction could possibly read or modify memory. 1028 bool mayLoadOrStore(QueryType Type = AnyInBundle) const { 1029 return mayLoad(Type) || mayStore(Type); 1030 } 1031 1032 /// Return true if this instruction could possibly raise a floating-point 1033 /// exception. This is the case if the instruction is a floating-point 1034 /// instruction that can in principle raise an exception, as indicated 1035 /// by the MCID::MayRaiseFPException property, *and* at the same time, 1036 /// the instruction is used in a context where we expect floating-point 1037 /// exceptions are not disabled, as indicated by the NoFPExcept MI flag. 1038 bool mayRaiseFPException() const { 1039 return hasProperty(MCID::MayRaiseFPException) && 1040 !getFlag(MachineInstr::MIFlag::NoFPExcept); 1041 } 1042 1043 //===--------------------------------------------------------------------===// 1044 // Flags that indicate whether an instruction can be modified by a method. 1045 //===--------------------------------------------------------------------===// 1046 1047 /// Return true if this may be a 2- or 3-address 1048 /// instruction (of the form "X = op Y, Z, ..."), which produces the same 1049 /// result if Y and Z are exchanged. If this flag is set, then the 1050 /// TargetInstrInfo::commuteInstruction method may be used to hack on the 1051 /// instruction. 1052 /// 1053 /// Note that this flag may be set on instructions that are only commutable 1054 /// sometimes. In these cases, the call to commuteInstruction will fail. 1055 /// Also note that some instructions require non-trivial modification to 1056 /// commute them. 1057 bool isCommutable(QueryType Type = IgnoreBundle) const { 1058 return hasProperty(MCID::Commutable, Type); 1059 } 1060 1061 /// Return true if this is a 2-address instruction 1062 /// which can be changed into a 3-address instruction if needed. Doing this 1063 /// transformation can be profitable in the register allocator, because it 1064 /// means that the instruction can use a 2-address form if possible, but 1065 /// degrade into a less efficient form if the source and dest register cannot 1066 /// be assigned to the same register. For example, this allows the x86 1067 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which 1068 /// is the same speed as the shift but has bigger code size. 1069 /// 1070 /// If this returns true, then the target must implement the 1071 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which 1072 /// is allowed to fail if the transformation isn't valid for this specific 1073 /// instruction (e.g. shl reg, 4 on x86). 1074 /// 1075 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const { 1076 return hasProperty(MCID::ConvertibleTo3Addr, Type); 1077 } 1078 1079 /// Return true if this instruction requires 1080 /// custom insertion support when the DAG scheduler is inserting it into a 1081 /// machine basic block. If this is true for the instruction, it basically 1082 /// means that it is a pseudo instruction used at SelectionDAG time that is 1083 /// expanded out into magic code by the target when MachineInstrs are formed. 1084 /// 1085 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method 1086 /// is used to insert this into the MachineBasicBlock. 1087 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const { 1088 return hasProperty(MCID::UsesCustomInserter, Type); 1089 } 1090 1091 /// Return true if this instruction requires *adjustment* 1092 /// after instruction selection by calling a target hook. For example, this 1093 /// can be used to fill in ARM 's' optional operand depending on whether 1094 /// the conditional flag register is used. 1095 bool hasPostISelHook(QueryType Type = IgnoreBundle) const { 1096 return hasProperty(MCID::HasPostISelHook, Type); 1097 } 1098 1099 /// Returns true if this instruction is a candidate for remat. 1100 /// This flag is deprecated, please don't use it anymore. If this 1101 /// flag is set, the isReallyTriviallyReMaterializable() method is called to 1102 /// verify the instruction is really rematable. 1103 bool isRematerializable(QueryType Type = AllInBundle) const { 1104 // It's only possible to re-mat a bundle if all bundled instructions are 1105 // re-materializable. 1106 return hasProperty(MCID::Rematerializable, Type); 1107 } 1108 1109 /// Returns true if this instruction has the same cost (or less) than a move 1110 /// instruction. This is useful during certain types of optimizations 1111 /// (e.g., remat during two-address conversion or machine licm) 1112 /// where we would like to remat or hoist the instruction, but not if it costs 1113 /// more than moving the instruction into the appropriate register. Note, we 1114 /// are not marking copies from and to the same register class with this flag. 1115 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { 1116 // Only returns true for a bundle if all bundled instructions are cheap. 1117 return hasProperty(MCID::CheapAsAMove, Type); 1118 } 1119 1120 /// Returns true if this instruction source operands 1121 /// have special register allocation requirements that are not captured by the 1122 /// operand register classes. e.g. ARM::STRD's two source registers must be an 1123 /// even / odd pair, ARM::STM registers have to be in ascending order. 1124 /// Post-register allocation passes should not attempt to change allocations 1125 /// for sources of instructions with this flag. 1126 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const { 1127 return hasProperty(MCID::ExtraSrcRegAllocReq, Type); 1128 } 1129 1130 /// Returns true if this instruction def operands 1131 /// have special register allocation requirements that are not captured by the 1132 /// operand register classes. e.g. ARM::LDRD's two def registers must be an 1133 /// even / odd pair, ARM::LDM registers have to be in ascending order. 1134 /// Post-register allocation passes should not attempt to change allocations 1135 /// for definitions of instructions with this flag. 1136 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const { 1137 return hasProperty(MCID::ExtraDefRegAllocReq, Type); 1138 } 1139 1140 enum MICheckType { 1141 CheckDefs, // Check all operands for equality 1142 CheckKillDead, // Check all operands including kill / dead markers 1143 IgnoreDefs, // Ignore all definitions 1144 IgnoreVRegDefs // Ignore virtual register definitions 1145 }; 1146 1147 /// Return true if this instruction is identical to \p Other. 1148 /// Two instructions are identical if they have the same opcode and all their 1149 /// operands are identical (with respect to MachineOperand::isIdenticalTo()). 1150 /// Note that this means liveness related flags (dead, undef, kill) do not 1151 /// affect the notion of identical. 1152 bool isIdenticalTo(const MachineInstr &Other, 1153 MICheckType Check = CheckDefs) const; 1154 1155 /// Unlink 'this' from the containing basic block, and return it without 1156 /// deleting it. 1157 /// 1158 /// This function can not be used on bundled instructions, use 1159 /// removeFromBundle() to remove individual instructions from a bundle. 1160 MachineInstr *removeFromParent(); 1161 1162 /// Unlink this instruction from its basic block and return it without 1163 /// deleting it. 1164 /// 1165 /// If the instruction is part of a bundle, the other instructions in the 1166 /// bundle remain bundled. 1167 MachineInstr *removeFromBundle(); 1168 1169 /// Unlink 'this' from the containing basic block and delete it. 1170 /// 1171 /// If this instruction is the header of a bundle, the whole bundle is erased. 1172 /// This function can not be used for instructions inside a bundle, use 1173 /// eraseFromBundle() to erase individual bundled instructions. 1174 void eraseFromParent(); 1175 1176 /// Unlink 'this' from the containing basic block and delete it. 1177 /// 1178 /// For all definitions mark their uses in DBG_VALUE nodes 1179 /// as undefined. Otherwise like eraseFromParent(). 1180 void eraseFromParentAndMarkDBGValuesForRemoval(); 1181 1182 /// Unlink 'this' form its basic block and delete it. 1183 /// 1184 /// If the instruction is part of a bundle, the other instructions in the 1185 /// bundle remain bundled. 1186 void eraseFromBundle(); 1187 1188 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } 1189 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } 1190 bool isAnnotationLabel() const { 1191 return getOpcode() == TargetOpcode::ANNOTATION_LABEL; 1192 } 1193 1194 /// Returns true if the MachineInstr represents a label. 1195 bool isLabel() const { 1196 return isEHLabel() || isGCLabel() || isAnnotationLabel(); 1197 } 1198 1199 bool isCFIInstruction() const { 1200 return getOpcode() == TargetOpcode::CFI_INSTRUCTION; 1201 } 1202 1203 bool isPseudoProbe() const { 1204 return getOpcode() == TargetOpcode::PSEUDO_PROBE; 1205 } 1206 1207 // True if the instruction represents a position in the function. 1208 bool isPosition() const { return isLabel() || isCFIInstruction(); } 1209 1210 bool isNonListDebugValue() const { 1211 return getOpcode() == TargetOpcode::DBG_VALUE; 1212 } 1213 bool isDebugValueList() const { 1214 return getOpcode() == TargetOpcode::DBG_VALUE_LIST; 1215 } 1216 bool isDebugValue() const { 1217 return isNonListDebugValue() || isDebugValueList(); 1218 } 1219 bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } 1220 bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; } 1221 bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; } 1222 bool isDebugInstr() const { 1223 return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI(); 1224 } 1225 bool isDebugOrPseudoInstr() const { 1226 return isDebugInstr() || isPseudoProbe(); 1227 } 1228 1229 bool isDebugOffsetImm() const { 1230 return isNonListDebugValue() && getDebugOffset().isImm(); 1231 } 1232 1233 /// A DBG_VALUE is indirect iff the location operand is a register and 1234 /// the offset operand is an immediate. 1235 bool isIndirectDebugValue() const { 1236 return isDebugOffsetImm() && getDebugOperand(0).isReg(); 1237 } 1238 1239 /// A DBG_VALUE is an entry value iff its debug expression contains the 1240 /// DW_OP_LLVM_entry_value operation. 1241 bool isDebugEntryValue() const; 1242 1243 /// Return true if the instruction is a debug value which describes a part of 1244 /// a variable as unavailable. 1245 bool isUndefDebugValue() const { 1246 if (!isDebugValue()) 1247 return false; 1248 // If any $noreg locations are given, this DV is undef. 1249 for (const MachineOperand &Op : debug_operands()) 1250 if (Op.isReg() && !Op.getReg().isValid()) 1251 return true; 1252 return false; 1253 } 1254 1255 bool isPHI() const { 1256 return getOpcode() == TargetOpcode::PHI || 1257 getOpcode() == TargetOpcode::G_PHI; 1258 } 1259 bool isKill() const { return getOpcode() == TargetOpcode::KILL; } 1260 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } 1261 bool isInlineAsm() const { 1262 return getOpcode() == TargetOpcode::INLINEASM || 1263 getOpcode() == TargetOpcode::INLINEASM_BR; 1264 } 1265 1266 /// FIXME: Seems like a layering violation that the AsmDialect, which is X86 1267 /// specific, be attached to a generic MachineInstr. 1268 bool isMSInlineAsm() const { 1269 return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel; 1270 } 1271 1272 bool isStackAligningInlineAsm() const; 1273 InlineAsm::AsmDialect getInlineAsmDialect() const; 1274 1275 bool isInsertSubreg() const { 1276 return getOpcode() == TargetOpcode::INSERT_SUBREG; 1277 } 1278 1279 bool isSubregToReg() const { 1280 return getOpcode() == TargetOpcode::SUBREG_TO_REG; 1281 } 1282 1283 bool isRegSequence() const { 1284 return getOpcode() == TargetOpcode::REG_SEQUENCE; 1285 } 1286 1287 bool isBundle() const { 1288 return getOpcode() == TargetOpcode::BUNDLE; 1289 } 1290 1291 bool isCopy() const { 1292 return getOpcode() == TargetOpcode::COPY; 1293 } 1294 1295 bool isFullCopy() const { 1296 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); 1297 } 1298 1299 bool isExtractSubreg() const { 1300 return getOpcode() == TargetOpcode::EXTRACT_SUBREG; 1301 } 1302 1303 /// Return true if the instruction behaves like a copy. 1304 /// This does not include native copy instructions. 1305 bool isCopyLike() const { 1306 return isCopy() || isSubregToReg(); 1307 } 1308 1309 /// Return true is the instruction is an identity copy. 1310 bool isIdentityCopy() const { 1311 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && 1312 getOperand(0).getSubReg() == getOperand(1).getSubReg(); 1313 } 1314 1315 /// Return true if this instruction doesn't produce any output in the form of 1316 /// executable instructions. 1317 bool isMetaInstruction() const { 1318 switch (getOpcode()) { 1319 default: 1320 return false; 1321 case TargetOpcode::IMPLICIT_DEF: 1322 case TargetOpcode::KILL: 1323 case TargetOpcode::CFI_INSTRUCTION: 1324 case TargetOpcode::EH_LABEL: 1325 case TargetOpcode::GC_LABEL: 1326 case TargetOpcode::DBG_VALUE: 1327 case TargetOpcode::DBG_VALUE_LIST: 1328 case TargetOpcode::DBG_INSTR_REF: 1329 case TargetOpcode::DBG_PHI: 1330 case TargetOpcode::DBG_LABEL: 1331 case TargetOpcode::LIFETIME_START: 1332 case TargetOpcode::LIFETIME_END: 1333 case TargetOpcode::PSEUDO_PROBE: 1334 return true; 1335 } 1336 } 1337 1338 /// Return true if this is a transient instruction that is either very likely 1339 /// to be eliminated during register allocation (such as copy-like 1340 /// instructions), or if this instruction doesn't have an execution-time cost. 1341 bool isTransient() const { 1342 switch (getOpcode()) { 1343 default: 1344 return isMetaInstruction(); 1345 // Copy-like instructions are usually eliminated during register allocation. 1346 case TargetOpcode::PHI: 1347 case TargetOpcode::G_PHI: 1348 case TargetOpcode::COPY: 1349 case TargetOpcode::INSERT_SUBREG: 1350 case TargetOpcode::SUBREG_TO_REG: 1351 case TargetOpcode::REG_SEQUENCE: 1352 return true; 1353 } 1354 } 1355 1356 /// Return the number of instructions inside the MI bundle, excluding the 1357 /// bundle header. 1358 /// 1359 /// This is the number of instructions that MachineBasicBlock::iterator 1360 /// skips, 0 for unbundled instructions. 1361 unsigned getBundleSize() const; 1362 1363 /// Return true if the MachineInstr reads the specified register. 1364 /// If TargetRegisterInfo is passed, then it also checks if there 1365 /// is a read of a super-register. 1366 /// This does not count partial redefines of virtual registers as reads: 1367 /// %reg1024:6 = OP. 1368 bool readsRegister(Register Reg, 1369 const TargetRegisterInfo *TRI = nullptr) const { 1370 return findRegisterUseOperandIdx(Reg, false, TRI) != -1; 1371 } 1372 1373 /// Return true if the MachineInstr reads the specified virtual register. 1374 /// Take into account that a partial define is a 1375 /// read-modify-write operation. 1376 bool readsVirtualRegister(Register Reg) const { 1377 return readsWritesVirtualRegister(Reg).first; 1378 } 1379 1380 /// Return a pair of bools (reads, writes) indicating if this instruction 1381 /// reads or writes Reg. This also considers partial defines. 1382 /// If Ops is not null, all operand indices for Reg are added. 1383 std::pair<bool,bool> readsWritesVirtualRegister(Register Reg, 1384 SmallVectorImpl<unsigned> *Ops = nullptr) const; 1385 1386 /// Return true if the MachineInstr kills the specified register. 1387 /// If TargetRegisterInfo is passed, then it also checks if there is 1388 /// a kill of a super-register. 1389 bool killsRegister(Register Reg, 1390 const TargetRegisterInfo *TRI = nullptr) const { 1391 return findRegisterUseOperandIdx(Reg, true, TRI) != -1; 1392 } 1393 1394 /// Return true if the MachineInstr fully defines the specified register. 1395 /// If TargetRegisterInfo is passed, then it also checks 1396 /// if there is a def of a super-register. 1397 /// NOTE: It's ignoring subreg indices on virtual registers. 1398 bool definesRegister(Register Reg, 1399 const TargetRegisterInfo *TRI = nullptr) const { 1400 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; 1401 } 1402 1403 /// Return true if the MachineInstr modifies (fully define or partially 1404 /// define) the specified register. 1405 /// NOTE: It's ignoring subreg indices on virtual registers. 1406 bool modifiesRegister(Register Reg, 1407 const TargetRegisterInfo *TRI = nullptr) const { 1408 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; 1409 } 1410 1411 /// Returns true if the register is dead in this machine instruction. 1412 /// If TargetRegisterInfo is passed, then it also checks 1413 /// if there is a dead def of a super-register. 1414 bool registerDefIsDead(Register Reg, 1415 const TargetRegisterInfo *TRI = nullptr) const { 1416 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; 1417 } 1418 1419 /// Returns true if the MachineInstr has an implicit-use operand of exactly 1420 /// the given register (not considering sub/super-registers). 1421 bool hasRegisterImplicitUseOperand(Register Reg) const; 1422 1423 /// Returns the operand index that is a use of the specific register or -1 1424 /// if it is not found. It further tightens the search criteria to a use 1425 /// that kills the register if isKill is true. 1426 int findRegisterUseOperandIdx(Register Reg, bool isKill = false, 1427 const TargetRegisterInfo *TRI = nullptr) const; 1428 1429 /// Wrapper for findRegisterUseOperandIdx, it returns 1430 /// a pointer to the MachineOperand rather than an index. 1431 MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false, 1432 const TargetRegisterInfo *TRI = nullptr) { 1433 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); 1434 return (Idx == -1) ? nullptr : &getOperand(Idx); 1435 } 1436 1437 const MachineOperand *findRegisterUseOperand( 1438 Register Reg, bool isKill = false, 1439 const TargetRegisterInfo *TRI = nullptr) const { 1440 return const_cast<MachineInstr *>(this)-> 1441 findRegisterUseOperand(Reg, isKill, TRI); 1442 } 1443 1444 /// Returns the operand index that is a def of the specified register or 1445 /// -1 if it is not found. If isDead is true, defs that are not dead are 1446 /// skipped. If Overlap is true, then it also looks for defs that merely 1447 /// overlap the specified register. If TargetRegisterInfo is non-null, 1448 /// then it also checks if there is a def of a super-register. 1449 /// This may also return a register mask operand when Overlap is true. 1450 int findRegisterDefOperandIdx(Register Reg, 1451 bool isDead = false, bool Overlap = false, 1452 const TargetRegisterInfo *TRI = nullptr) const; 1453 1454 /// Wrapper for findRegisterDefOperandIdx, it returns 1455 /// a pointer to the MachineOperand rather than an index. 1456 MachineOperand * 1457 findRegisterDefOperand(Register Reg, bool isDead = false, 1458 bool Overlap = false, 1459 const TargetRegisterInfo *TRI = nullptr) { 1460 int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI); 1461 return (Idx == -1) ? nullptr : &getOperand(Idx); 1462 } 1463 1464 const MachineOperand * 1465 findRegisterDefOperand(Register Reg, bool isDead = false, 1466 bool Overlap = false, 1467 const TargetRegisterInfo *TRI = nullptr) const { 1468 return const_cast<MachineInstr *>(this)->findRegisterDefOperand( 1469 Reg, isDead, Overlap, TRI); 1470 } 1471 1472 /// Find the index of the first operand in the 1473 /// operand list that is used to represent the predicate. It returns -1 if 1474 /// none is found. 1475 int findFirstPredOperandIdx() const; 1476 1477 /// Find the index of the flag word operand that 1478 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if 1479 /// getOperand(OpIdx) does not belong to an inline asm operand group. 1480 /// 1481 /// If GroupNo is not NULL, it will receive the number of the operand group 1482 /// containing OpIdx. 1483 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; 1484 1485 /// Compute the static register class constraint for operand OpIdx. 1486 /// For normal instructions, this is derived from the MCInstrDesc. 1487 /// For inline assembly it is derived from the flag words. 1488 /// 1489 /// Returns NULL if the static register class constraint cannot be 1490 /// determined. 1491 const TargetRegisterClass* 1492 getRegClassConstraint(unsigned OpIdx, 1493 const TargetInstrInfo *TII, 1494 const TargetRegisterInfo *TRI) const; 1495 1496 /// Applies the constraints (def/use) implied by this MI on \p Reg to 1497 /// the given \p CurRC. 1498 /// If \p ExploreBundle is set and MI is part of a bundle, all the 1499 /// instructions inside the bundle will be taken into account. In other words, 1500 /// this method accumulates all the constraints of the operand of this MI and 1501 /// the related bundle if MI is a bundle or inside a bundle. 1502 /// 1503 /// Returns the register class that satisfies both \p CurRC and the 1504 /// constraints set by MI. Returns NULL if such a register class does not 1505 /// exist. 1506 /// 1507 /// \pre CurRC must not be NULL. 1508 const TargetRegisterClass *getRegClassConstraintEffectForVReg( 1509 Register Reg, const TargetRegisterClass *CurRC, 1510 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, 1511 bool ExploreBundle = false) const; 1512 1513 /// Applies the constraints (def/use) implied by the \p OpIdx operand 1514 /// to the given \p CurRC. 1515 /// 1516 /// Returns the register class that satisfies both \p CurRC and the 1517 /// constraints set by \p OpIdx MI. Returns NULL if such a register class 1518 /// does not exist. 1519 /// 1520 /// \pre CurRC must not be NULL. 1521 /// \pre The operand at \p OpIdx must be a register. 1522 const TargetRegisterClass * 1523 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, 1524 const TargetInstrInfo *TII, 1525 const TargetRegisterInfo *TRI) const; 1526 1527 /// Add a tie between the register operands at DefIdx and UseIdx. 1528 /// The tie will cause the register allocator to ensure that the two 1529 /// operands are assigned the same physical register. 1530 /// 1531 /// Tied operands are managed automatically for explicit operands in the 1532 /// MCInstrDesc. This method is for exceptional cases like inline asm. 1533 void tieOperands(unsigned DefIdx, unsigned UseIdx); 1534 1535 /// Given the index of a tied register operand, find the 1536 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the 1537 /// index of the tied operand which must exist. 1538 unsigned findTiedOperandIdx(unsigned OpIdx) const; 1539 1540 /// Given the index of a register def operand, 1541 /// check if the register def is tied to a source operand, due to either 1542 /// two-address elimination or inline assembly constraints. Returns the 1543 /// first tied use operand index by reference if UseOpIdx is not null. 1544 bool isRegTiedToUseOperand(unsigned DefOpIdx, 1545 unsigned *UseOpIdx = nullptr) const { 1546 const MachineOperand &MO = getOperand(DefOpIdx); 1547 if (!MO.isReg() || !MO.isDef() || !MO.isTied()) 1548 return false; 1549 if (UseOpIdx) 1550 *UseOpIdx = findTiedOperandIdx(DefOpIdx); 1551 return true; 1552 } 1553 1554 /// Return true if the use operand of the specified index is tied to a def 1555 /// operand. It also returns the def operand index by reference if DefOpIdx 1556 /// is not null. 1557 bool isRegTiedToDefOperand(unsigned UseOpIdx, 1558 unsigned *DefOpIdx = nullptr) const { 1559 const MachineOperand &MO = getOperand(UseOpIdx); 1560 if (!MO.isReg() || !MO.isUse() || !MO.isTied()) 1561 return false; 1562 if (DefOpIdx) 1563 *DefOpIdx = findTiedOperandIdx(UseOpIdx); 1564 return true; 1565 } 1566 1567 /// Clears kill flags on all operands. 1568 void clearKillInfo(); 1569 1570 /// Replace all occurrences of FromReg with ToReg:SubIdx, 1571 /// properly composing subreg indices where necessary. 1572 void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, 1573 const TargetRegisterInfo &RegInfo); 1574 1575 /// We have determined MI kills a register. Look for the 1576 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, 1577 /// add a implicit operand if it's not found. Returns true if the operand 1578 /// exists / is added. 1579 bool addRegisterKilled(Register IncomingReg, 1580 const TargetRegisterInfo *RegInfo, 1581 bool AddIfNotFound = false); 1582 1583 /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes 1584 /// all aliasing registers. 1585 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo); 1586 1587 /// We have determined MI defined a register without a use. 1588 /// Look for the operand that defines it and mark it as IsDead. If 1589 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns 1590 /// true if the operand exists / is added. 1591 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, 1592 bool AddIfNotFound = false); 1593 1594 /// Clear all dead flags on operands defining register @p Reg. 1595 void clearRegisterDeads(Register Reg); 1596 1597 /// Mark all subregister defs of register @p Reg with the undef flag. 1598 /// This function is used when we determined to have a subregister def in an 1599 /// otherwise undefined super register. 1600 void setRegisterDefReadUndef(Register Reg, bool IsUndef = true); 1601 1602 /// We have determined MI defines a register. Make sure there is an operand 1603 /// defining Reg. 1604 void addRegisterDefined(Register Reg, 1605 const TargetRegisterInfo *RegInfo = nullptr); 1606 1607 /// Mark every physreg used by this instruction as 1608 /// dead except those in the UsedRegs list. 1609 /// 1610 /// On instructions with register mask operands, also add implicit-def 1611 /// operands for all registers in UsedRegs. 1612 void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, 1613 const TargetRegisterInfo &TRI); 1614 1615 /// Return true if it is safe to move this instruction. If 1616 /// SawStore is set to true, it means that there is a store (or call) between 1617 /// the instruction's location and its intended destination. 1618 bool isSafeToMove(AAResults *AA, bool &SawStore) const; 1619 1620 /// Returns true if this instruction's memory access aliases the memory 1621 /// access of Other. 1622 // 1623 /// Assumes any physical registers used to compute addresses 1624 /// have the same value for both instructions. Returns false if neither 1625 /// instruction writes to memory. 1626 /// 1627 /// @param AA Optional alias analysis, used to compare memory operands. 1628 /// @param Other MachineInstr to check aliasing against. 1629 /// @param UseTBAA Whether to pass TBAA information to alias analysis. 1630 bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const; 1631 1632 /// Return true if this instruction may have an ordered 1633 /// or volatile memory reference, or if the information describing the memory 1634 /// reference is not available. Return false if it is known to have no 1635 /// ordered or volatile memory references. 1636 bool hasOrderedMemoryRef() const; 1637 1638 /// Return true if this load instruction never traps and points to a memory 1639 /// location whose value doesn't change during the execution of this function. 1640 /// 1641 /// Examples include loading a value from the constant pool or from the 1642 /// argument area of a function (if it does not change). If the instruction 1643 /// does multiple loads, this returns true only if all of the loads are 1644 /// dereferenceable and invariant. 1645 bool isDereferenceableInvariantLoad(AAResults *AA) const; 1646 1647 /// If the specified instruction is a PHI that always merges together the 1648 /// same virtual register, return the register, otherwise return 0. 1649 unsigned isConstantValuePHI() const; 1650 1651 /// Return true if this instruction has side effects that are not modeled 1652 /// by mayLoad / mayStore, etc. 1653 /// For all instructions, the property is encoded in MCInstrDesc::Flags 1654 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is 1655 /// INLINEASM instruction, in which case the side effect property is encoded 1656 /// in one of its operands (see InlineAsm::Extra_HasSideEffect). 1657 /// 1658 bool hasUnmodeledSideEffects() const; 1659 1660 /// Returns true if it is illegal to fold a load across this instruction. 1661 bool isLoadFoldBarrier() const; 1662 1663 /// Return true if all the defs of this instruction are dead. 1664 bool allDefsAreDead() const; 1665 1666 /// Return a valid size if the instruction is a spill instruction. 1667 Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const; 1668 1669 /// Return a valid size if the instruction is a folded spill instruction. 1670 Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const; 1671 1672 /// Return a valid size if the instruction is a restore instruction. 1673 Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const; 1674 1675 /// Return a valid size if the instruction is a folded restore instruction. 1676 Optional<unsigned> 1677 getFoldedRestoreSize(const TargetInstrInfo *TII) const; 1678 1679 /// Copy implicit register operands from specified 1680 /// instruction to this instruction. 1681 void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI); 1682 1683 /// Debugging support 1684 /// @{ 1685 /// Determine the generic type to be printed (if needed) on uses and defs. 1686 LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, 1687 const MachineRegisterInfo &MRI) const; 1688 1689 /// Return true when an instruction has tied register that can't be determined 1690 /// by the instruction's descriptor. This is useful for MIR printing, to 1691 /// determine whether we need to print the ties or not. 1692 bool hasComplexRegisterTies() const; 1693 1694 /// Print this MI to \p OS. 1695 /// Don't print information that can be inferred from other instructions if 1696 /// \p IsStandalone is false. It is usually true when only a fragment of the 1697 /// function is printed. 1698 /// Only print the defs and the opcode if \p SkipOpers is true. 1699 /// Otherwise, also print operands if \p SkipDebugLoc is true. 1700 /// Otherwise, also print the debug loc, with a terminating newline. 1701 /// \p TII is used to print the opcode name. If it's not present, but the 1702 /// MI is in a function, the opcode will be printed using the function's TII. 1703 void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false, 1704 bool SkipDebugLoc = false, bool AddNewLine = true, 1705 const TargetInstrInfo *TII = nullptr) const; 1706 void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true, 1707 bool SkipOpers = false, bool SkipDebugLoc = false, 1708 bool AddNewLine = true, 1709 const TargetInstrInfo *TII = nullptr) const; 1710 void dump() const; 1711 /// Print on dbgs() the current instruction and the instructions defining its 1712 /// operands and so on until we reach \p MaxDepth. 1713 void dumpr(const MachineRegisterInfo &MRI, 1714 unsigned MaxDepth = UINT_MAX) const; 1715 /// @} 1716 1717 //===--------------------------------------------------------------------===// 1718 // Accessors used to build up machine instructions. 1719 1720 /// Add the specified operand to the instruction. If it is an implicit 1721 /// operand, it is added to the end of the operand list. If it is an 1722 /// explicit operand it is added at the end of the explicit operand list 1723 /// (before the first implicit operand). 1724 /// 1725 /// MF must be the machine function that was used to allocate this 1726 /// instruction. 1727 /// 1728 /// MachineInstrBuilder provides a more convenient interface for creating 1729 /// instructions and adding operands. 1730 void addOperand(MachineFunction &MF, const MachineOperand &Op); 1731 1732 /// Add an operand without providing an MF reference. This only works for 1733 /// instructions that are inserted in a basic block. 1734 /// 1735 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be 1736 /// preferred. 1737 void addOperand(const MachineOperand &Op); 1738 1739 /// Replace the instruction descriptor (thus opcode) of 1740 /// the current instruction with a new one. 1741 void setDesc(const MCInstrDesc &tid) { MCID = &tid; } 1742 1743 /// Replace current source information with new such. 1744 /// Avoid using this, the constructor argument is preferable. 1745 void setDebugLoc(DebugLoc dl) { 1746 debugLoc = std::move(dl); 1747 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); 1748 } 1749 1750 /// Erase an operand from an instruction, leaving it with one 1751 /// fewer operand than it started with. 1752 void RemoveOperand(unsigned OpNo); 1753 1754 /// Clear this MachineInstr's memory reference descriptor list. This resets 1755 /// the memrefs to their most conservative state. This should be used only 1756 /// as a last resort since it greatly pessimizes our knowledge of the memory 1757 /// access performed by the instruction. 1758 void dropMemRefs(MachineFunction &MF); 1759 1760 /// Assign this MachineInstr's memory reference descriptor list. 1761 /// 1762 /// Unlike other methods, this *will* allocate them into a new array 1763 /// associated with the provided `MachineFunction`. 1764 void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs); 1765 1766 /// Add a MachineMemOperand to the machine instruction. 1767 /// This function should be used only occasionally. The setMemRefs function 1768 /// is the primary method for setting up a MachineInstr's MemRefs list. 1769 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); 1770 1771 /// Clone another MachineInstr's memory reference descriptor list and replace 1772 /// ours with it. 1773 /// 1774 /// Note that `*this` may be the incoming MI! 1775 /// 1776 /// Prefer this API whenever possible as it can avoid allocations in common 1777 /// cases. 1778 void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI); 1779 1780 /// Clone the merge of multiple MachineInstrs' memory reference descriptors 1781 /// list and replace ours with it. 1782 /// 1783 /// Note that `*this` may be one of the incoming MIs! 1784 /// 1785 /// Prefer this API whenever possible as it can avoid allocations in common 1786 /// cases. 1787 void cloneMergedMemRefs(MachineFunction &MF, 1788 ArrayRef<const MachineInstr *> MIs); 1789 1790 /// Set a symbol that will be emitted just prior to the instruction itself. 1791 /// 1792 /// Setting this to a null pointer will remove any such symbol. 1793 /// 1794 /// FIXME: This is not fully implemented yet. 1795 void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); 1796 1797 /// Set a symbol that will be emitted just after the instruction itself. 1798 /// 1799 /// Setting this to a null pointer will remove any such symbol. 1800 /// 1801 /// FIXME: This is not fully implemented yet. 1802 void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); 1803 1804 /// Clone another MachineInstr's pre- and post- instruction symbols and 1805 /// replace ours with it. 1806 void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI); 1807 1808 /// Set a marker on instructions that denotes where we should create and emit 1809 /// heap alloc site labels. This waits until after instruction selection and 1810 /// optimizations to create the label, so it should still work if the 1811 /// instruction is removed or duplicated. 1812 void setHeapAllocMarker(MachineFunction &MF, MDNode *MD); 1813 1814 /// Return the MIFlags which represent both MachineInstrs. This 1815 /// should be used when merging two MachineInstrs into one. This routine does 1816 /// not modify the MIFlags of this MachineInstr. 1817 uint16_t mergeFlagsWith(const MachineInstr& Other) const; 1818 1819 static uint16_t copyFlagsFromInstruction(const Instruction &I); 1820 1821 /// Copy all flags to MachineInst MIFlags 1822 void copyIRFlags(const Instruction &I); 1823 1824 /// Break any tie involving OpIdx. 1825 void untieRegOperand(unsigned OpIdx) { 1826 MachineOperand &MO = getOperand(OpIdx); 1827 if (MO.isReg() && MO.isTied()) { 1828 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0; 1829 MO.TiedTo = 0; 1830 } 1831 } 1832 1833 /// Add all implicit def and use operands to this instruction. 1834 void addImplicitDefUseOperands(MachineFunction &MF); 1835 1836 /// Scan instructions immediately following MI and collect any matching 1837 /// DBG_VALUEs. 1838 void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues); 1839 1840 /// Find all DBG_VALUEs that point to the register def in this instruction 1841 /// and point them to \p Reg instead. 1842 void changeDebugValuesDefReg(Register Reg); 1843 1844 /// Returns the Intrinsic::ID for this instruction. 1845 /// \pre Must have an intrinsic ID operand. 1846 unsigned getIntrinsicID() const { 1847 return getOperand(getNumExplicitDefs()).getIntrinsicID(); 1848 } 1849 1850 /// Sets all register debug operands in this debug value instruction to be 1851 /// undef. 1852 void setDebugValueUndef() { 1853 assert(isDebugValue() && "Must be a debug value instruction."); 1854 for (MachineOperand &MO : debug_operands()) { 1855 if (MO.isReg()) { 1856 MO.setReg(0); 1857 MO.setSubReg(0); 1858 } 1859 } 1860 } 1861 1862 PseudoProbeAttributes getPseudoProbeAttribute() const { 1863 assert(isPseudoProbe() && "Must be a pseudo probe instruction"); 1864 return (PseudoProbeAttributes)getOperand(3).getImm(); 1865 } 1866 1867 void addPseudoProbeAttribute(PseudoProbeAttributes Attr) { 1868 assert(isPseudoProbe() && "Must be a pseudo probe instruction"); 1869 MachineOperand &AttrOperand = getOperand(3); 1870 AttrOperand.setImm(AttrOperand.getImm() | (uint32_t)Attr); 1871 } 1872 1873 private: 1874 /// If this instruction is embedded into a MachineFunction, return the 1875 /// MachineRegisterInfo object for the current function, otherwise 1876 /// return null. 1877 MachineRegisterInfo *getRegInfo(); 1878 1879 /// Unlink all of the register operands in this instruction from their 1880 /// respective use lists. This requires that the operands already be on their 1881 /// use lists. 1882 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); 1883 1884 /// Add all of the register operands in this instruction from their 1885 /// respective use lists. This requires that the operands not be on their 1886 /// use lists yet. 1887 void AddRegOperandsToUseLists(MachineRegisterInfo&); 1888 1889 /// Slow path for hasProperty when we're dealing with a bundle. 1890 bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const; 1891 1892 /// Implements the logic of getRegClassConstraintEffectForVReg for the 1893 /// this MI and the given operand index \p OpIdx. 1894 /// If the related operand does not constrained Reg, this returns CurRC. 1895 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl( 1896 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, 1897 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; 1898 1899 /// Stores extra instruction information inline or allocates as ExtraInfo 1900 /// based on the number of pointers. 1901 void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs, 1902 MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol, 1903 MDNode *HeapAllocMarker); 1904 }; 1905 1906 /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the 1907 /// instruction rather than by pointer value. 1908 /// The hashing and equality testing functions ignore definitions so this is 1909 /// useful for CSE, etc. 1910 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { 1911 static inline MachineInstr *getEmptyKey() { 1912 return nullptr; 1913 } 1914 1915 static inline MachineInstr *getTombstoneKey() { 1916 return reinterpret_cast<MachineInstr*>(-1); 1917 } 1918 1919 static unsigned getHashValue(const MachineInstr* const &MI); 1920 1921 static bool isEqual(const MachineInstr* const &LHS, 1922 const MachineInstr* const &RHS) { 1923 if (RHS == getEmptyKey() || RHS == getTombstoneKey() || 1924 LHS == getEmptyKey() || LHS == getTombstoneKey()) 1925 return LHS == RHS; 1926 return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs); 1927 } 1928 }; 1929 1930 //===----------------------------------------------------------------------===// 1931 // Debugging Support 1932 1933 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { 1934 MI.print(OS); 1935 return OS; 1936 } 1937 1938 } // end namespace llvm 1939 1940 #endif // LLVM_CODEGEN_MACHINEINSTR_H 1941