1//===- IntrinsicsARM.td - Defines ARM intrinsics -----------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines all of the ARM-specific intrinsics.
10//
11//===----------------------------------------------------------------------===//
12
13
14//===----------------------------------------------------------------------===//
15// TLS
16
17let TargetPrefix = "arm" in {  // All intrinsics start with "llvm.arm.".
18
19// A space-consuming intrinsic primarily for testing ARMConstantIslands. The
20// first argument is the number of bytes this "instruction" takes up, the second
21// and return value are essentially chains, used to force ordering during ISel.
22def int_arm_space : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>]>;
23
24// 16-bit multiplications
25def int_arm_smulbb : GCCBuiltin<"__builtin_arm_smulbb">,
26    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
27def int_arm_smulbt : GCCBuiltin<"__builtin_arm_smulbt">,
28    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
29def int_arm_smultb : GCCBuiltin<"__builtin_arm_smultb">,
30    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
31def int_arm_smultt : GCCBuiltin<"__builtin_arm_smultt">,
32    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
33def int_arm_smulwb : GCCBuiltin<"__builtin_arm_smulwb">,
34    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
35def int_arm_smulwt : GCCBuiltin<"__builtin_arm_smulwt">,
36    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
37
38//===----------------------------------------------------------------------===//
39// Saturating Arithmetic
40
41def int_arm_qadd : GCCBuiltin<"__builtin_arm_qadd">,
42    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
43    [Commutative, IntrNoMem]>;
44def int_arm_qsub : GCCBuiltin<"__builtin_arm_qsub">,
45    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
46def int_arm_ssat : GCCBuiltin<"__builtin_arm_ssat">,
47    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
48def int_arm_usat : GCCBuiltin<"__builtin_arm_usat">,
49    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
50
51// Accumulating multiplications
52def int_arm_smlabb : GCCBuiltin<"__builtin_arm_smlabb">,
53    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
54    [IntrNoMem]>;
55def int_arm_smlabt : GCCBuiltin<"__builtin_arm_smlabt">,
56    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
57    [IntrNoMem]>;
58def int_arm_smlatb : GCCBuiltin<"__builtin_arm_smlatb">,
59    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
60    [IntrNoMem]>;
61def int_arm_smlatt : GCCBuiltin<"__builtin_arm_smlatt">,
62    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
63    [IntrNoMem]>;
64def int_arm_smlawb : GCCBuiltin<"__builtin_arm_smlawb">,
65    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
66    [IntrNoMem]>;
67def int_arm_smlawt : GCCBuiltin<"__builtin_arm_smlawt">,
68    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
69    [IntrNoMem]>;
70
71// Parallel 16-bit saturation
72def int_arm_ssat16 : GCCBuiltin<"__builtin_arm_ssat16">,
73    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
74def int_arm_usat16 : GCCBuiltin<"__builtin_arm_usat16">,
75    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
76
77// Packing and unpacking
78def int_arm_sxtab16 : GCCBuiltin<"__builtin_arm_sxtab16">,
79    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
80def int_arm_sxtb16 : GCCBuiltin<"__builtin_arm_sxtb16">,
81    Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
82def int_arm_uxtab16 : GCCBuiltin<"__builtin_arm_uxtab16">,
83    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
84def int_arm_uxtb16 : GCCBuiltin<"__builtin_arm_uxtb16">,
85    Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
86
87// Parallel selection, reads the GE flags.
88def int_arm_sel : GCCBuiltin<"__builtin_arm_sel">,
89    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrReadMem]>;
90
91// Parallel 8-bit addition and subtraction
92def int_arm_qadd8  : GCCBuiltin<"__builtin_arm_qadd8">,
93    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
94def int_arm_qsub8  : GCCBuiltin<"__builtin_arm_qsub8">,
95    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
96// Writes to the GE bits.
97def int_arm_sadd8  : GCCBuiltin<"__builtin_arm_sadd8">,
98    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
99def int_arm_shadd8  : GCCBuiltin<"__builtin_arm_shadd8">,
100    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
101def int_arm_shsub8  : GCCBuiltin<"__builtin_arm_shsub8">,
102    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
103// Writes to the GE bits.
104def int_arm_ssub8  : GCCBuiltin<"__builtin_arm_ssub8">,
105    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
106// Writes to the GE bits.
107def int_arm_uadd8  : GCCBuiltin<"__builtin_arm_uadd8">,
108    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
109def int_arm_uhadd8  : GCCBuiltin<"__builtin_arm_uhadd8">,
110    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
111def int_arm_uhsub8  : GCCBuiltin<"__builtin_arm_uhsub8">,
112    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
113def int_arm_uqadd8  : GCCBuiltin<"__builtin_arm_uqadd8">,
114    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
115def int_arm_uqsub8  : GCCBuiltin<"__builtin_arm_uqsub8">,
116    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
117// Writes to the GE bits.
118def int_arm_usub8  : GCCBuiltin<"__builtin_arm_usub8">,
119    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
120
121// Sum of 8-bit absolute differences
122def int_arm_usad8  : GCCBuiltin<"__builtin_arm_usad8">,
123    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
124def int_arm_usada8  : GCCBuiltin<"__builtin_arm_usada8">,
125    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
126              [IntrNoMem]>;
127
128// Parallel 16-bit addition and subtraction
129def int_arm_qadd16  : GCCBuiltin<"__builtin_arm_qadd16">,
130    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
131def int_arm_qasx  : GCCBuiltin<"__builtin_arm_qasx">,
132    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
133def int_arm_qsax  : GCCBuiltin<"__builtin_arm_qsax">,
134    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
135def int_arm_qsub16  : GCCBuiltin<"__builtin_arm_qsub16">,
136    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
137// Writes to the GE bits.
138def int_arm_sadd16  : GCCBuiltin<"__builtin_arm_sadd16">,
139    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
140// Writes to the GE bits.
141def int_arm_sasx  : GCCBuiltin<"__builtin_arm_sasx">,
142    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
143def int_arm_shadd16  : GCCBuiltin<"__builtin_arm_shadd16">,
144    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
145def int_arm_shasx  : GCCBuiltin<"__builtin_arm_shasx">,
146    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
147def int_arm_shsax  : GCCBuiltin<"__builtin_arm_shsax">,
148    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
149def int_arm_shsub16  : GCCBuiltin<"__builtin_arm_shsub16">,
150    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
151// Writes to the GE bits.
152def int_arm_ssax  : GCCBuiltin<"__builtin_arm_ssax">,
153    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
154// Writes to the GE bits.
155def int_arm_ssub16  : GCCBuiltin<"__builtin_arm_ssub16">,
156    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
157// Writes to the GE bits.
158def int_arm_uadd16  : GCCBuiltin<"__builtin_arm_uadd16">,
159    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
160// Writes to the GE bits.
161def int_arm_uasx  : GCCBuiltin<"__builtin_arm_uasx">,
162    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
163def int_arm_uhadd16  : GCCBuiltin<"__builtin_arm_uhadd16">,
164    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
165def int_arm_uhasx  : GCCBuiltin<"__builtin_arm_uhasx">,
166    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
167def int_arm_uhsax  : GCCBuiltin<"__builtin_arm_uhsax">,
168    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
169def int_arm_uhsub16  : GCCBuiltin<"__builtin_arm_uhsub16">,
170    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
171def int_arm_uqadd16  : GCCBuiltin<"__builtin_arm_uqadd16">,
172    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
173def int_arm_uqasx  : GCCBuiltin<"__builtin_arm_uqasx">,
174    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
175def int_arm_uqsax  : GCCBuiltin<"__builtin_arm_uqsax">,
176    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
177def int_arm_uqsub16  : GCCBuiltin<"__builtin_arm_uqsub16">,
178    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
179// Writes to the GE bits.
180def int_arm_usax  : GCCBuiltin<"__builtin_arm_usax">,
181    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
182// Writes to the GE bits.
183def int_arm_usub16  : GCCBuiltin<"__builtin_arm_usub16">,
184    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], []>;
185
186// Parallel 16-bit multiplication
187def int_arm_smlad : GCCBuiltin<"__builtin_arm_smlad">,
188    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
189              [IntrNoMem]>;
190def int_arm_smladx : GCCBuiltin<"__builtin_arm_smladx">,
191    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
192              [IntrNoMem]>;
193def int_arm_smlald : GCCBuiltin<"__builtin_arm_smlald">,
194    Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
195              [IntrNoMem]>;
196def int_arm_smlaldx : GCCBuiltin<"__builtin_arm_smlaldx">,
197    Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
198              [IntrNoMem]>;
199def int_arm_smlsd : GCCBuiltin<"__builtin_arm_smlsd">,
200    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
201              [IntrNoMem]>;
202def int_arm_smlsdx : GCCBuiltin<"__builtin_arm_smlsdx">,
203    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
204              [IntrNoMem]>;
205def int_arm_smlsld : GCCBuiltin<"__builtin_arm_smlsld">,
206    Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
207              [IntrNoMem]>;
208def int_arm_smlsldx : GCCBuiltin<"__builtin_arm_smlsldx">,
209    Intrinsic<[llvm_i64_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i64_ty],
210              [IntrNoMem]>;
211def int_arm_smuad : GCCBuiltin<"__builtin_arm_smuad">,
212    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
213def int_arm_smuadx : GCCBuiltin<"__builtin_arm_smuadx">,
214    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
215def int_arm_smusd : GCCBuiltin<"__builtin_arm_smusd">,
216    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
217def int_arm_smusdx : GCCBuiltin<"__builtin_arm_smusdx">,
218    Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
219
220
221//===----------------------------------------------------------------------===//
222// Load, Store and Clear exclusive
223
224def int_arm_ldrex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
225def int_arm_strex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
226
227def int_arm_ldaex : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
228def int_arm_stlex : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_anyptr_ty]>;
229
230def int_arm_clrex : Intrinsic<[]>;
231
232def int_arm_strexd : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty,
233    llvm_ptr_ty]>;
234def int_arm_ldrexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
235
236def int_arm_stlexd : Intrinsic<[llvm_i32_ty],
237                               [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty]>;
238def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
239
240//===----------------------------------------------------------------------===//
241// Data barrier instructions
242def int_arm_dmb : GCCBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
243                  Intrinsic<[], [llvm_i32_ty]>;
244def int_arm_dsb : GCCBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
245                  Intrinsic<[], [llvm_i32_ty]>;
246def int_arm_isb : GCCBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
247                  Intrinsic<[], [llvm_i32_ty]>;
248
249//===----------------------------------------------------------------------===//
250// VFP
251
252def int_arm_get_fpscr : GCCBuiltin<"__builtin_arm_get_fpscr">,
253                       Intrinsic<[llvm_i32_ty], [], []>;
254def int_arm_set_fpscr : GCCBuiltin<"__builtin_arm_set_fpscr">,
255                       Intrinsic<[], [llvm_i32_ty], []>;
256def int_arm_vcvtr     : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
257                                  [IntrNoMem]>;
258def int_arm_vcvtru    : Intrinsic<[llvm_float_ty], [llvm_anyfloat_ty],
259                                  [IntrNoMem]>;
260
261//===----------------------------------------------------------------------===//
262// Coprocessor
263
264def int_arm_ldc : GCCBuiltin<"__builtin_arm_ldc">,
265   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
266def int_arm_ldcl : GCCBuiltin<"__builtin_arm_ldcl">,
267   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
268def int_arm_ldc2 : GCCBuiltin<"__builtin_arm_ldc2">,
269   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
270def int_arm_ldc2l : GCCBuiltin<"__builtin_arm_ldc2l">,
271   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
272
273def int_arm_stc : GCCBuiltin<"__builtin_arm_stc">,
274   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
275def int_arm_stcl : GCCBuiltin<"__builtin_arm_stcl">,
276   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
277def int_arm_stc2 : GCCBuiltin<"__builtin_arm_stc2">,
278   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
279def int_arm_stc2l : GCCBuiltin<"__builtin_arm_stc2l">,
280   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_ptr_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
281
282// Move to coprocessor
283def int_arm_mcr : GCCBuiltin<"__builtin_arm_mcr">,
284   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
285                  llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
286def int_arm_mcr2 : GCCBuiltin<"__builtin_arm_mcr2">,
287   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
288                  llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
289
290// Move from coprocessor
291def int_arm_mrc : GCCBuiltin<"__builtin_arm_mrc">,
292                  MSBuiltin<"_MoveFromCoprocessor">,
293   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
294                             llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
295def int_arm_mrc2 : GCCBuiltin<"__builtin_arm_mrc2">,
296                   MSBuiltin<"_MoveFromCoprocessor2">,
297   Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
298                             llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>]>;
299
300// Coprocessor data processing
301def int_arm_cdp : GCCBuiltin<"__builtin_arm_cdp">,
302   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
303                  llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
304def int_arm_cdp2 : GCCBuiltin<"__builtin_arm_cdp2">,
305   Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
306                  llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>, ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<5>>]>;
307
308// Move from two registers to coprocessor
309def int_arm_mcrr : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
310                                  llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
311def int_arm_mcrr2 : Intrinsic<[], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
312                                   llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<4>>]>;
313
314def int_arm_mrrc : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
315                              llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
316def int_arm_mrrc2 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,
317                               llvm_i32_ty, llvm_i32_ty], [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>>, ImmArg<ArgIndex<2>>]>;
318
319//===----------------------------------------------------------------------===//
320// CRC32
321
322def int_arm_crc32b  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
323    [IntrNoMem]>;
324def int_arm_crc32cb : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
325    [IntrNoMem]>;
326def int_arm_crc32h  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
327    [IntrNoMem]>;
328def int_arm_crc32ch : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
329    [IntrNoMem]>;
330def int_arm_crc32w  : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
331    [IntrNoMem]>;
332def int_arm_crc32cw : Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty],
333    [IntrNoMem]>;
334
335//===----------------------------------------------------------------------===//
336// CMSE
337
338def int_arm_cmse_tt : GCCBuiltin<"__builtin_arm_cmse_TT">,
339    Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
340def int_arm_cmse_ttt : GCCBuiltin<"__builtin_arm_cmse_TTT">,
341    Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
342def int_arm_cmse_tta : GCCBuiltin<"__builtin_arm_cmse_TTA">,
343    Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
344def int_arm_cmse_ttat : GCCBuiltin<"__builtin_arm_cmse_TTAT">,
345    Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrNoMem]>;
346
347//===----------------------------------------------------------------------===//
348// HINT
349
350def int_arm_hint : Intrinsic<[], [llvm_i32_ty]>;
351def int_arm_dbg : Intrinsic<[], [llvm_i32_ty]>;
352
353//===----------------------------------------------------------------------===//
354// UND (reserved undefined sequence)
355
356def int_arm_undefined : Intrinsic<[], [llvm_i32_ty]>;
357
358//===----------------------------------------------------------------------===//
359// Advanced SIMD (NEON)
360
361// The following classes do not correspond directly to GCC builtins.
362class Neon_1Arg_Intrinsic
363  : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
364class Neon_1Arg_Narrow_Intrinsic
365  : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>], [IntrNoMem]>;
366class Neon_2Arg_Intrinsic
367  : Intrinsic<[llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
368              [IntrNoMem]>;
369class Neon_2Arg_Narrow_Intrinsic
370  : Intrinsic<[llvm_anyvector_ty], [LLVMExtendedType<0>, LLVMExtendedType<0>],
371              [IntrNoMem]>;
372class Neon_2Arg_Long_Intrinsic
373  : Intrinsic<[llvm_anyvector_ty], [LLVMTruncatedType<0>, LLVMTruncatedType<0>],
374              [IntrNoMem]>;
375class Neon_3Arg_Intrinsic
376  : Intrinsic<[llvm_anyvector_ty],
377              [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
378              [IntrNoMem]>;
379class Neon_3Arg_Long_Intrinsic
380  : Intrinsic<[llvm_anyvector_ty],
381              [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
382              [IntrNoMem]>;
383
384class Neon_1FloatArg_Intrinsic
385  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
386
387class Neon_CvtFxToFP_Intrinsic
388  : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
389class Neon_CvtFPToFx_Intrinsic
390  : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
391class Neon_CvtFPtoInt_1Arg_Intrinsic
392  : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
393
394class Neon_Compare_Intrinsic
395  : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty, LLVMMatchType<1>],
396              [IntrNoMem]>;
397
398// The table operands for VTBL and VTBX consist of 1 to 4 v8i8 vectors.
399// Besides the table, VTBL has one other v8i8 argument and VTBX has two.
400// Overall, the classes range from 2 to 6 v8i8 arguments.
401class Neon_Tbl2Arg_Intrinsic
402  : Intrinsic<[llvm_v8i8_ty],
403              [llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
404class Neon_Tbl3Arg_Intrinsic
405  : Intrinsic<[llvm_v8i8_ty],
406              [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
407class Neon_Tbl4Arg_Intrinsic
408  : Intrinsic<[llvm_v8i8_ty],
409              [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty],
410              [IntrNoMem]>;
411class Neon_Tbl5Arg_Intrinsic
412  : Intrinsic<[llvm_v8i8_ty],
413              [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
414               llvm_v8i8_ty], [IntrNoMem]>;
415class Neon_Tbl6Arg_Intrinsic
416  : Intrinsic<[llvm_v8i8_ty],
417              [llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty, llvm_v8i8_ty,
418               llvm_v8i8_ty, llvm_v8i8_ty], [IntrNoMem]>;
419
420// Arithmetic ops
421
422let IntrProperties = [IntrNoMem, Commutative] in {
423
424  // Vector Add.
425  def int_arm_neon_vhadds : Neon_2Arg_Intrinsic;
426  def int_arm_neon_vhaddu : Neon_2Arg_Intrinsic;
427  def int_arm_neon_vrhadds : Neon_2Arg_Intrinsic;
428  def int_arm_neon_vrhaddu : Neon_2Arg_Intrinsic;
429  def int_arm_neon_vraddhn : Neon_2Arg_Narrow_Intrinsic;
430
431  // Vector Multiply.
432  def int_arm_neon_vmulp : Neon_2Arg_Intrinsic;
433  def int_arm_neon_vqdmulh : Neon_2Arg_Intrinsic;
434  def int_arm_neon_vqrdmulh : Neon_2Arg_Intrinsic;
435  def int_arm_neon_vmulls : Neon_2Arg_Long_Intrinsic;
436  def int_arm_neon_vmullu : Neon_2Arg_Long_Intrinsic;
437  def int_arm_neon_vmullp : Neon_2Arg_Long_Intrinsic;
438  def int_arm_neon_vqdmull : Neon_2Arg_Long_Intrinsic;
439
440  // Vector Maximum.
441  def int_arm_neon_vmaxs : Neon_2Arg_Intrinsic;
442  def int_arm_neon_vmaxu : Neon_2Arg_Intrinsic;
443  def int_arm_neon_vmaxnm : Neon_2Arg_Intrinsic;
444
445  // Vector Minimum.
446  def int_arm_neon_vmins : Neon_2Arg_Intrinsic;
447  def int_arm_neon_vminu : Neon_2Arg_Intrinsic;
448  def int_arm_neon_vminnm : Neon_2Arg_Intrinsic;
449
450  // Vector Reciprocal Step.
451  def int_arm_neon_vrecps : Neon_2Arg_Intrinsic;
452
453  // Vector Reciprocal Square Root Step.
454  def int_arm_neon_vrsqrts : Neon_2Arg_Intrinsic;
455}
456
457// Vector Subtract.
458def int_arm_neon_vhsubs : Neon_2Arg_Intrinsic;
459def int_arm_neon_vhsubu : Neon_2Arg_Intrinsic;
460def int_arm_neon_vrsubhn : Neon_2Arg_Narrow_Intrinsic;
461
462// Vector Absolute Compare.
463def int_arm_neon_vacge : Neon_Compare_Intrinsic;
464def int_arm_neon_vacgt : Neon_Compare_Intrinsic;
465
466// Vector Absolute Differences.
467def int_arm_neon_vabds : Neon_2Arg_Intrinsic;
468def int_arm_neon_vabdu : Neon_2Arg_Intrinsic;
469
470// Vector Pairwise Add.
471def int_arm_neon_vpadd : Neon_2Arg_Intrinsic;
472
473// Vector Pairwise Add Long.
474// Note: This is different than the other "long" NEON intrinsics because
475// the result vector has half as many elements as the source vector.
476// The source and destination vector types must be specified separately.
477def int_arm_neon_vpaddls : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
478                                     [IntrNoMem]>;
479def int_arm_neon_vpaddlu : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty],
480                                     [IntrNoMem]>;
481
482// Vector Pairwise Add and Accumulate Long.
483// Note: This is similar to vpaddl but the destination vector also appears
484// as the first argument.
485def int_arm_neon_vpadals : Intrinsic<[llvm_anyvector_ty],
486                                     [LLVMMatchType<0>, llvm_anyvector_ty],
487                                     [IntrNoMem]>;
488def int_arm_neon_vpadalu : Intrinsic<[llvm_anyvector_ty],
489                                     [LLVMMatchType<0>, llvm_anyvector_ty],
490                                     [IntrNoMem]>;
491
492// Vector Pairwise Maximum and Minimum.
493def int_arm_neon_vpmaxs : Neon_2Arg_Intrinsic;
494def int_arm_neon_vpmaxu : Neon_2Arg_Intrinsic;
495def int_arm_neon_vpmins : Neon_2Arg_Intrinsic;
496def int_arm_neon_vpminu : Neon_2Arg_Intrinsic;
497
498// Vector Shifts:
499//
500// The various saturating and rounding vector shift operations need to be
501// represented by intrinsics in LLVM, and even the basic VSHL variable shift
502// operation cannot be safely translated to LLVM's shift operators.  VSHL can
503// be used for both left and right shifts, or even combinations of the two,
504// depending on the signs of the shift amounts.  It also has well-defined
505// behavior for shift amounts that LLVM leaves undefined.  Only basic shifts
506// by constants can be represented with LLVM's shift operators.
507//
508// The shift counts for these intrinsics are always vectors, even for constant
509// shifts, where the constant is replicated.  For consistency with VSHL (and
510// other variable shift instructions), left shifts have positive shift counts
511// and right shifts have negative shift counts.  This convention is also used
512// for constant right shift intrinsics, and to help preserve sanity, the
513// intrinsic names use "shift" instead of either "shl" or "shr".  Where
514// applicable, signed and unsigned versions of the intrinsics are
515// distinguished with "s" and "u" suffixes.  A few NEON shift instructions,
516// such as VQSHLU, take signed operands but produce unsigned results; these
517// use a "su" suffix.
518
519// Vector Shift.
520def int_arm_neon_vshifts : Neon_2Arg_Intrinsic;
521def int_arm_neon_vshiftu : Neon_2Arg_Intrinsic;
522
523// Vector Rounding Shift.
524def int_arm_neon_vrshifts : Neon_2Arg_Intrinsic;
525def int_arm_neon_vrshiftu : Neon_2Arg_Intrinsic;
526def int_arm_neon_vrshiftn : Neon_2Arg_Narrow_Intrinsic;
527
528// Vector Saturating Shift.
529def int_arm_neon_vqshifts : Neon_2Arg_Intrinsic;
530def int_arm_neon_vqshiftu : Neon_2Arg_Intrinsic;
531def int_arm_neon_vqshiftsu : Neon_2Arg_Intrinsic;
532def int_arm_neon_vqshiftns : Neon_2Arg_Narrow_Intrinsic;
533def int_arm_neon_vqshiftnu : Neon_2Arg_Narrow_Intrinsic;
534def int_arm_neon_vqshiftnsu : Neon_2Arg_Narrow_Intrinsic;
535
536// Vector Saturating Rounding Shift.
537def int_arm_neon_vqrshifts : Neon_2Arg_Intrinsic;
538def int_arm_neon_vqrshiftu : Neon_2Arg_Intrinsic;
539def int_arm_neon_vqrshiftns : Neon_2Arg_Narrow_Intrinsic;
540def int_arm_neon_vqrshiftnu : Neon_2Arg_Narrow_Intrinsic;
541def int_arm_neon_vqrshiftnsu : Neon_2Arg_Narrow_Intrinsic;
542
543// Vector Shift and Insert.
544def int_arm_neon_vshiftins : Neon_3Arg_Intrinsic;
545
546// Vector Absolute Value and Saturating Absolute Value.
547def int_arm_neon_vabs : Neon_1Arg_Intrinsic;
548def int_arm_neon_vqabs : Neon_1Arg_Intrinsic;
549
550// Vector Saturating Negate.
551def int_arm_neon_vqneg : Neon_1Arg_Intrinsic;
552
553// Vector Count Leading Sign/Zero Bits.
554def int_arm_neon_vcls : Neon_1Arg_Intrinsic;
555
556// Vector Reciprocal Estimate.
557def int_arm_neon_vrecpe : Neon_1Arg_Intrinsic;
558
559// Vector Reciprocal Square Root Estimate.
560def int_arm_neon_vrsqrte : Neon_1Arg_Intrinsic;
561
562// Vector Conversions Between Floating-point and Integer
563def int_arm_neon_vcvtau : Neon_CvtFPtoInt_1Arg_Intrinsic;
564def int_arm_neon_vcvtas : Neon_CvtFPtoInt_1Arg_Intrinsic;
565def int_arm_neon_vcvtnu : Neon_CvtFPtoInt_1Arg_Intrinsic;
566def int_arm_neon_vcvtns : Neon_CvtFPtoInt_1Arg_Intrinsic;
567def int_arm_neon_vcvtpu : Neon_CvtFPtoInt_1Arg_Intrinsic;
568def int_arm_neon_vcvtps : Neon_CvtFPtoInt_1Arg_Intrinsic;
569def int_arm_neon_vcvtmu : Neon_CvtFPtoInt_1Arg_Intrinsic;
570def int_arm_neon_vcvtms : Neon_CvtFPtoInt_1Arg_Intrinsic;
571
572// Vector Conversions Between Floating-point and Fixed-point.
573def int_arm_neon_vcvtfp2fxs : Neon_CvtFPToFx_Intrinsic;
574def int_arm_neon_vcvtfp2fxu : Neon_CvtFPToFx_Intrinsic;
575def int_arm_neon_vcvtfxs2fp : Neon_CvtFxToFP_Intrinsic;
576def int_arm_neon_vcvtfxu2fp : Neon_CvtFxToFP_Intrinsic;
577
578// Vector Conversions Between Half-Precision and Single-Precision.
579def int_arm_neon_vcvtfp2hf
580    : Intrinsic<[llvm_v4i16_ty], [llvm_v4f32_ty], [IntrNoMem]>;
581def int_arm_neon_vcvthf2fp
582    : Intrinsic<[llvm_v4f32_ty], [llvm_v4i16_ty], [IntrNoMem]>;
583
584// Narrowing Saturating Vector Moves.
585def int_arm_neon_vqmovns : Neon_1Arg_Narrow_Intrinsic;
586def int_arm_neon_vqmovnu : Neon_1Arg_Narrow_Intrinsic;
587def int_arm_neon_vqmovnsu : Neon_1Arg_Narrow_Intrinsic;
588
589// Vector Table Lookup.
590// The first 1-4 arguments are the table.
591def int_arm_neon_vtbl1 : Neon_Tbl2Arg_Intrinsic;
592def int_arm_neon_vtbl2 : Neon_Tbl3Arg_Intrinsic;
593def int_arm_neon_vtbl3 : Neon_Tbl4Arg_Intrinsic;
594def int_arm_neon_vtbl4 : Neon_Tbl5Arg_Intrinsic;
595
596// Vector Table Extension.
597// Some elements of the destination vector may not be updated, so the original
598// value of that vector is passed as the first argument.  The next 1-4
599// arguments after that are the table.
600def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
601def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
602def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
603def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
604
605// Vector and Scalar Rounding.
606def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
607def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
608def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
609def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
610def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
611def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
612
613// De-interleaving vector loads from N-element structures.
614// Source operands are the address and alignment.
615def int_arm_neon_vld1 : Intrinsic<[llvm_anyvector_ty],
616                                  [llvm_anyptr_ty, llvm_i32_ty],
617                                  [IntrReadMem, IntrArgMemOnly]>;
618def int_arm_neon_vld2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
619                                  [llvm_anyptr_ty, llvm_i32_ty],
620                                  [IntrReadMem, IntrArgMemOnly]>;
621def int_arm_neon_vld3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
622                                   LLVMMatchType<0>],
623                                  [llvm_anyptr_ty, llvm_i32_ty],
624                                  [IntrReadMem, IntrArgMemOnly]>;
625def int_arm_neon_vld4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
626                                   LLVMMatchType<0>, LLVMMatchType<0>],
627                                  [llvm_anyptr_ty, llvm_i32_ty],
628                                  [IntrReadMem, IntrArgMemOnly]>;
629
630def int_arm_neon_vld1x2 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
631                                    [LLVMAnyPointerType<LLVMMatchType<0>>],
632                                    [IntrReadMem, IntrArgMemOnly]>;
633def int_arm_neon_vld1x3 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
634                                     LLVMMatchType<0>],
635                                    [LLVMAnyPointerType<LLVMMatchType<0>>],
636                                    [IntrReadMem, IntrArgMemOnly]>;
637def int_arm_neon_vld1x4 : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
638                                     LLVMMatchType<0>, LLVMMatchType<0>],
639                                    [LLVMAnyPointerType<LLVMMatchType<0>>],
640                                    [IntrReadMem, IntrArgMemOnly]>;
641
642// Vector load N-element structure to one lane.
643// Source operands are: the address, the N input vectors (since only one
644// lane is assigned), the lane number, and the alignment.
645def int_arm_neon_vld2lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
646                                      [llvm_anyptr_ty, LLVMMatchType<0>,
647                                       LLVMMatchType<0>, llvm_i32_ty,
648                                       llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
649def int_arm_neon_vld3lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
650                                       LLVMMatchType<0>],
651                                      [llvm_anyptr_ty, LLVMMatchType<0>,
652                                       LLVMMatchType<0>, LLVMMatchType<0>,
653                                       llvm_i32_ty, llvm_i32_ty],
654                                      [IntrReadMem, IntrArgMemOnly]>;
655def int_arm_neon_vld4lane : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
656                                       LLVMMatchType<0>, LLVMMatchType<0>],
657                                      [llvm_anyptr_ty, LLVMMatchType<0>,
658                                       LLVMMatchType<0>, LLVMMatchType<0>,
659                                       LLVMMatchType<0>, llvm_i32_ty,
660                                       llvm_i32_ty], [IntrReadMem, IntrArgMemOnly]>;
661
662// Vector load N-element structure to all lanes.
663// Source operands are the address and alignment.
664def int_arm_neon_vld2dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>],
665                                     [llvm_anyptr_ty, llvm_i32_ty],
666                                     [IntrReadMem, IntrArgMemOnly]>;
667def int_arm_neon_vld3dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
668                                      LLVMMatchType<0>],
669                                     [llvm_anyptr_ty, llvm_i32_ty],
670                                     [IntrReadMem, IntrArgMemOnly]>;
671def int_arm_neon_vld4dup : Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>,
672                                      LLVMMatchType<0>, LLVMMatchType<0>],
673                                     [llvm_anyptr_ty, llvm_i32_ty],
674                                     [IntrReadMem, IntrArgMemOnly]>;
675
676// Interleaving vector stores from N-element structures.
677// Source operands are: the address, the N vectors, and the alignment.
678def int_arm_neon_vst1 : Intrinsic<[],
679                                  [llvm_anyptr_ty, llvm_anyvector_ty,
680                                   llvm_i32_ty], [IntrArgMemOnly]>;
681def int_arm_neon_vst2 : Intrinsic<[],
682                                  [llvm_anyptr_ty, llvm_anyvector_ty,
683                                   LLVMMatchType<1>, llvm_i32_ty],
684                                  [IntrArgMemOnly]>;
685def int_arm_neon_vst3 : Intrinsic<[],
686                                  [llvm_anyptr_ty, llvm_anyvector_ty,
687                                   LLVMMatchType<1>, LLVMMatchType<1>,
688                                   llvm_i32_ty], [IntrArgMemOnly]>;
689def int_arm_neon_vst4 : Intrinsic<[],
690                                  [llvm_anyptr_ty, llvm_anyvector_ty,
691                                   LLVMMatchType<1>, LLVMMatchType<1>,
692                                   LLVMMatchType<1>, llvm_i32_ty],
693                                  [IntrArgMemOnly]>;
694
695def int_arm_neon_vst1x2 : Intrinsic<[],
696                                    [llvm_anyptr_ty, llvm_anyvector_ty,
697                                     LLVMMatchType<1>],
698                                    [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
699def int_arm_neon_vst1x3 : Intrinsic<[],
700                                    [llvm_anyptr_ty, llvm_anyvector_ty,
701                                     LLVMMatchType<1>, LLVMMatchType<1>],
702                                    [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
703def int_arm_neon_vst1x4 : Intrinsic<[],
704                                    [llvm_anyptr_ty, llvm_anyvector_ty,
705                                     LLVMMatchType<1>, LLVMMatchType<1>,
706                                     LLVMMatchType<1>],
707                                    [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
708
709// Vector store N-element structure from one lane.
710// Source operands are: the address, the N vectors, the lane number, and
711// the alignment.
712def int_arm_neon_vst2lane : Intrinsic<[],
713                                      [llvm_anyptr_ty, llvm_anyvector_ty,
714                                       LLVMMatchType<1>, llvm_i32_ty,
715                                       llvm_i32_ty], [IntrArgMemOnly]>;
716def int_arm_neon_vst3lane : Intrinsic<[],
717                                      [llvm_anyptr_ty, llvm_anyvector_ty,
718                                       LLVMMatchType<1>, LLVMMatchType<1>,
719                                       llvm_i32_ty, llvm_i32_ty],
720                                      [IntrArgMemOnly]>;
721def int_arm_neon_vst4lane : Intrinsic<[],
722                                      [llvm_anyptr_ty, llvm_anyvector_ty,
723                                       LLVMMatchType<1>, LLVMMatchType<1>,
724                                       LLVMMatchType<1>, llvm_i32_ty,
725                                       llvm_i32_ty], [IntrArgMemOnly]>;
726
727// Vector bitwise select.
728def int_arm_neon_vbsl : Intrinsic<[llvm_anyvector_ty],
729                        [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
730                        [IntrNoMem]>;
731
732
733// Crypto instructions
734class AES_1Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
735                                     [llvm_v16i8_ty], [IntrNoMem]>;
736class AES_2Arg_Intrinsic : Intrinsic<[llvm_v16i8_ty],
737                                     [llvm_v16i8_ty, llvm_v16i8_ty],
738                                     [IntrNoMem]>;
739
740class SHA_1Arg_Intrinsic : Intrinsic<[llvm_i32_ty], [llvm_i32_ty],
741                                     [IntrNoMem]>;
742class SHA_2Arg_Intrinsic : Intrinsic<[llvm_v4i32_ty],
743                                     [llvm_v4i32_ty, llvm_v4i32_ty],
744                                     [IntrNoMem]>;
745class SHA_3Arg_i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
746                                   [llvm_v4i32_ty, llvm_i32_ty, llvm_v4i32_ty],
747                                   [IntrNoMem]>;
748class SHA_3Arg_v4i32_Intrinsic : Intrinsic<[llvm_v4i32_ty],
749                                   [llvm_v4i32_ty, llvm_v4i32_ty,llvm_v4i32_ty],
750                                   [IntrNoMem]>;
751
752def int_arm_neon_aesd : AES_2Arg_Intrinsic;
753def int_arm_neon_aese : AES_2Arg_Intrinsic;
754def int_arm_neon_aesimc : AES_1Arg_Intrinsic;
755def int_arm_neon_aesmc : AES_1Arg_Intrinsic;
756def int_arm_neon_sha1h : SHA_1Arg_Intrinsic;
757def int_arm_neon_sha1su1 : SHA_2Arg_Intrinsic;
758def int_arm_neon_sha256su0 : SHA_2Arg_Intrinsic;
759def int_arm_neon_sha1c : SHA_3Arg_i32_Intrinsic;
760def int_arm_neon_sha1m : SHA_3Arg_i32_Intrinsic;
761def int_arm_neon_sha1p : SHA_3Arg_i32_Intrinsic;
762def int_arm_neon_sha1su0: SHA_3Arg_v4i32_Intrinsic;
763def int_arm_neon_sha256h: SHA_3Arg_v4i32_Intrinsic;
764def int_arm_neon_sha256h2: SHA_3Arg_v4i32_Intrinsic;
765def int_arm_neon_sha256su1: SHA_3Arg_v4i32_Intrinsic;
766
767// Armv8.2-A dot product instructions
768class Neon_Dot_Intrinsic
769  : Intrinsic<[llvm_anyvector_ty],
770              [LLVMMatchType<0>, llvm_anyvector_ty,
771               LLVMMatchType<1>],
772              [IntrNoMem]>;
773def int_arm_neon_udot : Neon_Dot_Intrinsic;
774def int_arm_neon_sdot : Neon_Dot_Intrinsic;
775
776// v8.6-A Matrix Multiply Intrinsics
777class Neon_MatMul_Intrinsic
778  : Intrinsic<[llvm_anyvector_ty],
779              [LLVMMatchType<0>, llvm_anyvector_ty,
780               LLVMMatchType<1>],
781              [IntrNoMem]>;
782def int_arm_neon_ummla  : Neon_MatMul_Intrinsic;
783def int_arm_neon_smmla  : Neon_MatMul_Intrinsic;
784def int_arm_neon_usmmla : Neon_MatMul_Intrinsic;
785def int_arm_neon_usdot  : Neon_Dot_Intrinsic;
786
787// v8.6-A Bfloat Intrinsics
788def int_arm_neon_vcvtfp2bf
789    : Intrinsic<[llvm_anyvector_ty], [llvm_v4f32_ty], [IntrNoMem]>;
790def int_arm_neon_vcvtbfp2bf
791    : Intrinsic<[llvm_bfloat_ty], [llvm_float_ty], [IntrNoMem]>;
792
793def int_arm_neon_bfdot : Neon_Dot_Intrinsic;
794def int_arm_neon_bfmmla
795    : Intrinsic<[llvm_v4f32_ty],
796                [llvm_v4f32_ty, llvm_v8bf16_ty, llvm_v8bf16_ty],
797                [IntrNoMem]>;
798
799class Neon_BF16FML_Intrinsic
800    : Intrinsic<[llvm_v4f32_ty],
801                [llvm_v4f32_ty, llvm_v8bf16_ty, llvm_v8bf16_ty],
802                [IntrNoMem]>;
803def int_arm_neon_bfmlalb : Neon_BF16FML_Intrinsic;
804def int_arm_neon_bfmlalt : Neon_BF16FML_Intrinsic;
805
806def int_arm_cls: Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
807def int_arm_cls64: Intrinsic<[llvm_i32_ty], [llvm_i64_ty], [IntrNoMem]>;
808
809def int_arm_mve_vctp8  : Intrinsic<[llvm_v16i1_ty], [llvm_i32_ty], [IntrNoMem]>;
810def int_arm_mve_vctp16 : Intrinsic<[llvm_v8i1_ty], [llvm_i32_ty], [IntrNoMem]>;
811def int_arm_mve_vctp32 : Intrinsic<[llvm_v4i1_ty], [llvm_i32_ty], [IntrNoMem]>;
812// vctp64 takes v4i1, to work around v2i1 not being a legal MVE type
813def int_arm_mve_vctp64 : Intrinsic<[llvm_v4i1_ty], [llvm_i32_ty], [IntrNoMem]>;
814
815// v8.3-A Floating-point complex add
816def int_arm_neon_vcadd_rot90  : Neon_2Arg_Intrinsic;
817def int_arm_neon_vcadd_rot270 : Neon_2Arg_Intrinsic;
818
819// GNU eabi mcount
820def int_arm_gnu_eabi_mcount : Intrinsic<[], [], []>;
821
822def int_arm_mve_pred_i2v : Intrinsic<
823  [llvm_anyvector_ty], [llvm_i32_ty], [IntrNoMem]>;
824def int_arm_mve_pred_v2i : Intrinsic<
825  [llvm_i32_ty], [llvm_anyvector_ty], [IntrNoMem]>;
826def int_arm_mve_vreinterpretq : Intrinsic<
827  [llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
828
829def int_arm_mve_min_predicated: Intrinsic<[llvm_anyvector_ty],
830   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
831    llvm_anyvector_ty, LLVMMatchType<0>],
832   [IntrNoMem]>;
833def int_arm_mve_max_predicated: Intrinsic<[llvm_anyvector_ty],
834   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
835    llvm_anyvector_ty, LLVMMatchType<0>],
836   [IntrNoMem]>;
837def int_arm_mve_abd_predicated: Intrinsic<[llvm_anyvector_ty],
838   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
839    llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
840def int_arm_mve_add_predicated: Intrinsic<[llvm_anyvector_ty],
841   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
842   [IntrNoMem]>;
843def int_arm_mve_and_predicated: Intrinsic<[llvm_anyvector_ty],
844   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
845   [IntrNoMem]>;
846def int_arm_mve_bic_predicated: Intrinsic<[llvm_anyvector_ty],
847   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
848   [IntrNoMem]>;
849def int_arm_mve_eor_predicated: Intrinsic<[llvm_anyvector_ty],
850   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
851   [IntrNoMem]>;
852def int_arm_mve_orn_predicated: Intrinsic<[llvm_anyvector_ty],
853   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
854   [IntrNoMem]>;
855def int_arm_mve_orr_predicated: Intrinsic<[llvm_anyvector_ty],
856   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
857   [IntrNoMem]>;
858def int_arm_mve_sub_predicated: Intrinsic<[llvm_anyvector_ty],
859   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
860   [IntrNoMem]>;
861def int_arm_mve_mul_predicated: Intrinsic<[llvm_anyvector_ty],
862   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
863   [IntrNoMem]>;
864def int_arm_mve_mulh_predicated: Intrinsic<[llvm_anyvector_ty],
865   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
866    llvm_anyvector_ty, LLVMMatchType<0>],
867   [IntrNoMem]>;
868def int_arm_mve_qdmulh_predicated: Intrinsic<[llvm_anyvector_ty],
869   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
870   [IntrNoMem]>;
871def int_arm_mve_rmulh_predicated: Intrinsic<[llvm_anyvector_ty],
872   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
873    llvm_anyvector_ty, LLVMMatchType<0>],
874   [IntrNoMem]>;
875def int_arm_mve_qrdmulh_predicated: Intrinsic<[llvm_anyvector_ty],
876   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
877   [IntrNoMem]>;
878def int_arm_mve_mull_int_predicated: Intrinsic<[llvm_anyvector_ty],
879   [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty /* unsigned */,
880    llvm_i32_ty /* top */, llvm_anyvector_ty, LLVMMatchType<0>],
881   [IntrNoMem]>;
882def int_arm_mve_mull_poly_predicated: Intrinsic<[llvm_anyvector_ty],
883   [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty,
884    LLVMMatchType<0>],
885   [IntrNoMem]>;
886def int_arm_mve_qadd_predicated: Intrinsic<[llvm_anyvector_ty],
887   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
888    llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
889def int_arm_mve_hadd_predicated: Intrinsic<[llvm_anyvector_ty],
890   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
891    llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
892def int_arm_mve_rhadd_predicated: Intrinsic<[llvm_anyvector_ty],
893   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
894    llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
895def int_arm_mve_qsub_predicated: Intrinsic<[llvm_anyvector_ty],
896   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
897    llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
898def int_arm_mve_hsub_predicated: Intrinsic<[llvm_anyvector_ty],
899   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */,
900    llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
901def int_arm_mve_vmina_predicated: Intrinsic<[llvm_anyvector_ty],
902   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty],
903    [IntrNoMem]>;
904def int_arm_mve_vmaxa_predicated: Intrinsic<[llvm_anyvector_ty],
905   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty],
906    [IntrNoMem]>;
907def int_arm_mve_vminnma_predicated: Intrinsic<[llvm_anyvector_ty],
908   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty],
909    [IntrNoMem]>;
910def int_arm_mve_vmaxnma_predicated: Intrinsic<[llvm_anyvector_ty],
911   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty],
912    [IntrNoMem]>;
913
914multiclass MVEPredicated<list<LLVMType> rets, list<LLVMType> params,
915                         LLVMType pred = llvm_anyvector_ty,
916                         list<IntrinsicProperty> props = [IntrNoMem],
917                         list<SDNodeProperty> sdprops = []> {
918  def "": Intrinsic<rets, params, props, "", sdprops>;
919  def _predicated: Intrinsic<rets, params # [pred], props, "", sdprops>;
920}
921multiclass MVEPredicatedM<list<LLVMType> rets, list<LLVMType> params,
922                          LLVMType pred = llvm_anyvector_ty,
923                          list<IntrinsicProperty> props = [IntrNoMem]> {
924  def "": Intrinsic<rets, params, props>;
925  def _predicated: Intrinsic<rets, params # [pred,
926      !if(!eq(rets[0], llvm_anyvector_ty),
927          LLVMMatchType<0>, rets[0])], props>;
928}
929
930multiclass MVE_minmaxv {
931  defm v: MVEPredicated<[llvm_i32_ty],
932     [llvm_i32_ty, llvm_anyvector_ty, llvm_i32_ty /* unsigned */]>;
933  defm av: MVEPredicated<[llvm_i32_ty],
934     [llvm_i32_ty, llvm_anyvector_ty]>;
935  defm nmv: MVEPredicated<[llvm_anyfloat_ty],
936     [LLVMMatchType<0>, llvm_anyvector_ty]>;
937  defm nmav: MVEPredicated<[llvm_anyfloat_ty],
938     [LLVMMatchType<0>, llvm_anyvector_ty]>;
939}
940defm int_arm_mve_min: MVE_minmaxv;
941defm int_arm_mve_max: MVE_minmaxv;
942
943defm int_arm_mve_addv: MVEPredicated<[llvm_i32_ty],
944   [llvm_anyvector_ty, llvm_i32_ty /* unsigned */]>;
945defm int_arm_mve_addlv: MVEPredicated<[llvm_i64_ty],
946   [llvm_anyvector_ty, llvm_i32_ty /* unsigned */]>;
947
948// Intrinsic with a predicated and a non-predicated case. The predicated case
949// has two additional parameters: inactive (the value for inactive lanes, can
950// be undef) and predicate.
951multiclass MVEMXPredicated<list<LLVMType> rets, list<LLVMType> flags,
952                           list<LLVMType> params, LLVMType inactive,
953                           LLVMType predicate,
954                           list<IntrinsicProperty> props = [IntrNoMem]> {
955  def "":          Intrinsic<rets, flags # params, props>;
956  def _predicated: Intrinsic<rets, flags # [inactive] # params # [predicate],
957                             props>;
958}
959
960defm int_arm_mve_vcvt_narrow: MVEPredicated<[llvm_v8f16_ty],
961   [llvm_v8f16_ty, llvm_v4f32_ty, llvm_i32_ty], llvm_v4i1_ty>;
962defm int_arm_mve_vcvt_widen: MVEMXPredicated<[llvm_v4f32_ty], [],
963   [llvm_v8f16_ty, llvm_i32_ty], llvm_v4f32_ty, llvm_v4i1_ty>;
964
965defm int_arm_mve_vldr_gather_base: MVEPredicated<
966   [llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty],
967   llvm_anyvector_ty, [IntrReadMem], [SDNPMemOperand]>;
968defm int_arm_mve_vldr_gather_base_wb: MVEPredicated<
969   [llvm_anyvector_ty, llvm_anyvector_ty],
970   [LLVMMatchType<1>, llvm_i32_ty], llvm_anyvector_ty, [IntrReadMem],
971   [SDNPMemOperand]>;
972defm int_arm_mve_vstr_scatter_base: MVEPredicated<
973   [], [llvm_anyvector_ty, llvm_i32_ty, llvm_anyvector_ty],
974   llvm_anyvector_ty, [IntrWriteMem], [SDNPMemOperand]>;
975defm int_arm_mve_vstr_scatter_base_wb: MVEPredicated<
976   [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty],
977   llvm_anyvector_ty, [IntrWriteMem], [SDNPMemOperand]>;
978
979// gather_offset takes three i32 parameters. The first is the size of
980// memory element loaded, in bits. The second is a left bit shift to
981// apply to each offset in the vector parameter (must be either 0, or
982// correspond to the element size of the destination vector type). The
983// last is 1 to indicate zero extension (if the load is widening), or
984// 0 for sign extension.
985//
986// scatter_offset has the first two of those parameters, but since it
987// narrows rather than widening, it doesn't have the last one.
988defm int_arm_mve_vldr_gather_offset: MVEPredicated<
989   [llvm_anyvector_ty], [llvm_anyptr_ty, llvm_anyvector_ty,
990   llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], llvm_anyvector_ty, [IntrReadMem],
991   [SDNPMemOperand]>;
992defm int_arm_mve_vstr_scatter_offset: MVEPredicated<
993   [], [llvm_anyptr_ty, llvm_anyvector_ty, llvm_anyvector_ty,
994   llvm_i32_ty, llvm_i32_ty], llvm_anyvector_ty, [IntrWriteMem],
995   [SDNPMemOperand]>;
996
997def int_arm_mve_shl_imm_predicated: Intrinsic<[llvm_anyvector_ty],
998   [LLVMMatchType<0>, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>],
999   [IntrNoMem]>;
1000def int_arm_mve_shr_imm_predicated: Intrinsic<[llvm_anyvector_ty],
1001   [LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty, // extra i32 is unsigned flag
1002    llvm_anyvector_ty, LLVMMatchType<0>],
1003   [IntrNoMem]>;
1004
1005defm int_arm_mve_vqshl_imm: MVEPredicatedM<[llvm_anyvector_ty],
1006   [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/]>;
1007defm int_arm_mve_vrshr_imm: MVEPredicatedM<[llvm_anyvector_ty],
1008   [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/]>;
1009defm int_arm_mve_vqshlu_imm: MVEPredicatedM<[llvm_anyvector_ty],
1010   [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/]>;
1011defm int_arm_mve_vshll_imm: MVEPredicatedM<[llvm_anyvector_ty],
1012   [llvm_anyvector_ty, llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*unsigned*/,
1013                       llvm_i32_ty /*top-half*/]>;
1014
1015defm int_arm_mve_vsli: MVEPredicated<
1016   [llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty]>;
1017defm int_arm_mve_vsri: MVEPredicated<
1018   [llvm_anyvector_ty], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty]>;
1019
1020defm int_arm_mve_vshrn: MVEPredicated<
1021   [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty,
1022    llvm_i32_ty /*shiftcount*/, llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/,
1023    llvm_i32_ty /*unsigned-out*/, llvm_i32_ty /*unsigned-in*/,
1024    llvm_i32_ty /*top-half*/]>;
1025
1026defm int_arm_mve_vshl_scalar: MVEPredicated<
1027   [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_i32_ty /*shiftcount*/,
1028    llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, llvm_i32_ty /*unsigned*/]>;
1029defm int_arm_mve_vshl_vector: MVEPredicatedM<
1030   [llvm_anyvector_ty], [LLVMMatchType<0>, llvm_anyvector_ty /*shiftcounts*/,
1031    llvm_i32_ty /*saturate*/, llvm_i32_ty /*round*/, llvm_i32_ty /*unsigned*/]>;
1032
1033// MVE scalar shifts.
1034class ARM_MVE_qrshift_single<list<LLVMType> value,
1035                             list<LLVMType> saturate = []> :
1036  Intrinsic<value, value # [llvm_i32_ty] # saturate, [IntrNoMem]>;
1037multiclass ARM_MVE_qrshift<list<LLVMType> saturate = []> {
1038  // Most of these shifts come in 32- and 64-bit versions. But only
1039  // the 64-bit ones have the extra saturation argument (if any).
1040  def "": ARM_MVE_qrshift_single<[llvm_i32_ty]>;
1041  def l:  ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty], saturate>;
1042}
1043defm int_arm_mve_urshr: ARM_MVE_qrshift;
1044defm int_arm_mve_uqshl: ARM_MVE_qrshift;
1045defm int_arm_mve_srshr: ARM_MVE_qrshift;
1046defm int_arm_mve_sqshl: ARM_MVE_qrshift;
1047defm int_arm_mve_uqrshl: ARM_MVE_qrshift<[llvm_i32_ty]>;
1048defm int_arm_mve_sqrshr: ARM_MVE_qrshift<[llvm_i32_ty]>;
1049// LSLL and ASRL only have 64-bit versions, not 32.
1050def int_arm_mve_lsll: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>;
1051def int_arm_mve_asrl: ARM_MVE_qrshift_single<[llvm_i32_ty, llvm_i32_ty]>;
1052
1053def int_arm_mve_vabd: Intrinsic<
1054   [llvm_anyvector_ty],
1055   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1056   [IntrNoMem]>;
1057def int_arm_mve_vadc: Intrinsic<
1058   [llvm_anyvector_ty, llvm_i32_ty],
1059   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>;
1060def int_arm_mve_vsbc: Intrinsic<
1061   [llvm_anyvector_ty, llvm_i32_ty],
1062   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>;
1063def int_arm_mve_vadc_predicated: Intrinsic<
1064   [llvm_anyvector_ty, llvm_i32_ty],
1065   [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
1066    llvm_i32_ty, llvm_anyvector_ty], [IntrNoMem]>;
1067def int_arm_mve_vsbc_predicated: Intrinsic<
1068   [llvm_anyvector_ty, llvm_i32_ty],
1069   [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
1070    llvm_i32_ty, llvm_anyvector_ty], [IntrNoMem]>;
1071def int_arm_mve_vshlc: Intrinsic<
1072   [llvm_i32_ty /* bits shifted out */, llvm_anyvector_ty],
1073   [LLVMMatchType<0>, llvm_i32_ty /* bits shifted in */,
1074    llvm_i32_ty /* shift count */], [IntrNoMem]>;
1075def int_arm_mve_vshlc_predicated: Intrinsic<
1076   [llvm_i32_ty /* bits shifted out */, llvm_anyvector_ty],
1077   [LLVMMatchType<0>, llvm_i32_ty /* bits shifted in */,
1078    llvm_i32_ty /* shift count */, llvm_anyvector_ty], [IntrNoMem]>;
1079def int_arm_mve_vmulh: Intrinsic<
1080   [llvm_anyvector_ty],
1081   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1082   [IntrNoMem]>;
1083def int_arm_mve_vqdmulh: Intrinsic<
1084   [llvm_anyvector_ty],
1085   [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
1086def int_arm_mve_vhadd: Intrinsic<
1087   [llvm_anyvector_ty],
1088   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1089   [IntrNoMem]>;
1090def int_arm_mve_vrhadd: Intrinsic<
1091   [llvm_anyvector_ty],
1092   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1093   [IntrNoMem]>;
1094def int_arm_mve_vhsub: Intrinsic<
1095   [llvm_anyvector_ty],
1096   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1097   [IntrNoMem]>;
1098def int_arm_mve_vrmulh: Intrinsic<
1099   [llvm_anyvector_ty],
1100   [LLVMMatchType<0>, LLVMMatchType<0>, llvm_i32_ty /* unsigned */],
1101   [IntrNoMem]>;
1102def int_arm_mve_vqrdmulh: Intrinsic<
1103   [llvm_anyvector_ty],
1104   [LLVMMatchType<0>, LLVMMatchType<0>], [IntrNoMem]>;
1105def int_arm_mve_vmull: Intrinsic<
1106   [llvm_anyvector_ty],
1107   [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty /* unsigned */,
1108    llvm_i32_ty /* top */], [IntrNoMem]>;
1109def int_arm_mve_vmull_poly: Intrinsic<
1110   [llvm_anyvector_ty],
1111   [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty], [IntrNoMem]>;
1112
1113// The first two parameters are compile-time constants:
1114// * Halving: 0 means  halving (vhcaddq), 1 means non-halving (vcaddq)
1115//            instruction. Note: the flag is inverted to match the corresponding
1116//            bit in the instruction encoding
1117// * Rotation angle: 0 mean 90 deg, 1 means 180 deg
1118defm int_arm_mve_vcaddq : MVEMXPredicated<
1119  [llvm_anyvector_ty],
1120  [llvm_i32_ty, llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
1121   LLVMMatchType<0>, llvm_anyvector_ty>;
1122
1123// The first operand of the following two intrinsics is the rotation angle
1124// (must be a compile-time constant):
1125// 0 - 0 deg
1126// 1 - 90 deg
1127// 2 - 180 deg
1128// 3 - 270 deg
1129defm int_arm_mve_vcmulq : MVEMXPredicated<
1130  [llvm_anyvector_ty],
1131  [llvm_i32_ty], [LLVMMatchType<0>, LLVMMatchType<0>],
1132   LLVMMatchType<0>, llvm_anyvector_ty>;
1133
1134defm int_arm_mve_vcmlaq : MVEPredicated<
1135  [llvm_anyvector_ty],
1136  [llvm_i32_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
1137   llvm_anyvector_ty>;
1138
1139def int_arm_mve_vld2q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>], [llvm_anyptr_ty],
1140                                 [IntrReadMem, IntrArgMemOnly]>;
1141def int_arm_mve_vld4q: Intrinsic<[llvm_anyvector_ty, LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>], [llvm_anyptr_ty],
1142                                 [IntrReadMem, IntrArgMemOnly]>;
1143
1144def int_arm_mve_vst2q: Intrinsic<[], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty],
1145                                 [IntrWriteMem, IntrArgMemOnly], "", [SDNPMemOperand]>;
1146def int_arm_mve_vst4q: Intrinsic<[], [llvm_anyptr_ty, llvm_anyvector_ty, LLVMMatchType<1>, LLVMMatchType<1>, LLVMMatchType<1>, llvm_i32_ty],
1147                                 [IntrWriteMem, IntrArgMemOnly], "", [SDNPMemOperand]>;
1148
1149// MVE vector absolute difference and accumulate across vector
1150// The first operand is an 'unsigned' flag. The remaining operands are:
1151// * accumulator
1152// * first vector operand
1153// * second vector operand
1154// * mask (only in predicated versions)
1155defm int_arm_mve_vabav: MVEPredicated<
1156  [llvm_i32_ty],
1157  [llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], llvm_anyvector_ty>;
1158
1159// The following 3 instrinsics are MVE vector reductions with two vector
1160// operands.
1161// The first 3 operands are boolean flags (must be compile-time constants):
1162// * unsigned - the instruction operates on vectors of unsigned values and
1163//              unsigned scalars
1164// * subtract - the instruction performs subtraction after multiplication of
1165//              lane pairs (e.g., vmlsdav vs vmladav)
1166// * exchange - the instruction exchanges successive even and odd lanes of
1167//              the first operands before multiplication of lane pairs
1168//              (e.g., vmladavx vs vmladav)
1169// The remaining operands are:
1170// * accumulator
1171// * first vector operand
1172// * second vector operand
1173// * mask (only in predicated versions)
1174
1175// Version with 32-bit result, vml{a,s}dav[a][x]
1176defm int_arm_mve_vmldava: MVEPredicated<
1177  [llvm_i32_ty],
1178  [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
1179   llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>],
1180  llvm_anyvector_ty>;
1181
1182// Version with 64-bit result, vml{a,s}ldav[a][x]
1183defm int_arm_mve_vmlldava: MVEPredicated<
1184  [llvm_i32_ty, llvm_i32_ty],
1185  [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
1186   llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>],
1187  llvm_anyvector_ty>;
1188
1189// Version with 72-bit rounded result, vrml{a,s}ldavh[a][x]
1190defm int_arm_mve_vrmlldavha: MVEPredicated<
1191  [llvm_i32_ty, llvm_i32_ty],
1192  [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
1193   llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>],
1194  llvm_anyvector_ty>;
1195
1196defm int_arm_mve_vidup: MVEMXPredicated<
1197   [llvm_anyvector_ty /* output */, llvm_i32_ty /* written-back base */], [],
1198   [llvm_i32_ty /* base */, llvm_i32_ty /* step */],
1199   LLVMMatchType<0>, llvm_anyvector_ty>;
1200defm int_arm_mve_vddup: MVEMXPredicated<
1201   [llvm_anyvector_ty /* output */, llvm_i32_ty /* written-back base */], [],
1202   [llvm_i32_ty /* base */, llvm_i32_ty /* step */],
1203   LLVMMatchType<0>, llvm_anyvector_ty>;
1204defm int_arm_mve_viwdup: MVEMXPredicated<
1205   [llvm_anyvector_ty /* output */, llvm_i32_ty /* written-back base */], [],
1206   [llvm_i32_ty /* base */, llvm_i32_ty /* limit */, llvm_i32_ty /* step */],
1207   LLVMMatchType<0>, llvm_anyvector_ty>;
1208defm int_arm_mve_vdwdup: MVEMXPredicated<
1209   [llvm_anyvector_ty /* output */, llvm_i32_ty /* written-back base */], [],
1210   [llvm_i32_ty /* base */, llvm_i32_ty /* limit */, llvm_i32_ty /* step */],
1211   LLVMMatchType<0>, llvm_anyvector_ty>;
1212
1213// Flags:
1214// * unsigned
1215defm int_arm_mve_vcvt_fix: MVEMXPredicated<
1216  [llvm_anyvector_ty /* output */], [llvm_i32_ty],
1217  [llvm_anyvector_ty /* input vector */, llvm_i32_ty /* scale */],
1218  LLVMMatchType<0>, llvm_anyvector_ty>;
1219
1220def int_arm_mve_vcvt_fp_int_predicated: Intrinsic<
1221  [llvm_anyvector_ty], [llvm_anyvector_ty, llvm_i32_ty /* unsigned */,
1222   llvm_anyvector_ty /* predicate */, LLVMMatchType<0> /* inactive */],
1223  [IntrNoMem]>;
1224
1225foreach suffix = ["a","n","p","m"] in {
1226  defm "int_arm_mve_vcvt"#suffix: MVEMXPredicated<
1227    [llvm_anyvector_ty /* output */], [llvm_i32_ty /* unsigned */],
1228    [llvm_anyvector_ty /* input */], LLVMMatchType<0>, llvm_anyvector_ty>;
1229}
1230
1231def int_arm_mve_vrintn: Intrinsic<
1232  [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
1233def int_arm_mve_vcls: Intrinsic<
1234  [llvm_anyvector_ty], [LLVMMatchType<0>], [IntrNoMem]>;
1235
1236defm int_arm_mve_vbrsr: MVEMXPredicated<
1237  [llvm_anyvector_ty], [],
1238  [LLVMMatchType<0>, llvm_i32_ty], LLVMMatchType<0>, llvm_anyvector_ty>;
1239
1240def int_arm_mve_vqdmull: Intrinsic<
1241  [llvm_anyvector_ty],
1242  [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty],
1243  [IntrNoMem]>;
1244def int_arm_mve_vqdmull_predicated: Intrinsic<
1245  [llvm_anyvector_ty],
1246  [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty,
1247   LLVMMatchType<0>],
1248  [IntrNoMem]>;
1249
1250class MVESimpleUnaryPredicated: Intrinsic<[llvm_anyvector_ty],
1251   [LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
1252
1253def int_arm_mve_mvn_predicated: MVESimpleUnaryPredicated;
1254def int_arm_mve_abs_predicated: MVESimpleUnaryPredicated;
1255def int_arm_mve_neg_predicated: MVESimpleUnaryPredicated;
1256def int_arm_mve_qabs_predicated: MVESimpleUnaryPredicated;
1257def int_arm_mve_qneg_predicated: MVESimpleUnaryPredicated;
1258def int_arm_mve_clz_predicated: MVESimpleUnaryPredicated;
1259def int_arm_mve_cls_predicated: MVESimpleUnaryPredicated;
1260def int_arm_mve_vrintz_predicated: MVESimpleUnaryPredicated;
1261def int_arm_mve_vrintm_predicated: MVESimpleUnaryPredicated;
1262def int_arm_mve_vrintp_predicated: MVESimpleUnaryPredicated;
1263def int_arm_mve_vrinta_predicated: MVESimpleUnaryPredicated;
1264def int_arm_mve_vrintx_predicated: MVESimpleUnaryPredicated;
1265def int_arm_mve_vrintn_predicated: MVESimpleUnaryPredicated;
1266
1267def int_arm_mve_vrev_predicated: Intrinsic<[llvm_anyvector_ty],
1268   [LLVMMatchType<0>, llvm_i32_ty /* size to reverse */,
1269    llvm_anyvector_ty, LLVMMatchType<0>], [IntrNoMem]>;
1270
1271def int_arm_mve_vmovl_predicated: Intrinsic<[llvm_anyvector_ty],
1272   [llvm_anyvector_ty, llvm_i32_ty /* unsigned */, llvm_i32_ty /* top half */,
1273    llvm_anyvector_ty /* predicate */, LLVMMatchType<0>], [IntrNoMem]>;
1274def int_arm_mve_vmovn_predicated: Intrinsic<[llvm_anyvector_ty],
1275   [LLVMMatchType<0>, llvm_anyvector_ty, llvm_i32_ty /* top half */,
1276    llvm_anyvector_ty /* predicate */], [IntrNoMem]>;
1277
1278def int_arm_mve_vqmovn: Intrinsic<[llvm_anyvector_ty],
1279   [LLVMMatchType<0>, llvm_anyvector_ty,
1280    llvm_i32_ty /* unsigned output */, llvm_i32_ty /* unsigned input */,
1281    llvm_i32_ty /* top half */], [IntrNoMem]>;
1282def int_arm_mve_vqmovn_predicated: Intrinsic<[llvm_anyvector_ty],
1283   [LLVMMatchType<0>, llvm_anyvector_ty,
1284    llvm_i32_ty /* unsigned output */, llvm_i32_ty /* unsigned input */,
1285    llvm_i32_ty /* top half */, llvm_anyvector_ty /* pred */], [IntrNoMem]>;
1286
1287def int_arm_mve_fma_predicated: Intrinsic<[llvm_anyvector_ty],
1288   [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1289    LLVMMatchType<0> /* addend */, llvm_anyvector_ty /* pred */], [IntrNoMem]>;
1290def int_arm_mve_vmla_n_predicated: Intrinsic<[llvm_anyvector_ty],
1291   [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1292    llvm_i32_ty /* mult op #2 (scalar) */, llvm_anyvector_ty /* pred */],
1293   [IntrNoMem]>;
1294def int_arm_mve_vmlas_n_predicated: Intrinsic<[llvm_anyvector_ty],
1295   [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1296    llvm_i32_ty /* addend (scalar) */, llvm_anyvector_ty /* pred */],
1297   [IntrNoMem]>;
1298
1299defm int_arm_mve_vqdmlah: MVEPredicated<[llvm_anyvector_ty],
1300  [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1301   llvm_i32_ty /* mult op #2 (scalar) */]>;
1302defm int_arm_mve_vqrdmlah: MVEPredicated<[llvm_anyvector_ty],
1303  [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* addend */,
1304   llvm_i32_ty /* mult op #2 (scalar) */]>;
1305defm int_arm_mve_vqdmlash: MVEPredicated<[llvm_anyvector_ty],
1306  [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1307   llvm_i32_ty /* addend (scalar) */]>;
1308defm int_arm_mve_vqrdmlash: MVEPredicated<[llvm_anyvector_ty],
1309  [LLVMMatchType<0> /* mult op #1 */, LLVMMatchType<0> /* mult op #2 */,
1310   llvm_i32_ty /* addend (scalar) */]>;
1311
1312defm int_arm_mve_vqdmlad: MVEPredicated<[llvm_anyvector_ty],
1313  [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>,
1314   llvm_i32_ty /* exchange */, llvm_i32_ty /* round */,
1315   llvm_i32_ty /* subtract */]>;
1316
1317// CDE (Custom Datapath Extension)
1318
1319multiclass CDEGPRIntrinsics<list<LLVMType> args> {
1320  def "" : Intrinsic<
1321    [llvm_i32_ty],
1322    !listconcat([llvm_i32_ty /* coproc */], args, [llvm_i32_ty /* imm */]),
1323    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 1)>>]>;
1324  def a : Intrinsic<
1325    [llvm_i32_ty],
1326    !listconcat([llvm_i32_ty /* coproc */, llvm_i32_ty /* acc */], args,
1327                [llvm_i32_ty /* imm */]),
1328    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1329
1330  def d: Intrinsic<
1331    [llvm_i32_ty /* lo */, llvm_i32_ty /* hi */],
1332    !listconcat([llvm_i32_ty /* coproc */], args, [llvm_i32_ty /* imm */]),
1333    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 1)>>]>;
1334  def da: Intrinsic<
1335    [llvm_i32_ty /* lo */, llvm_i32_ty /* hi */],
1336    !listconcat([llvm_i32_ty /* coproc */, llvm_i32_ty /* acc_lo */,
1337                 llvm_i32_ty /* acc_hi */], args, [llvm_i32_ty /* imm */]),
1338    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 3)>>]>;
1339}
1340
1341defm int_arm_cde_cx1: CDEGPRIntrinsics<[]>;
1342defm int_arm_cde_cx2: CDEGPRIntrinsics<[llvm_i32_ty]>;
1343defm int_arm_cde_cx3: CDEGPRIntrinsics<[llvm_i32_ty, llvm_i32_ty]>;
1344
1345multiclass CDEVCXIntrinsics<list<LLVMType> args> {
1346  def "" : Intrinsic<
1347    [llvm_anyfloat_ty],
1348    !listconcat([llvm_i32_ty /* coproc */], args, [llvm_i32_ty /* imm */]),
1349    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 1)>>]>;
1350  def a : Intrinsic<
1351    [llvm_anyfloat_ty],
1352    !listconcat([llvm_i32_ty /* coproc */,  LLVMMatchType<0> /* acc */],
1353                args, [llvm_i32_ty /* imm */]),
1354    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1355}
1356
1357defm int_arm_cde_vcx1 : CDEVCXIntrinsics<[]>;
1358defm int_arm_cde_vcx2 : CDEVCXIntrinsics<[LLVMMatchType<0>]>;
1359defm int_arm_cde_vcx3 : CDEVCXIntrinsics<[LLVMMatchType<0>, LLVMMatchType<0>]>;
1360
1361multiclass CDEVCXVecIntrinsics<list<LLVMType> args> {
1362  def "" : Intrinsic<
1363    [llvm_v16i8_ty],
1364    !listconcat([llvm_i32_ty /* coproc */], args, [llvm_i32_ty /* imm */]),
1365    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 1)>>]>;
1366  def a : Intrinsic<
1367    [llvm_v16i8_ty],
1368    !listconcat([llvm_i32_ty /* coproc */, llvm_v16i8_ty /* acc */],
1369                args, [llvm_i32_ty /* imm */]),
1370    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1371
1372  def _predicated : Intrinsic<
1373    [llvm_anyvector_ty],
1374    !listconcat([llvm_i32_ty /* coproc */, LLVMMatchType<0> /* inactive */],
1375                args, [llvm_i32_ty /* imm */, llvm_anyvector_ty /* mask */]),
1376    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1377  def a_predicated : Intrinsic<
1378    [llvm_anyvector_ty],
1379    !listconcat([llvm_i32_ty /* coproc */, LLVMMatchType<0> /* acc */],
1380                args, [llvm_i32_ty /* imm */, llvm_anyvector_ty /* mask */]),
1381    [IntrNoMem, ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<!add(!size(args), 2)>>]>;
1382}
1383
1384defm int_arm_cde_vcx1q : CDEVCXVecIntrinsics<[]>;
1385defm int_arm_cde_vcx2q : CDEVCXVecIntrinsics<[llvm_v16i8_ty]>;
1386defm int_arm_cde_vcx3q : CDEVCXVecIntrinsics<[llvm_v16i8_ty, llvm_v16i8_ty]>;
1387
1388} // end TargetPrefix
1389