1 //===-- AArch64BaseInfo.h - Top level definitions for AArch64 ---*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the AArch64 target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15
16 #ifndef LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
17 #define LLVM_LIB_TARGET_AARCH64_UTILS_AARCH64BASEINFO_H
18
19 // FIXME: Is it easiest to fix this layering violation by moving the .inc
20 // #includes from AArch64MCTargetDesc.h to here?
21 #include "MCTargetDesc/AArch64MCTargetDesc.h" // For AArch64::X0 and friends.
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/MC/SubtargetFeature.h"
25 #include "llvm/Support/ErrorHandling.h"
26
27 namespace llvm {
28
getWRegFromXReg(unsigned Reg)29 inline static unsigned getWRegFromXReg(unsigned Reg) {
30 switch (Reg) {
31 case AArch64::X0: return AArch64::W0;
32 case AArch64::X1: return AArch64::W1;
33 case AArch64::X2: return AArch64::W2;
34 case AArch64::X3: return AArch64::W3;
35 case AArch64::X4: return AArch64::W4;
36 case AArch64::X5: return AArch64::W5;
37 case AArch64::X6: return AArch64::W6;
38 case AArch64::X7: return AArch64::W7;
39 case AArch64::X8: return AArch64::W8;
40 case AArch64::X9: return AArch64::W9;
41 case AArch64::X10: return AArch64::W10;
42 case AArch64::X11: return AArch64::W11;
43 case AArch64::X12: return AArch64::W12;
44 case AArch64::X13: return AArch64::W13;
45 case AArch64::X14: return AArch64::W14;
46 case AArch64::X15: return AArch64::W15;
47 case AArch64::X16: return AArch64::W16;
48 case AArch64::X17: return AArch64::W17;
49 case AArch64::X18: return AArch64::W18;
50 case AArch64::X19: return AArch64::W19;
51 case AArch64::X20: return AArch64::W20;
52 case AArch64::X21: return AArch64::W21;
53 case AArch64::X22: return AArch64::W22;
54 case AArch64::X23: return AArch64::W23;
55 case AArch64::X24: return AArch64::W24;
56 case AArch64::X25: return AArch64::W25;
57 case AArch64::X26: return AArch64::W26;
58 case AArch64::X27: return AArch64::W27;
59 case AArch64::X28: return AArch64::W28;
60 case AArch64::FP: return AArch64::W29;
61 case AArch64::LR: return AArch64::W30;
62 case AArch64::SP: return AArch64::WSP;
63 case AArch64::XZR: return AArch64::WZR;
64 }
65 // For anything else, return it unchanged.
66 return Reg;
67 }
68
getXRegFromWReg(unsigned Reg)69 inline static unsigned getXRegFromWReg(unsigned Reg) {
70 switch (Reg) {
71 case AArch64::W0: return AArch64::X0;
72 case AArch64::W1: return AArch64::X1;
73 case AArch64::W2: return AArch64::X2;
74 case AArch64::W3: return AArch64::X3;
75 case AArch64::W4: return AArch64::X4;
76 case AArch64::W5: return AArch64::X5;
77 case AArch64::W6: return AArch64::X6;
78 case AArch64::W7: return AArch64::X7;
79 case AArch64::W8: return AArch64::X8;
80 case AArch64::W9: return AArch64::X9;
81 case AArch64::W10: return AArch64::X10;
82 case AArch64::W11: return AArch64::X11;
83 case AArch64::W12: return AArch64::X12;
84 case AArch64::W13: return AArch64::X13;
85 case AArch64::W14: return AArch64::X14;
86 case AArch64::W15: return AArch64::X15;
87 case AArch64::W16: return AArch64::X16;
88 case AArch64::W17: return AArch64::X17;
89 case AArch64::W18: return AArch64::X18;
90 case AArch64::W19: return AArch64::X19;
91 case AArch64::W20: return AArch64::X20;
92 case AArch64::W21: return AArch64::X21;
93 case AArch64::W22: return AArch64::X22;
94 case AArch64::W23: return AArch64::X23;
95 case AArch64::W24: return AArch64::X24;
96 case AArch64::W25: return AArch64::X25;
97 case AArch64::W26: return AArch64::X26;
98 case AArch64::W27: return AArch64::X27;
99 case AArch64::W28: return AArch64::X28;
100 case AArch64::W29: return AArch64::FP;
101 case AArch64::W30: return AArch64::LR;
102 case AArch64::WSP: return AArch64::SP;
103 case AArch64::WZR: return AArch64::XZR;
104 }
105 // For anything else, return it unchanged.
106 return Reg;
107 }
108
getXRegFromXRegTuple(unsigned RegTuple)109 inline static unsigned getXRegFromXRegTuple(unsigned RegTuple) {
110 switch (RegTuple) {
111 case AArch64::X0_X1_X2_X3_X4_X5_X6_X7: return AArch64::X0;
112 case AArch64::X2_X3_X4_X5_X6_X7_X8_X9: return AArch64::X2;
113 case AArch64::X4_X5_X6_X7_X8_X9_X10_X11: return AArch64::X4;
114 case AArch64::X6_X7_X8_X9_X10_X11_X12_X13: return AArch64::X6;
115 case AArch64::X8_X9_X10_X11_X12_X13_X14_X15: return AArch64::X8;
116 case AArch64::X10_X11_X12_X13_X14_X15_X16_X17: return AArch64::X10;
117 case AArch64::X12_X13_X14_X15_X16_X17_X18_X19: return AArch64::X12;
118 case AArch64::X14_X15_X16_X17_X18_X19_X20_X21: return AArch64::X14;
119 case AArch64::X16_X17_X18_X19_X20_X21_X22_X23: return AArch64::X16;
120 case AArch64::X18_X19_X20_X21_X22_X23_X24_X25: return AArch64::X18;
121 case AArch64::X20_X21_X22_X23_X24_X25_X26_X27: return AArch64::X20;
122 case AArch64::X22_X23_X24_X25_X26_X27_X28_FP: return AArch64::X22;
123 }
124 // For anything else, return it unchanged.
125 return RegTuple;
126 }
127
getBRegFromDReg(unsigned Reg)128 static inline unsigned getBRegFromDReg(unsigned Reg) {
129 switch (Reg) {
130 case AArch64::D0: return AArch64::B0;
131 case AArch64::D1: return AArch64::B1;
132 case AArch64::D2: return AArch64::B2;
133 case AArch64::D3: return AArch64::B3;
134 case AArch64::D4: return AArch64::B4;
135 case AArch64::D5: return AArch64::B5;
136 case AArch64::D6: return AArch64::B6;
137 case AArch64::D7: return AArch64::B7;
138 case AArch64::D8: return AArch64::B8;
139 case AArch64::D9: return AArch64::B9;
140 case AArch64::D10: return AArch64::B10;
141 case AArch64::D11: return AArch64::B11;
142 case AArch64::D12: return AArch64::B12;
143 case AArch64::D13: return AArch64::B13;
144 case AArch64::D14: return AArch64::B14;
145 case AArch64::D15: return AArch64::B15;
146 case AArch64::D16: return AArch64::B16;
147 case AArch64::D17: return AArch64::B17;
148 case AArch64::D18: return AArch64::B18;
149 case AArch64::D19: return AArch64::B19;
150 case AArch64::D20: return AArch64::B20;
151 case AArch64::D21: return AArch64::B21;
152 case AArch64::D22: return AArch64::B22;
153 case AArch64::D23: return AArch64::B23;
154 case AArch64::D24: return AArch64::B24;
155 case AArch64::D25: return AArch64::B25;
156 case AArch64::D26: return AArch64::B26;
157 case AArch64::D27: return AArch64::B27;
158 case AArch64::D28: return AArch64::B28;
159 case AArch64::D29: return AArch64::B29;
160 case AArch64::D30: return AArch64::B30;
161 case AArch64::D31: return AArch64::B31;
162 }
163 // For anything else, return it unchanged.
164 return Reg;
165 }
166
167
getDRegFromBReg(unsigned Reg)168 static inline unsigned getDRegFromBReg(unsigned Reg) {
169 switch (Reg) {
170 case AArch64::B0: return AArch64::D0;
171 case AArch64::B1: return AArch64::D1;
172 case AArch64::B2: return AArch64::D2;
173 case AArch64::B3: return AArch64::D3;
174 case AArch64::B4: return AArch64::D4;
175 case AArch64::B5: return AArch64::D5;
176 case AArch64::B6: return AArch64::D6;
177 case AArch64::B7: return AArch64::D7;
178 case AArch64::B8: return AArch64::D8;
179 case AArch64::B9: return AArch64::D9;
180 case AArch64::B10: return AArch64::D10;
181 case AArch64::B11: return AArch64::D11;
182 case AArch64::B12: return AArch64::D12;
183 case AArch64::B13: return AArch64::D13;
184 case AArch64::B14: return AArch64::D14;
185 case AArch64::B15: return AArch64::D15;
186 case AArch64::B16: return AArch64::D16;
187 case AArch64::B17: return AArch64::D17;
188 case AArch64::B18: return AArch64::D18;
189 case AArch64::B19: return AArch64::D19;
190 case AArch64::B20: return AArch64::D20;
191 case AArch64::B21: return AArch64::D21;
192 case AArch64::B22: return AArch64::D22;
193 case AArch64::B23: return AArch64::D23;
194 case AArch64::B24: return AArch64::D24;
195 case AArch64::B25: return AArch64::D25;
196 case AArch64::B26: return AArch64::D26;
197 case AArch64::B27: return AArch64::D27;
198 case AArch64::B28: return AArch64::D28;
199 case AArch64::B29: return AArch64::D29;
200 case AArch64::B30: return AArch64::D30;
201 case AArch64::B31: return AArch64::D31;
202 }
203 // For anything else, return it unchanged.
204 return Reg;
205 }
206
atomicBarrierDroppedOnZero(unsigned Opcode)207 static inline bool atomicBarrierDroppedOnZero(unsigned Opcode) {
208 switch (Opcode) {
209 case AArch64::LDADDAB: case AArch64::LDADDAH:
210 case AArch64::LDADDAW: case AArch64::LDADDAX:
211 case AArch64::LDADDALB: case AArch64::LDADDALH:
212 case AArch64::LDADDALW: case AArch64::LDADDALX:
213 case AArch64::LDCLRAB: case AArch64::LDCLRAH:
214 case AArch64::LDCLRAW: case AArch64::LDCLRAX:
215 case AArch64::LDCLRALB: case AArch64::LDCLRALH:
216 case AArch64::LDCLRALW: case AArch64::LDCLRALX:
217 case AArch64::LDEORAB: case AArch64::LDEORAH:
218 case AArch64::LDEORAW: case AArch64::LDEORAX:
219 case AArch64::LDEORALB: case AArch64::LDEORALH:
220 case AArch64::LDEORALW: case AArch64::LDEORALX:
221 case AArch64::LDSETAB: case AArch64::LDSETAH:
222 case AArch64::LDSETAW: case AArch64::LDSETAX:
223 case AArch64::LDSETALB: case AArch64::LDSETALH:
224 case AArch64::LDSETALW: case AArch64::LDSETALX:
225 case AArch64::LDSMAXAB: case AArch64::LDSMAXAH:
226 case AArch64::LDSMAXAW: case AArch64::LDSMAXAX:
227 case AArch64::LDSMAXALB: case AArch64::LDSMAXALH:
228 case AArch64::LDSMAXALW: case AArch64::LDSMAXALX:
229 case AArch64::LDSMINAB: case AArch64::LDSMINAH:
230 case AArch64::LDSMINAW: case AArch64::LDSMINAX:
231 case AArch64::LDSMINALB: case AArch64::LDSMINALH:
232 case AArch64::LDSMINALW: case AArch64::LDSMINALX:
233 case AArch64::LDUMAXAB: case AArch64::LDUMAXAH:
234 case AArch64::LDUMAXAW: case AArch64::LDUMAXAX:
235 case AArch64::LDUMAXALB: case AArch64::LDUMAXALH:
236 case AArch64::LDUMAXALW: case AArch64::LDUMAXALX:
237 case AArch64::LDUMINAB: case AArch64::LDUMINAH:
238 case AArch64::LDUMINAW: case AArch64::LDUMINAX:
239 case AArch64::LDUMINALB: case AArch64::LDUMINALH:
240 case AArch64::LDUMINALW: case AArch64::LDUMINALX:
241 case AArch64::SWPAB: case AArch64::SWPAH:
242 case AArch64::SWPAW: case AArch64::SWPAX:
243 case AArch64::SWPALB: case AArch64::SWPALH:
244 case AArch64::SWPALW: case AArch64::SWPALX:
245 return true;
246 }
247 return false;
248 }
249
250 namespace AArch64CC {
251
252 // The CondCodes constants map directly to the 4-bit encoding of the condition
253 // field for predicated instructions.
254 enum CondCode { // Meaning (integer) Meaning (floating-point)
255 EQ = 0x0, // Equal Equal
256 NE = 0x1, // Not equal Not equal, or unordered
257 HS = 0x2, // Unsigned higher or same >, ==, or unordered
258 LO = 0x3, // Unsigned lower Less than
259 MI = 0x4, // Minus, negative Less than
260 PL = 0x5, // Plus, positive or zero >, ==, or unordered
261 VS = 0x6, // Overflow Unordered
262 VC = 0x7, // No overflow Not unordered
263 HI = 0x8, // Unsigned higher Greater than, or unordered
264 LS = 0x9, // Unsigned lower or same Less than or equal
265 GE = 0xa, // Greater than or equal Greater than or equal
266 LT = 0xb, // Less than Less than, or unordered
267 GT = 0xc, // Greater than Greater than
268 LE = 0xd, // Less than or equal <, ==, or unordered
269 AL = 0xe, // Always (unconditional) Always (unconditional)
270 NV = 0xf, // Always (unconditional) Always (unconditional)
271 // Note the NV exists purely to disassemble 0b1111. Execution is "always".
272 Invalid,
273
274 // Common aliases used for SVE.
275 ANY_ACTIVE = NE, // (!Z)
276 FIRST_ACTIVE = MI, // ( N)
277 LAST_ACTIVE = LO, // (!C)
278 NONE_ACTIVE = EQ // ( Z)
279 };
280
getCondCodeName(CondCode Code)281 inline static const char *getCondCodeName(CondCode Code) {
282 switch (Code) {
283 default: llvm_unreachable("Unknown condition code");
284 case EQ: return "eq";
285 case NE: return "ne";
286 case HS: return "hs";
287 case LO: return "lo";
288 case MI: return "mi";
289 case PL: return "pl";
290 case VS: return "vs";
291 case VC: return "vc";
292 case HI: return "hi";
293 case LS: return "ls";
294 case GE: return "ge";
295 case LT: return "lt";
296 case GT: return "gt";
297 case LE: return "le";
298 case AL: return "al";
299 case NV: return "nv";
300 }
301 }
302
getInvertedCondCode(CondCode Code)303 inline static CondCode getInvertedCondCode(CondCode Code) {
304 // To reverse a condition it's necessary to only invert the low bit:
305
306 return static_cast<CondCode>(static_cast<unsigned>(Code) ^ 0x1);
307 }
308
309 /// Given a condition code, return NZCV flags that would satisfy that condition.
310 /// The flag bits are in the format expected by the ccmp instructions.
311 /// Note that many different flag settings can satisfy a given condition code,
312 /// this function just returns one of them.
getNZCVToSatisfyCondCode(CondCode Code)313 inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
314 // NZCV flags encoded as expected by ccmp instructions, ARMv8 ISA 5.5.7.
315 enum { N = 8, Z = 4, C = 2, V = 1 };
316 switch (Code) {
317 default: llvm_unreachable("Unknown condition code");
318 case EQ: return Z; // Z == 1
319 case NE: return 0; // Z == 0
320 case HS: return C; // C == 1
321 case LO: return 0; // C == 0
322 case MI: return N; // N == 1
323 case PL: return 0; // N == 0
324 case VS: return V; // V == 1
325 case VC: return 0; // V == 0
326 case HI: return C; // C == 1 && Z == 0
327 case LS: return 0; // C == 0 || Z == 1
328 case GE: return 0; // N == V
329 case LT: return N; // N != V
330 case GT: return 0; // Z == 0 && N == V
331 case LE: return Z; // Z == 1 || N != V
332 }
333 }
334 } // end namespace AArch64CC
335
336 struct SysAlias {
337 const char *Name;
338 uint16_t Encoding;
339 FeatureBitset FeaturesRequired;
340
SysAliasSysAlias341 constexpr SysAlias(const char *N, uint16_t E) : Name(N), Encoding(E) {}
SysAliasSysAlias342 constexpr SysAlias(const char *N, uint16_t E, FeatureBitset F)
343 : Name(N), Encoding(E), FeaturesRequired(F) {}
344
haveFeaturesSysAlias345 bool haveFeatures(FeatureBitset ActiveFeatures) const {
346 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
347 }
348
getRequiredFeaturesSysAlias349 FeatureBitset getRequiredFeatures() const { return FeaturesRequired; }
350 };
351
352 struct SysAliasReg : SysAlias {
353 bool NeedsReg;
SysAliasRegSysAliasReg354 constexpr SysAliasReg(const char *N, uint16_t E, bool R)
355 : SysAlias(N, E), NeedsReg(R) {}
SysAliasRegSysAliasReg356 constexpr SysAliasReg(const char *N, uint16_t E, bool R, FeatureBitset F)
357 : SysAlias(N, E, F), NeedsReg(R) {}
358 };
359
360 struct SysAliasImm : SysAlias {
361 uint16_t ImmValue;
SysAliasImmSysAliasImm362 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I)
363 : SysAlias(N, E), ImmValue(I) {}
SysAliasImmSysAliasImm364 constexpr SysAliasImm(const char *N, uint16_t E, uint16_t I, FeatureBitset F)
365 : SysAlias(N, E, F), ImmValue(I) {}
366 };
367
368 namespace AArch64SVCR {
369 struct SVCR : SysAlias{
370 using SysAlias::SysAlias;
371 };
372 #define GET_SVCR_DECL
373 #include "AArch64GenSystemOperands.inc"
374 }
375
376 namespace AArch64AT{
377 struct AT : SysAlias {
378 using SysAlias::SysAlias;
379 };
380 #define GET_AT_DECL
381 #include "AArch64GenSystemOperands.inc"
382 }
383
384 namespace AArch64DB {
385 struct DB : SysAlias {
386 using SysAlias::SysAlias;
387 };
388 #define GET_DB_DECL
389 #include "AArch64GenSystemOperands.inc"
390 }
391
392 namespace AArch64DBnXS {
393 struct DBnXS : SysAliasImm {
394 using SysAliasImm::SysAliasImm;
395 };
396 #define GET_DBNXS_DECL
397 #include "AArch64GenSystemOperands.inc"
398 }
399
400 namespace AArch64DC {
401 struct DC : SysAlias {
402 using SysAlias::SysAlias;
403 };
404 #define GET_DC_DECL
405 #include "AArch64GenSystemOperands.inc"
406 }
407
408 namespace AArch64IC {
409 struct IC : SysAliasReg {
410 using SysAliasReg::SysAliasReg;
411 };
412 #define GET_IC_DECL
413 #include "AArch64GenSystemOperands.inc"
414 }
415
416 namespace AArch64ISB {
417 struct ISB : SysAlias {
418 using SysAlias::SysAlias;
419 };
420 #define GET_ISB_DECL
421 #include "AArch64GenSystemOperands.inc"
422 }
423
424 namespace AArch64TSB {
425 struct TSB : SysAlias {
426 using SysAlias::SysAlias;
427 };
428 #define GET_TSB_DECL
429 #include "AArch64GenSystemOperands.inc"
430 }
431
432 namespace AArch64PRFM {
433 struct PRFM : SysAlias {
434 using SysAlias::SysAlias;
435 };
436 #define GET_PRFM_DECL
437 #include "AArch64GenSystemOperands.inc"
438 }
439
440 namespace AArch64SVEPRFM {
441 struct SVEPRFM : SysAlias {
442 using SysAlias::SysAlias;
443 };
444 #define GET_SVEPRFM_DECL
445 #include "AArch64GenSystemOperands.inc"
446 }
447
448 namespace AArch64SVEPredPattern {
449 struct SVEPREDPAT {
450 const char *Name;
451 uint16_t Encoding;
452 };
453 #define GET_SVEPREDPAT_DECL
454 #include "AArch64GenSystemOperands.inc"
455 }
456
457 namespace AArch64ExactFPImm {
458 struct ExactFPImm {
459 const char *Name;
460 int Enum;
461 const char *Repr;
462 };
463 #define GET_EXACTFPIMM_DECL
464 #include "AArch64GenSystemOperands.inc"
465 }
466
467 namespace AArch64PState {
468 struct PState : SysAlias{
469 using SysAlias::SysAlias;
470 };
471 #define GET_PSTATE_DECL
472 #include "AArch64GenSystemOperands.inc"
473 }
474
475 namespace AArch64PSBHint {
476 struct PSB : SysAlias {
477 using SysAlias::SysAlias;
478 };
479 #define GET_PSB_DECL
480 #include "AArch64GenSystemOperands.inc"
481 }
482
483 namespace AArch64BTIHint {
484 struct BTI : SysAlias {
485 using SysAlias::SysAlias;
486 };
487 #define GET_BTI_DECL
488 #include "AArch64GenSystemOperands.inc"
489 }
490
491 namespace AArch64SE {
492 enum ShiftExtSpecifiers {
493 Invalid = -1,
494 LSL,
495 MSL,
496 LSR,
497 ASR,
498 ROR,
499
500 UXTB,
501 UXTH,
502 UXTW,
503 UXTX,
504
505 SXTB,
506 SXTH,
507 SXTW,
508 SXTX
509 };
510 }
511
512 namespace AArch64Layout {
513 enum VectorLayout {
514 Invalid = -1,
515 VL_8B,
516 VL_4H,
517 VL_2S,
518 VL_1D,
519
520 VL_16B,
521 VL_8H,
522 VL_4S,
523 VL_2D,
524
525 // Bare layout for the 128-bit vector
526 // (only show ".b", ".h", ".s", ".d" without vector number)
527 VL_B,
528 VL_H,
529 VL_S,
530 VL_D
531 };
532 }
533
534 inline static const char *
AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout)535 AArch64VectorLayoutToString(AArch64Layout::VectorLayout Layout) {
536 switch (Layout) {
537 case AArch64Layout::VL_8B: return ".8b";
538 case AArch64Layout::VL_4H: return ".4h";
539 case AArch64Layout::VL_2S: return ".2s";
540 case AArch64Layout::VL_1D: return ".1d";
541 case AArch64Layout::VL_16B: return ".16b";
542 case AArch64Layout::VL_8H: return ".8h";
543 case AArch64Layout::VL_4S: return ".4s";
544 case AArch64Layout::VL_2D: return ".2d";
545 case AArch64Layout::VL_B: return ".b";
546 case AArch64Layout::VL_H: return ".h";
547 case AArch64Layout::VL_S: return ".s";
548 case AArch64Layout::VL_D: return ".d";
549 default: llvm_unreachable("Unknown Vector Layout");
550 }
551 }
552
553 inline static AArch64Layout::VectorLayout
AArch64StringToVectorLayout(StringRef LayoutStr)554 AArch64StringToVectorLayout(StringRef LayoutStr) {
555 return StringSwitch<AArch64Layout::VectorLayout>(LayoutStr)
556 .Case(".8b", AArch64Layout::VL_8B)
557 .Case(".4h", AArch64Layout::VL_4H)
558 .Case(".2s", AArch64Layout::VL_2S)
559 .Case(".1d", AArch64Layout::VL_1D)
560 .Case(".16b", AArch64Layout::VL_16B)
561 .Case(".8h", AArch64Layout::VL_8H)
562 .Case(".4s", AArch64Layout::VL_4S)
563 .Case(".2d", AArch64Layout::VL_2D)
564 .Case(".b", AArch64Layout::VL_B)
565 .Case(".h", AArch64Layout::VL_H)
566 .Case(".s", AArch64Layout::VL_S)
567 .Case(".d", AArch64Layout::VL_D)
568 .Default(AArch64Layout::Invalid);
569 }
570
571 namespace AArch64SysReg {
572 struct SysReg {
573 const char *Name;
574 unsigned Encoding;
575 bool Readable;
576 bool Writeable;
577 FeatureBitset FeaturesRequired;
578
haveFeaturesSysReg579 bool haveFeatures(FeatureBitset ActiveFeatures) const {
580 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired;
581 }
582 };
583
584 #define GET_SYSREG_DECL
585 #include "AArch64GenSystemOperands.inc"
586
587 const SysReg *lookupSysRegByName(StringRef);
588 const SysReg *lookupSysRegByEncoding(uint16_t);
589
590 uint32_t parseGenericRegister(StringRef Name);
591 std::string genericRegisterString(uint32_t Bits);
592 }
593
594 namespace AArch64TLBI {
595 struct TLBI : SysAliasReg {
596 using SysAliasReg::SysAliasReg;
597 };
598 #define GET_TLBITable_DECL
599 #include "AArch64GenSystemOperands.inc"
600 }
601
602 namespace AArch64PRCTX {
603 struct PRCTX : SysAliasReg {
604 using SysAliasReg::SysAliasReg;
605 };
606 #define GET_PRCTX_DECL
607 #include "AArch64GenSystemOperands.inc"
608 }
609
610 namespace AArch64II {
611 /// Target Operand Flag enum.
612 enum TOF {
613 //===------------------------------------------------------------------===//
614 // AArch64 Specific MachineOperand flags.
615
616 MO_NO_FLAG,
617
618 MO_FRAGMENT = 0x7,
619
620 /// MO_PAGE - A symbol operand with this flag represents the pc-relative
621 /// offset of the 4K page containing the symbol. This is used with the
622 /// ADRP instruction.
623 MO_PAGE = 1,
624
625 /// MO_PAGEOFF - A symbol operand with this flag represents the offset of
626 /// that symbol within a 4K page. This offset is added to the page address
627 /// to produce the complete address.
628 MO_PAGEOFF = 2,
629
630 /// MO_G3 - A symbol operand with this flag (granule 3) represents the high
631 /// 16-bits of a 64-bit address, used in a MOVZ or MOVK instruction
632 MO_G3 = 3,
633
634 /// MO_G2 - A symbol operand with this flag (granule 2) represents the bits
635 /// 32-47 of a 64-bit address, used in a MOVZ or MOVK instruction
636 MO_G2 = 4,
637
638 /// MO_G1 - A symbol operand with this flag (granule 1) represents the bits
639 /// 16-31 of a 64-bit address, used in a MOVZ or MOVK instruction
640 MO_G1 = 5,
641
642 /// MO_G0 - A symbol operand with this flag (granule 0) represents the bits
643 /// 0-15 of a 64-bit address, used in a MOVZ or MOVK instruction
644 MO_G0 = 6,
645
646 /// MO_HI12 - This flag indicates that a symbol operand represents the bits
647 /// 13-24 of a 64-bit address, used in a arithmetic immediate-shifted-left-
648 /// by-12-bits instruction.
649 MO_HI12 = 7,
650
651 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
652 /// reference is actually to the ".refptr.FOO" symbol. This is used for
653 /// stub symbols on windows.
654 MO_COFFSTUB = 0x8,
655
656 /// MO_GOT - This flag indicates that a symbol operand represents the
657 /// address of the GOT entry for the symbol, rather than the address of
658 /// the symbol itself.
659 MO_GOT = 0x10,
660
661 /// MO_NC - Indicates whether the linker is expected to check the symbol
662 /// reference for overflow. For example in an ADRP/ADD pair of relocations
663 /// the ADRP usually does check, but not the ADD.
664 MO_NC = 0x20,
665
666 /// MO_TLS - Indicates that the operand being accessed is some kind of
667 /// thread-local symbol. On Darwin, only one type of thread-local access
668 /// exists (pre linker-relaxation), but on ELF the TLSModel used for the
669 /// referee will affect interpretation.
670 MO_TLS = 0x40,
671
672 /// MO_DLLIMPORT - On a symbol operand, this represents that the reference
673 /// to the symbol is for an import stub. This is used for DLL import
674 /// storage class indication on Windows.
675 MO_DLLIMPORT = 0x80,
676
677 /// MO_S - Indicates that the bits of the symbol operand represented by
678 /// MO_G0 etc are signed.
679 MO_S = 0x100,
680
681 /// MO_PREL - Indicates that the bits of the symbol operand represented by
682 /// MO_G0 etc are PC relative.
683 MO_PREL = 0x200,
684
685 /// MO_TAGGED - With MO_PAGE, indicates that the page includes a memory tag
686 /// in bits 56-63.
687 /// On a FrameIndex operand, indicates that the underlying memory is tagged
688 /// with an unknown tag value (MTE); this needs to be lowered either to an
689 /// SP-relative load or store instruction (which do not check tags), or to
690 /// an LDG instruction to obtain the tag value.
691 MO_TAGGED = 0x400,
692 };
693 } // end namespace AArch64II
694
695 namespace AArch64 {
696 // The number of bits in a SVE register is architecturally defined
697 // to be a multiple of this value. If <M x t> has this number of bits,
698 // a <n x M x t> vector can be stored in a SVE register without any
699 // redundant bits. If <M x t> has this number of bits divided by P,
700 // a <n x M x t> vector is stored in a SVE register by placing index i
701 // in index i*P of a <n x (M*P) x t> vector. The other elements of the
702 // <n x (M*P) x t> vector (such as index 1) are undefined.
703 static constexpr unsigned SVEBitsPerBlock = 128;
704 static constexpr unsigned SVEMaxBitsPerVector = 2048;
705 const unsigned NeonBitsPerVector = 128;
706 } // end namespace AArch64
707 } // end namespace llvm
708
709 #endif
710