1//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --------------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains DAG node definitions for the AMDGPU target.
10//
11//===----------------------------------------------------------------------===//
12
13//===----------------------------------------------------------------------===//
14// AMDGPU DAG Profiles
15//===----------------------------------------------------------------------===//
16
17def AMDGPUDTIntTernaryOp : SDTypeProfile<1, 3, [
18  SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>, SDTCisInt<3>
19]>;
20
21def AMDGPULdExpOp : SDTypeProfile<1, 2,
22  [SDTCisSameAs<0, 1>, SDTCisFP<0>, SDTCisInt<2>]
23>;
24
25def AMDGPUFPClassOp : SDTypeProfile<1, 2,
26  [SDTCisInt<0>, SDTCisFP<1>, SDTCisInt<2>]
27>;
28
29def AMDGPUFPPackOp : SDTypeProfile<1, 2,
30  [SDTCisFP<1>, SDTCisSameAs<1, 2>]
31>;
32
33def AMDGPUIntPackOp : SDTypeProfile<1, 2,
34  [SDTCisInt<1>, SDTCisSameAs<1, 2>]
35>;
36
37def AMDGPUDivScaleOp : SDTypeProfile<2, 3,
38  [SDTCisFP<0>, SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisSameAs<0, 4>]
39>;
40
41// float, float, float, vcc
42def AMDGPUFmasOp : SDTypeProfile<1, 4,
43  [SDTCisFP<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, SDTCisInt<4>]
44>;
45
46def AMDGPUKillSDT : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
47
48def AMDGPUIfOp : SDTypeProfile<1, 2,
49  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
50>;
51
52def AMDGPUElseOp : SDTypeProfile<1, 2,
53  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, OtherVT>]
54>;
55
56def AMDGPULoopOp : SDTypeProfile<0, 2,
57  [SDTCisVT<0, i1>, SDTCisVT<1, OtherVT>]
58>;
59
60def AMDGPUIfBreakOp : SDTypeProfile<1, 2,
61  [SDTCisVT<0, i1>, SDTCisVT<1, i1>, SDTCisVT<2, i1>]
62>;
63
64//===----------------------------------------------------------------------===//
65// AMDGPU DAG Nodes
66//
67
68def AMDGPUif : SDNode<"AMDGPUISD::IF", AMDGPUIfOp, [SDNPHasChain]>;
69def AMDGPUelse : SDNode<"AMDGPUISD::ELSE", AMDGPUElseOp, [SDNPHasChain]>;
70def AMDGPUloop : SDNode<"AMDGPUISD::LOOP", AMDGPULoopOp, [SDNPHasChain]>;
71
72def callseq_start : SDNode<"ISD::CALLSEQ_START",
73  SDCallSeqStart<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
74  [SDNPHasChain, SDNPOutGlue]
75>;
76
77def callseq_end : SDNode<"ISD::CALLSEQ_END",
78 SDCallSeqEnd<[ SDTCisVT<0, i32>, SDTCisVT<1, i32> ]>,
79  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]
80>;
81
82def AMDGPUcall : SDNode<"AMDGPUISD::CALL",
83  SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
84  [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
85  SDNPVariadic]
86>;
87
88def AMDGPUtc_return: SDNode<"AMDGPUISD::TC_RETURN",
89  SDTypeProfile<0, 3, [SDTCisPtrTy<0>]>,
90  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
91>;
92
93def AMDGPUtrap : SDNode<"AMDGPUISD::TRAP",
94  SDTypeProfile<0, -1, [SDTCisVT<0, i16>]>,
95    [SDNPHasChain, SDNPVariadic, SDNPSideEffect, SDNPInGlue]
96>;
97
98def AMDGPUconstdata_ptr : SDNode<
99  "AMDGPUISD::CONST_DATA_PTR", SDTypeProfile <1, 1, [SDTCisVT<0, iPTR>,
100                                                     SDTCisVT<0, iPTR>]>
101>;
102
103// This argument to this node is a dword address.
104def AMDGPUdwordaddr : SDNode<"AMDGPUISD::DWORDADDR", SDTIntUnaryOp>;
105
106// Force dependencies for vector trunc stores
107def R600dummy_chain : SDNode<"AMDGPUISD::DUMMY_CHAIN", SDTNone, [SDNPHasChain]>;
108
109def AMDGPUcos_impl : SDNode<"AMDGPUISD::COS_HW", SDTFPUnaryOp>;
110def AMDGPUsin_impl : SDNode<"AMDGPUISD::SIN_HW", SDTFPUnaryOp>;
111// out = a - floor(a)
112def AMDGPUfract_impl : SDNode<"AMDGPUISD::FRACT", SDTFPUnaryOp>;
113
114// out = 1.0 / a
115def AMDGPUrcp_impl : SDNode<"AMDGPUISD::RCP", SDTFPUnaryOp>;
116
117// out = 1.0 / sqrt(a)
118def AMDGPUrsq_impl : SDNode<"AMDGPUISD::RSQ", SDTFPUnaryOp>;
119
120def AMDGPUrcp_legacy_impl : SDNode<"AMDGPUISD::RCP_LEGACY", SDTFPUnaryOp>;
121
122def AMDGPUrcp_iflag : SDNode<"AMDGPUISD::RCP_IFLAG", SDTFPUnaryOp>;
123
124// out = 1.0 / sqrt(a) result clamped to +/- max_float.
125def AMDGPUrsq_clamp_impl : SDNode<"AMDGPUISD::RSQ_CLAMP", SDTFPUnaryOp>;
126
127def AMDGPUldexp_impl : SDNode<"AMDGPUISD::LDEXP", AMDGPULdExpOp>;
128
129def AMDGPUpkrtz_f16_f32_impl : SDNode<"AMDGPUISD::CVT_PKRTZ_F16_F32", AMDGPUFPPackOp>;
130def AMDGPUpknorm_i16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_I16_F32", AMDGPUFPPackOp>;
131def AMDGPUpknorm_u16_f32_impl : SDNode<"AMDGPUISD::CVT_PKNORM_U16_F32", AMDGPUFPPackOp>;
132def AMDGPUpk_i16_i32_impl : SDNode<"AMDGPUISD::CVT_PK_I16_I32", AMDGPUIntPackOp>;
133def AMDGPUpk_u16_u32_impl : SDNode<"AMDGPUISD::CVT_PK_U16_U32", AMDGPUIntPackOp>;
134def AMDGPUfp_to_f16 : SDNode<"AMDGPUISD::FP_TO_FP16" , SDTFPToIntOp>;
135
136
137def AMDGPUfp_class_impl : SDNode<"AMDGPUISD::FP_CLASS", AMDGPUFPClassOp>;
138
139// out = max(a, b) a and b are floats, where a nan comparison fails.
140// This is not commutative because this gives the second operand:
141//   x < nan ? x : nan -> nan
142//   nan < x ? nan : x -> x
143def AMDGPUfmax_legacy : SDNode<"AMDGPUISD::FMAX_LEGACY", SDTFPBinOp,
144  []
145>;
146
147def AMDGPUfmul_legacy_impl : SDNode<"AMDGPUISD::FMUL_LEGACY", SDTFPBinOp,
148  [SDNPCommutative, SDNPAssociative]
149>;
150
151// out = min(a, b) a and b are floats, where a nan comparison fails.
152def AMDGPUfmin_legacy : SDNode<"AMDGPUISD::FMIN_LEGACY", SDTFPBinOp,
153  []
154>;
155
156// FIXME: TableGen doesn't like commutative instructions with more
157// than 2 operands.
158// out = max(a, b, c) a, b and c are floats
159def AMDGPUfmax3 : SDNode<"AMDGPUISD::FMAX3", SDTFPTernaryOp,
160  [/*SDNPCommutative, SDNPAssociative*/]
161>;
162
163// out = max(a, b, c) a, b, and c are signed ints
164def AMDGPUsmax3 : SDNode<"AMDGPUISD::SMAX3", AMDGPUDTIntTernaryOp,
165  [/*SDNPCommutative, SDNPAssociative*/]
166>;
167
168// out = max(a, b, c) a, b and c are unsigned ints
169def AMDGPUumax3 : SDNode<"AMDGPUISD::UMAX3", AMDGPUDTIntTernaryOp,
170  [/*SDNPCommutative, SDNPAssociative*/]
171>;
172
173// out = min(a, b, c) a, b and c are floats
174def AMDGPUfmin3 : SDNode<"AMDGPUISD::FMIN3", SDTFPTernaryOp,
175  [/*SDNPCommutative, SDNPAssociative*/]
176>;
177
178// out = min(a, b, c) a, b and c are signed ints
179def AMDGPUsmin3 : SDNode<"AMDGPUISD::SMIN3", AMDGPUDTIntTernaryOp,
180  [/*SDNPCommutative, SDNPAssociative*/]
181>;
182
183// out = min(a, b) a and b are unsigned ints
184def AMDGPUumin3 : SDNode<"AMDGPUISD::UMIN3", AMDGPUDTIntTernaryOp,
185  [/*SDNPCommutative, SDNPAssociative*/]
186>;
187
188// out = (src0 + src1 > 0xFFFFFFFF) ? 1 : 0
189def AMDGPUcarry : SDNode<"AMDGPUISD::CARRY", SDTIntBinOp, []>;
190
191// out = (src1 > src0) ? 1 : 0
192def AMDGPUborrow : SDNode<"AMDGPUISD::BORROW", SDTIntBinOp, []>;
193
194def AMDGPUSetCCOp : SDTypeProfile<1, 3, [        // setcc
195  SDTCisInt<0>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>
196]>;
197
198def AMDGPUsetcc : SDNode<"AMDGPUISD::SETCC", AMDGPUSetCCOp>;
199
200def AMDGPUfma : SDNode<"AMDGPUISD::FMA_W_CHAIN", SDTFPTernaryOp, [
201   SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
202
203def AMDGPUmul : SDNode<"AMDGPUISD::FMUL_W_CHAIN", SDTFPBinOp, [
204  SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
205
206def AMDGPUcvt_f32_ubyte0 : SDNode<"AMDGPUISD::CVT_F32_UBYTE0",
207  SDTIntToFPOp, []>;
208def AMDGPUcvt_f32_ubyte1 : SDNode<"AMDGPUISD::CVT_F32_UBYTE1",
209  SDTIntToFPOp, []>;
210def AMDGPUcvt_f32_ubyte2 : SDNode<"AMDGPUISD::CVT_F32_UBYTE2",
211  SDTIntToFPOp, []>;
212def AMDGPUcvt_f32_ubyte3 : SDNode<"AMDGPUISD::CVT_F32_UBYTE3",
213  SDTIntToFPOp, []>;
214
215def AMDGPUcvt_pk_i16_i32 : SDNode<"AMDGPUISD::CVT_PK_I16_I32",
216  AMDGPUIntPackOp, []>;
217
218// urecip - This operation is a helper for integer division, it returns the
219// result of 1 / a as a fractional unsigned integer.
220// out = (2^32 / a) + e
221// e is rounding error
222def AMDGPUurecip : SDNode<"AMDGPUISD::URECIP", SDTIntUnaryOp>;
223
224// Special case divide preop and flags.
225def AMDGPUdiv_scale : SDNode<"AMDGPUISD::DIV_SCALE", AMDGPUDivScaleOp>;
226
227//  Special case divide FMA with scale and flags (src0 = Quotient,
228//  src1 = Denominator, src2 = Numerator).
229def AMDGPUdiv_fmas_impl : SDNode<"AMDGPUISD::DIV_FMAS", AMDGPUFmasOp,
230                            [SDNPOptInGlue]>;
231
232// Single or double precision division fixup.
233// Special case divide fixup and flags(src0 = Quotient, src1 =
234// Denominator, src2 = Numerator).
235def AMDGPUdiv_fixup_impl : SDNode<"AMDGPUISD::DIV_FIXUP", SDTFPTernaryOp>;
236
237def AMDGPUfmad_ftz_impl : SDNode<"AMDGPUISD::FMAD_FTZ", SDTFPTernaryOp>;
238
239def AMDGPUregister_load : SDNode<"AMDGPUISD::REGISTER_LOAD",
240                          SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
241                          [SDNPHasChain, SDNPMayLoad]>;
242
243def AMDGPUregister_store : SDNode<"AMDGPUISD::REGISTER_STORE",
244                           SDTypeProfile<0, 3, [SDTCisPtrTy<1>, SDTCisInt<2>]>,
245                           [SDNPHasChain, SDNPMayStore]>;
246
247// MSKOR instructions are atomic memory instructions used mainly for storing
248// 8-bit and 16-bit values.  The definition is:
249//
250// MSKOR(dst, mask, src) MEM[dst] = ((MEM[dst] & ~mask) | src)
251//
252// src0: vec4(src, 0, 0, mask)
253// src1: dst - rat offset (aka pointer) in dwords
254def AMDGPUstore_mskor : SDNode<"AMDGPUISD::STORE_MSKOR",
255                        SDTypeProfile<0, 2, []>,
256                        [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
257
258def AMDGPUatomic_cmp_swap : SDNode<"AMDGPUISD::ATOMIC_CMP_SWAP",
259                            SDTypeProfile<1, 2, [SDTCisPtrTy<1>, SDTCisVec<2>]>,
260                            [SDNPHasChain, SDNPMayStore, SDNPMayLoad,
261                             SDNPMemOperand]>;
262
263def AMDGPUround : SDNode<"ISD::FROUND",
264                         SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>>;
265
266def AMDGPUbfe_u32_impl : SDNode<"AMDGPUISD::BFE_U32", AMDGPUDTIntTernaryOp>;
267def AMDGPUbfe_i32_impl : SDNode<"AMDGPUISD::BFE_I32", AMDGPUDTIntTernaryOp>;
268def AMDGPUbfi : SDNode<"AMDGPUISD::BFI", AMDGPUDTIntTernaryOp>;
269def AMDGPUbfm : SDNode<"AMDGPUISD::BFM", SDTIntBinOp>;
270
271def AMDGPUffbh_u32_impl : SDNode<"AMDGPUISD::FFBH_U32", SDTIntBitCountUnaryOp>;
272def AMDGPUffbh_i32_impl : SDNode<"AMDGPUISD::FFBH_I32", SDTIntBitCountUnaryOp>;
273
274def AMDGPUffbl_b32_impl : SDNode<"AMDGPUISD::FFBL_B32", SDTIntBitCountUnaryOp>;
275
276// Signed and unsigned 24-bit multiply. The highest 8-bits are ignore
277// when performing the multiply. The result is a 32-bit value.
278def AMDGPUmul_u24_impl : SDNode<"AMDGPUISD::MUL_U24", SDTIntBinOp,
279  [SDNPCommutative, SDNPAssociative]
280>;
281def AMDGPUmul_i24_impl : SDNode<"AMDGPUISD::MUL_I24", SDTIntBinOp,
282  [SDNPCommutative, SDNPAssociative]
283>;
284
285def AMDGPUmulhi_u24 : SDNode<"AMDGPUISD::MULHI_U24", SDTIntBinOp,
286  [SDNPCommutative, SDNPAssociative]
287>;
288def AMDGPUmulhi_i24 : SDNode<"AMDGPUISD::MULHI_I24", SDTIntBinOp,
289  [SDNPCommutative, SDNPAssociative]
290>;
291
292def AMDGPUmad_u24 : SDNode<"AMDGPUISD::MAD_U24", AMDGPUDTIntTernaryOp,
293  []
294>;
295def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp,
296  []
297>;
298
299def AMDGPUsmed3 : SDNode<"AMDGPUISD::SMED3", AMDGPUDTIntTernaryOp,
300  []
301>;
302
303def AMDGPUumed3 : SDNode<"AMDGPUISD::UMED3", AMDGPUDTIntTernaryOp,
304  []
305>;
306
307def AMDGPUfmed3_impl : SDNode<"AMDGPUISD::FMED3", SDTFPTernaryOp, []>;
308
309def AMDGPUfdot2_impl : SDNode<"AMDGPUISD::FDOT2",
310                  SDTypeProfile<1, 4, [SDTCisSameAs<0, 3>, SDTCisSameAs<1, 2>,
311                                       SDTCisFP<0>, SDTCisVec<1>,
312                                       SDTCisInt<4>]>,
313                  []>;
314
315def AMDGPUperm_impl : SDNode<"AMDGPUISD::PERM", AMDGPUDTIntTernaryOp, []>;
316
317// SI+ export
318def AMDGPUExportOp : SDTypeProfile<0, 8, [
319  SDTCisInt<0>,       // i8 tgt
320  SDTCisInt<1>,       // i8 en
321                      // i32 or f32 src0
322  SDTCisSameAs<3, 2>, // f32 src1
323  SDTCisSameAs<4, 2>, // f32 src2
324  SDTCisSameAs<5, 2>, // f32 src3
325  SDTCisInt<6>,       // i1 compr
326  // skip done
327  SDTCisInt<1>        // i1 vm
328
329]>;
330
331
332def R600ExportOp : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
333
334def R600_EXPORT: SDNode<"AMDGPUISD::R600_EXPORT", R600ExportOp,
335  [SDNPHasChain, SDNPSideEffect]>;
336
337//===----------------------------------------------------------------------===//
338// Flow Control Profile Types
339//===----------------------------------------------------------------------===//
340// Branch instruction where second and third are basic blocks
341def SDTIL_BRCond : SDTypeProfile<0, 2, [
342    SDTCisVT<0, OtherVT>
343    ]>;
344
345//===----------------------------------------------------------------------===//
346// Flow Control DAG Nodes
347//===----------------------------------------------------------------------===//
348def IL_brcond      : SDNode<"AMDGPUISD::BRANCH_COND", SDTIL_BRCond, [SDNPHasChain]>;
349
350//===----------------------------------------------------------------------===//
351// Call/Return DAG Nodes
352//===----------------------------------------------------------------------===//
353def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone,
354    [SDNPHasChain, SDNPOptInGlue]>;
355
356def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone,
357    [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
358
359def AMDGPUret_flag : SDNode<"AMDGPUISD::RET_FLAG", SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>,
360  [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]
361>;
362
363
364//===----------------------------------------------------------------------===//
365// Intrinsic/Custom node compatibility PatFrags
366//===----------------------------------------------------------------------===//
367
368def AMDGPUrcp : PatFrags<(ops node:$src), [(int_amdgcn_rcp node:$src),
369                                           (AMDGPUrcp_impl node:$src)]>;
370def AMDGPUrcp_legacy : PatFrags<(ops node:$src), [(int_amdgcn_rcp_legacy node:$src),
371                                                  (AMDGPUrcp_legacy_impl node:$src)]>;
372
373def AMDGPUrsq : PatFrags<(ops node:$src), [(int_amdgcn_rsq node:$src),
374                                           (AMDGPUrsq_impl node:$src)]>;
375
376def AMDGPUrsq_clamp : PatFrags<(ops node:$src), [(int_amdgcn_rsq_clamp node:$src),
377                                                 (AMDGPUrsq_clamp_impl node:$src)]>;
378
379def AMDGPUsin : PatFrags<(ops node:$src), [(int_amdgcn_sin node:$src),
380                                           (AMDGPUsin_impl node:$src)]>;
381def AMDGPUcos : PatFrags<(ops node:$src), [(int_amdgcn_cos node:$src),
382                                           (AMDGPUcos_impl node:$src)]>;
383def AMDGPUfract : PatFrags<(ops node:$src), [(int_amdgcn_fract node:$src),
384                                             (AMDGPUfract_impl node:$src)]>;
385
386def AMDGPUldexp : PatFrags<(ops node:$src0, node:$src1),
387  [(int_amdgcn_ldexp node:$src0, node:$src1),
388   (AMDGPUldexp_impl node:$src0, node:$src1)]>;
389
390def AMDGPUfp_class : PatFrags<(ops node:$src0, node:$src1),
391  [(int_amdgcn_class node:$src0, node:$src1),
392  (AMDGPUfp_class_impl node:$src0, node:$src1)]>;
393
394def AMDGPUfmed3 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
395  [(int_amdgcn_fmed3 node:$src0, node:$src1, node:$src2),
396   (AMDGPUfmed3_impl node:$src0, node:$src1, node:$src2)]>;
397
398def AMDGPUdiv_fixup : PatFrags<(ops node:$src0, node:$src1, node:$src2),
399  [(int_amdgcn_div_fixup node:$src0, node:$src1, node:$src2),
400   (AMDGPUdiv_fixup_impl node:$src0, node:$src1, node:$src2)]>;
401
402def AMDGPUffbh_i32 : PatFrags<(ops node:$src),
403  [(int_amdgcn_sffbh node:$src),
404   (AMDGPUffbh_i32_impl node:$src)]>;
405
406def AMDGPUffbh_u32 : PatFrags<(ops node:$src),
407  [(ctlz_zero_undef node:$src),
408   (AMDGPUffbh_u32_impl node:$src)]>;
409
410def AMDGPUffbl_b32 : PatFrags<(ops node:$src),
411  [(cttz_zero_undef node:$src),
412   (AMDGPUffbl_b32_impl node:$src)]>;
413
414def AMDGPUpkrtz_f16_f32 : PatFrags<(ops node:$src0, node:$src1),
415  [(int_amdgcn_cvt_pkrtz node:$src0, node:$src1),
416  (AMDGPUpkrtz_f16_f32_impl node:$src0, node:$src1)]>;
417
418def AMDGPUpknorm_i16_f32 : PatFrags<(ops node:$src0, node:$src1),
419  [(int_amdgcn_cvt_pknorm_i16 node:$src0, node:$src1),
420  (AMDGPUpknorm_i16_f32_impl node:$src0, node:$src1)]>;
421
422def AMDGPUpknorm_u16_f32 : PatFrags<(ops node:$src0, node:$src1),
423  [(int_amdgcn_cvt_pknorm_u16 node:$src0, node:$src1),
424  (AMDGPUpknorm_u16_f32_impl node:$src0, node:$src1)]>;
425
426def AMDGPUpk_i16_i32 : PatFrags<(ops node:$src0, node:$src1),
427  [(int_amdgcn_cvt_pk_i16 node:$src0, node:$src1),
428  (AMDGPUpk_i16_i32_impl node:$src0, node:$src1)]>;
429
430def AMDGPUpk_u16_u32 : PatFrags<(ops node:$src0, node:$src1),
431  [(int_amdgcn_cvt_pk_u16 node:$src0, node:$src1),
432  (AMDGPUpk_u16_u32_impl node:$src0, node:$src1)]>;
433
434def AMDGPUfmad_ftz : PatFrags<(ops node:$src0, node:$src1, node:$src2),
435  [(int_amdgcn_fmad_ftz node:$src0, node:$src1, node:$src2),
436   (AMDGPUfmad_ftz_impl node:$src0, node:$src1, node:$src2)]>;
437
438def AMDGPUmul_u24 : PatFrags<(ops node:$src0, node:$src1),
439  [(int_amdgcn_mul_u24 node:$src0, node:$src1),
440   (AMDGPUmul_u24_impl node:$src0, node:$src1)]>;
441
442def AMDGPUmul_i24 : PatFrags<(ops node:$src0, node:$src1),
443  [(int_amdgcn_mul_i24 node:$src0, node:$src1),
444   (AMDGPUmul_i24_impl node:$src0, node:$src1)]>;
445
446def AMDGPUbfe_i32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
447  [(int_amdgcn_sbfe node:$src0, node:$src1, node:$src2),
448   (AMDGPUbfe_i32_impl node:$src0, node:$src1, node:$src2)]>;
449
450def AMDGPUbfe_u32 : PatFrags<(ops node:$src0, node:$src1, node:$src2),
451  [(int_amdgcn_ubfe node:$src0, node:$src1, node:$src2),
452   (AMDGPUbfe_u32_impl node:$src0, node:$src1, node:$src2)]>;
453
454def AMDGPUfmul_legacy : PatFrags<(ops node:$src0, node:$src1),
455  [(int_amdgcn_fmul_legacy node:$src0, node:$src1),
456   (AMDGPUfmul_legacy_impl node:$src0, node:$src1)]>;
457
458def AMDGPUfdot2 : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$clamp),
459  [(int_amdgcn_fdot2 node:$src0, node:$src1, node:$src2, node:$clamp),
460   (AMDGPUfdot2_impl node:$src0, node:$src1, node:$src2, node:$clamp)]>;
461
462def AMDGPUdiv_fmas : PatFrags<(ops node:$src0, node:$src1, node:$src2, node:$vcc),
463  [(int_amdgcn_div_fmas node:$src0, node:$src1, node:$src2, node:$vcc),
464   (AMDGPUdiv_fmas_impl node:$src0, node:$src1, node:$src2, node:$vcc)]>;
465
466def AMDGPUperm : PatFrags<(ops node:$src0, node:$src1, node:$src2),
467  [(int_amdgcn_perm node:$src0, node:$src1, node:$src2),
468   (AMDGPUperm_impl node:$src0, node:$src1, node:$src2)]>;
469