1//===-- DSInstructions.td - DS Instruction Definitions --------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
10  InstSI <outs, ins, "", pattern>,
11  SIMCInstr <opName, SIEncodingFamily.NONE> {
12
13  let LGKM_CNT = 1;
14  let DS = 1;
15  let Size = 8;
16  let UseNamedOperandTable = 1;
17
18  // Most instruction load and store data, so set this as the default.
19  let mayLoad = 1;
20  let mayStore = 1;
21  let maybeAtomic = 1;
22
23  let hasSideEffects = 0;
24  let SchedRW = [WriteLDS];
25
26  let isPseudo = 1;
27  let isCodeGenOnly = 1;
28
29  let AsmMatchConverter = "cvtDS";
30
31  string Mnemonic = opName;
32  string AsmOperands = asmOps;
33
34  // Well these bits a kind of hack because it would be more natural
35  // to test "outs" and "ins" dags for the presence of particular operands
36  bits<1> has_vdst = 1;
37  bits<1> has_addr = 1;
38  bits<1> has_data0 = 1;
39  bits<1> has_data1 = 1;
40
41  bits<1> has_gws_data0 = 0; // data0 is encoded as addr
42
43  bits<1> has_offset  = 1; // has "offset" that should be split to offset0,1
44  bits<1> has_offset0 = 1;
45  bits<1> has_offset1 = 1;
46
47  bits<1> has_gds = 1;
48  bits<1> gdsValue = 0; // if has_gds == 0 set gds to this value
49
50  bits<1> has_m0_read = 1;
51
52  let Uses = !if(has_m0_read, [M0, EXEC], [EXEC]);
53}
54
55class DS_Real <DS_Pseudo ps> :
56  InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
57  Enc64 {
58
59  let isPseudo = 0;
60  let isCodeGenOnly = 0;
61  let LGKM_CNT = 1;
62  let DS = 1;
63  let UseNamedOperandTable = 1;
64
65  // copy relevant pseudo op flags
66  let SubtargetPredicate = ps.SubtargetPredicate;
67  let OtherPredicates    = ps.OtherPredicates;
68  let AsmMatchConverter  = ps.AsmMatchConverter;
69  let SchedRW            = ps.SchedRW;
70  let mayLoad            = ps.mayLoad;
71  let mayStore           = ps.mayStore;
72  let IsAtomicRet        = ps.IsAtomicRet;
73  let IsAtomicNoRet      = ps.IsAtomicNoRet;
74
75  // encoding fields
76  bits<10> vdst;
77  bits<1> gds;
78  bits<8> addr;
79  bits<10> data0;
80  bits<10> data1;
81  bits<8> offset0;
82  bits<8> offset1;
83
84  bits<16> offset;
85  let offset0 = !if(ps.has_offset, offset{7-0}, ?);
86  let offset1 = !if(ps.has_offset, offset{15-8}, ?);
87
88  bits<1> acc = !if(ps.has_vdst, vdst{9},
89                    !if(!or(ps.has_data0, ps.has_gws_data0), data0{9}, 0));
90}
91
92
93// DS Pseudo instructions
94
95class DS_0A1D_NORET<string opName, RegisterClass rc = VGPR_32>
96: DS_Pseudo<opName,
97  (outs),
98  (ins getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
99  " $data0$offset$gds"> {
100
101  let has_addr = 0;
102  let has_data1 = 0;
103  let has_vdst = 0;
104}
105
106class DS_1A1D_NORET<string opName, RegisterClass rc = VGPR_32>
107: DS_Pseudo<opName,
108  (outs),
109  (ins VGPR_32:$addr, getLdStRegisterOperand<rc>.ret:$data0, offset:$offset, gds:$gds),
110  " $addr, $data0$offset$gds"> {
111
112  let has_data1 = 0;
113  let has_vdst = 0;
114  let IsAtomicNoRet = 1;
115}
116
117multiclass DS_1A1D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
118  def "" : DS_1A1D_NORET<opName, rc>,
119           AtomicNoRet<opName, 0>;
120
121  let has_m0_read = 0 in {
122    def _gfx9 : DS_1A1D_NORET<opName, rc>,
123                AtomicNoRet<opName#"_gfx9", 0>;
124  }
125}
126
127multiclass DS_1A1D_NORET_mc_gfx9<string opName, RegisterClass rc = VGPR_32> {
128  let has_m0_read = 0 in {
129    def "" : DS_1A1D_NORET<opName, rc>,
130                AtomicNoRet<opName, 0>;
131  }
132}
133
134class DS_1A2D_NORET<string opName, RegisterClass rc = VGPR_32,
135                    RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
136: DS_Pseudo<opName,
137  (outs),
138  (ins VGPR_32:$addr, data_op:$data0, data_op:$data1, offset:$offset, gds:$gds),
139  " $addr, $data0, $data1$offset$gds"> {
140
141  let has_vdst = 0;
142  let IsAtomicNoRet = 1;
143}
144
145multiclass DS_1A2D_NORET_mc<string opName, RegisterClass rc = VGPR_32> {
146  def "" : DS_1A2D_NORET<opName, rc>,
147           AtomicNoRet<opName, 0>;
148
149  let has_m0_read = 0 in {
150    def _gfx9 : DS_1A2D_NORET<opName, rc>,
151                AtomicNoRet<opName#"_gfx9", 0>;
152  }
153}
154
155class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32,
156                          RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
157: DS_Pseudo<opName,
158  (outs),
159  (ins VGPR_32:$addr, data_op:$data0, data_op:$data1,
160       offset0:$offset0, offset1:$offset1, gds:$gds),
161  " $addr, $data0, $data1$offset0$offset1$gds"> {
162
163  let has_vdst = 0;
164  let has_offset = 0;
165  let AsmMatchConverter = "cvtDSOffset01";
166}
167
168multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
169  def "" : DS_1A2D_Off8_NORET<opName, rc>;
170
171  let has_m0_read = 0 in {
172    def _gfx9 : DS_1A2D_Off8_NORET<opName, rc>;
173  }
174}
175
176class DS_1A1D_RET <string opName, RegisterClass rc = VGPR_32,
177                  RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
178: DS_Pseudo<opName,
179  (outs data_op:$vdst),
180  (ins VGPR_32:$addr, data_op:$data0, offset:$offset, gds:$gds),
181  " $vdst, $addr, $data0$offset$gds"> {
182
183  let hasPostISelHook = 1;
184  let has_data1 = 0;
185  let IsAtomicRet = 1;
186}
187
188multiclass DS_1A1D_RET_mc <string opName, RegisterClass rc = VGPR_32,
189                           string NoRetOp = ""> {
190  def "" : DS_1A1D_RET<opName, rc>,
191    AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
192
193  let has_m0_read = 0 in {
194    def _gfx9 : DS_1A1D_RET<opName, rc>,
195      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp#"_gfx9"),
196                  !ne(NoRetOp, "")>;
197  }
198}
199
200multiclass DS_1A1D_RET_mc_gfx9 <string opName, RegisterClass rc = VGPR_32,
201                                string NoRetOp = ""> {
202  let has_m0_read = 0 in {
203    def "" : DS_1A1D_RET<opName, rc>,
204      AtomicNoRet<!if(!eq(NoRetOp, ""), "", NoRetOp),
205                  !if(!eq(NoRetOp, ""), 0, 1)>;
206  }
207}
208
209class DS_1A2D_RET<string opName,
210                  RegisterClass rc = VGPR_32,
211                  RegisterClass src = rc,
212                  RegisterOperand dst_op = getLdStRegisterOperand<rc>.ret,
213                  RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
214: DS_Pseudo<opName,
215  (outs dst_op:$vdst),
216  (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset:$offset, gds:$gds),
217  " $vdst, $addr, $data0, $data1$offset$gds"> {
218
219  let hasPostISelHook = 1;
220  let IsAtomicRet = 1;
221}
222
223multiclass DS_1A2D_RET_mc<string opName,
224                          RegisterClass rc = VGPR_32,
225                          string NoRetOp = "",
226                          RegisterClass src = rc> {
227  def "" : DS_1A2D_RET<opName, rc, src>,
228    AtomicNoRet<NoRetOp, !ne(NoRetOp, "")>;
229
230  let has_m0_read = 0 in {
231    def _gfx9 : DS_1A2D_RET<opName, rc, src>,
232      AtomicNoRet<NoRetOp#"_gfx9", !ne(NoRetOp, "")>;
233  }
234}
235
236class DS_1A2D_Off8_RET<string opName,
237                       RegisterClass rc = VGPR_32,
238                       RegisterClass src = rc,
239                       RegisterOperand dst_op = getLdStRegisterOperand<rc>.ret,
240                       RegisterOperand src_op = getLdStRegisterOperand<src>.ret>
241: DS_Pseudo<opName,
242  (outs dst_op:$vdst),
243  (ins VGPR_32:$addr, src_op:$data0, src_op:$data1, offset0:$offset0, offset1:$offset1, gds:$gds),
244  " $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
245
246  let has_offset = 0;
247  let AsmMatchConverter = "cvtDSOffset01";
248
249  let hasPostISelHook = 1;
250}
251
252multiclass DS_1A2D_Off8_RET_mc<string opName,
253                               RegisterClass rc = VGPR_32,
254                               RegisterClass src = rc> {
255  def "" : DS_1A2D_Off8_RET<opName, rc, src>;
256
257  let has_m0_read = 0 in {
258    def _gfx9 : DS_1A2D_Off8_RET<opName, rc, src>;
259  }
260}
261
262
263class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset,
264                RegisterOperand data_op = getLdStRegisterOperand<rc>.ret>
265: DS_Pseudo<opName,
266  (outs data_op:$vdst),
267  !if(HasTiedOutput,
268    (ins VGPR_32:$addr, ofs:$offset, gds:$gds, data_op:$vdst_in),
269    (ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
270  " $vdst, $addr$offset$gds"> {
271  let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
272  let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
273  let has_data0 = 0;
274  let has_data1 = 0;
275}
276
277multiclass DS_1A_RET_mc<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0, Operand ofs = offset> {
278  def "" : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
279
280  let has_m0_read = 0 in {
281    def _gfx9 : DS_1A_RET<opName, rc, HasTiedOutput, ofs>;
282  }
283}
284
285class DS_1A_RET_Tied<string opName, RegisterClass rc = VGPR_32> :
286  DS_1A_RET<opName, rc, 1>;
287
288class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
289: DS_Pseudo<opName,
290  (outs getLdStRegisterOperand<rc>.ret:$vdst),
291  (ins VGPR_32:$addr, offset0:$offset0, offset1:$offset1, gds:$gds),
292  " $vdst, $addr$offset0$offset1$gds"> {
293
294  let has_offset = 0;
295  let has_data0 = 0;
296  let has_data1 = 0;
297  let AsmMatchConverter = "cvtDSOffset01";
298}
299
300multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
301  def "" : DS_1A_Off8_RET<opName, rc>;
302
303  let has_m0_read = 0 in {
304    def _gfx9 : DS_1A_Off8_RET<opName, rc>;
305  }
306}
307
308class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
309  (outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
310  (ins VGPR_32:$addr, offset:$offset),
311  " $vdst, $addr$offset gds"> {
312
313  let has_data0 = 0;
314  let has_data1 = 0;
315  let has_gds = 0;
316  let gdsValue = 1;
317  let AsmMatchConverter = "cvtDSGds";
318}
319
320class DS_0A_RET <string opName> : DS_Pseudo<opName,
321  (outs getLdStRegisterOperand<VGPR_32>.ret:$vdst),
322  (ins offset:$offset, gds:$gds),
323  " $vdst$offset$gds"> {
324
325  let mayLoad = 1;
326  let mayStore = 1;
327
328  let has_addr = 0;
329  let has_data0 = 0;
330  let has_data1 = 0;
331}
332
333class DS_1A <string opName> : DS_Pseudo<opName,
334  (outs),
335  (ins VGPR_32:$addr, offset:$offset, gds:$gds),
336  " $addr$offset$gds"> {
337
338  let mayLoad = 1;
339  let mayStore = 1;
340
341  let has_vdst = 0;
342  let has_data0 = 0;
343  let has_data1 = 0;
344}
345
346multiclass DS_1A_mc <string opName> {
347  def "" : DS_1A<opName>;
348
349  let has_m0_read = 0 in {
350    def _gfx9 : DS_1A<opName>;
351  }
352}
353
354
355class DS_GWS <string opName, dag ins, string asmOps>
356: DS_Pseudo<opName, (outs), ins, asmOps> {
357
358  let has_vdst  = 0;
359  let has_addr  = 0;
360  let has_data0 = 0;
361  let has_data1 = 0;
362
363  let has_gds   = 0;
364  let gdsValue  = 1;
365  let AsmMatchConverter = "cvtDSGds";
366}
367
368class DS_GWS_0D <string opName>
369: DS_GWS<opName,
370  (ins offset:$offset), "$offset gds"> {
371  let hasSideEffects = 1;
372}
373
374class DS_GWS_1D <string opName>
375: DS_GWS<opName,
376  (ins getLdStRegisterOperand<VGPR_32>.ret:$data0, offset:$offset),
377  " $data0$offset gds"> {
378
379  let has_gws_data0 = 1;
380  let hasSideEffects = 1;
381}
382
383class DS_VOID <string opName> : DS_Pseudo<opName,
384  (outs), (ins), ""> {
385  let mayLoad = 0;
386  let mayStore = 0;
387  let hasSideEffects = 1;
388  let UseNamedOperandTable = 0;
389  let AsmMatchConverter = "";
390
391  let has_vdst = 0;
392  let has_addr = 0;
393  let has_data0 = 0;
394  let has_data1 = 0;
395  let has_offset = 0;
396  let has_offset0 = 0;
397  let has_offset1 = 0;
398  let has_gds = 0;
399}
400
401class DS_1A1D_PERMUTE <string opName, SDPatternOperator node = null_frag,
402                       RegisterOperand data_op = getLdStRegisterOperand<VGPR_32>.ret>
403: DS_Pseudo<opName,
404  (outs data_op:$vdst),
405  (ins VGPR_32:$addr, data_op:$data0, offset:$offset),
406  " $vdst, $addr, $data0$offset",
407  [(set i32:$vdst,
408   (node (DS1Addr1Offset i32:$addr, i16:$offset), i32:$data0))] > {
409
410  let mayLoad = 0;
411  let mayStore = 0;
412  let isConvergent = 1;
413
414  let has_data1 = 0;
415  let has_gds = 0;
416}
417
418defm DS_ADD_U32       : DS_1A1D_NORET_mc<"ds_add_u32">;
419defm DS_SUB_U32       : DS_1A1D_NORET_mc<"ds_sub_u32">;
420defm DS_RSUB_U32      : DS_1A1D_NORET_mc<"ds_rsub_u32">;
421defm DS_INC_U32       : DS_1A1D_NORET_mc<"ds_inc_u32">;
422defm DS_DEC_U32       : DS_1A1D_NORET_mc<"ds_dec_u32">;
423defm DS_MIN_I32       : DS_1A1D_NORET_mc<"ds_min_i32">;
424defm DS_MAX_I32       : DS_1A1D_NORET_mc<"ds_max_i32">;
425defm DS_MIN_U32       : DS_1A1D_NORET_mc<"ds_min_u32">;
426defm DS_MAX_U32       : DS_1A1D_NORET_mc<"ds_max_u32">;
427defm DS_AND_B32       : DS_1A1D_NORET_mc<"ds_and_b32">;
428defm DS_OR_B32        : DS_1A1D_NORET_mc<"ds_or_b32">;
429defm DS_XOR_B32       : DS_1A1D_NORET_mc<"ds_xor_b32">;
430
431let SubtargetPredicate = HasLDSFPAtomics in {
432defm DS_ADD_F32       : DS_1A1D_NORET_mc<"ds_add_f32">;
433}
434
435// FIXME: Are these really present pre-gfx8?
436defm DS_MIN_F32       : DS_1A1D_NORET_mc<"ds_min_f32">;
437defm DS_MAX_F32       : DS_1A1D_NORET_mc<"ds_max_f32">;
438
439let mayLoad = 0 in {
440defm DS_WRITE_B8      : DS_1A1D_NORET_mc<"ds_write_b8">;
441defm DS_WRITE_B16     : DS_1A1D_NORET_mc<"ds_write_b16">;
442defm DS_WRITE_B32     : DS_1A1D_NORET_mc<"ds_write_b32">;
443defm DS_WRITE2_B32    : DS_1A2D_Off8_NORET_mc<"ds_write2_b32">;
444defm DS_WRITE2ST64_B32: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b32">;
445
446
447let has_m0_read = 0 in {
448
449let SubtargetPredicate = HasD16LoadStore in {
450def DS_WRITE_B8_D16_HI  : DS_1A1D_NORET<"ds_write_b8_d16_hi">;
451def DS_WRITE_B16_D16_HI : DS_1A1D_NORET<"ds_write_b16_d16_hi">;
452}
453
454} // End has_m0_read = 0
455
456let SubtargetPredicate = HasDSAddTid in {
457def DS_WRITE_ADDTID_B32 : DS_0A1D_NORET<"ds_write_addtid_b32">;
458}
459
460} // End mayLoad = 0
461
462let SubtargetPredicate = isGFX90APlus in {
463  defm DS_ADD_F64     : DS_1A1D_NORET_mc_gfx9<"ds_add_f64", VReg_64>;
464  defm DS_ADD_RTN_F64 : DS_1A1D_RET_mc_gfx9<"ds_add_rtn_f64", VReg_64, "ds_add_f64">;
465} // End SubtargetPredicate = isGFX90APlus
466
467defm DS_MSKOR_B32     : DS_1A2D_NORET_mc<"ds_mskor_b32">;
468defm DS_CMPST_B32     : DS_1A2D_NORET_mc<"ds_cmpst_b32">;
469defm DS_CMPST_F32     : DS_1A2D_NORET_mc<"ds_cmpst_f32">;
470
471defm DS_ADD_U64       : DS_1A1D_NORET_mc<"ds_add_u64", VReg_64>;
472defm DS_SUB_U64       : DS_1A1D_NORET_mc<"ds_sub_u64", VReg_64>;
473defm DS_RSUB_U64      : DS_1A1D_NORET_mc<"ds_rsub_u64", VReg_64>;
474defm DS_INC_U64       : DS_1A1D_NORET_mc<"ds_inc_u64", VReg_64>;
475defm DS_DEC_U64       : DS_1A1D_NORET_mc<"ds_dec_u64", VReg_64>;
476defm DS_MIN_I64       : DS_1A1D_NORET_mc<"ds_min_i64", VReg_64>;
477defm DS_MAX_I64       : DS_1A1D_NORET_mc<"ds_max_i64", VReg_64>;
478defm DS_MIN_U64       : DS_1A1D_NORET_mc<"ds_min_u64", VReg_64>;
479defm DS_MAX_U64       : DS_1A1D_NORET_mc<"ds_max_u64", VReg_64>;
480defm DS_AND_B64       : DS_1A1D_NORET_mc<"ds_and_b64", VReg_64>;
481defm DS_OR_B64        : DS_1A1D_NORET_mc<"ds_or_b64", VReg_64>;
482defm DS_XOR_B64       : DS_1A1D_NORET_mc<"ds_xor_b64", VReg_64>;
483defm DS_MSKOR_B64     : DS_1A2D_NORET_mc<"ds_mskor_b64", VReg_64>;
484let mayLoad = 0 in {
485defm DS_WRITE_B64     : DS_1A1D_NORET_mc<"ds_write_b64", VReg_64>;
486defm DS_WRITE2_B64    : DS_1A2D_Off8_NORET_mc<"ds_write2_b64", VReg_64>;
487defm DS_WRITE2ST64_B64: DS_1A2D_Off8_NORET_mc<"ds_write2st64_b64", VReg_64>;
488}
489defm DS_CMPST_B64     : DS_1A2D_NORET_mc<"ds_cmpst_b64", VReg_64>;
490defm DS_CMPST_F64     : DS_1A2D_NORET_mc<"ds_cmpst_f64", VReg_64>;
491defm DS_MIN_F64       : DS_1A1D_NORET_mc<"ds_min_f64", VReg_64>;
492defm DS_MAX_F64       : DS_1A1D_NORET_mc<"ds_max_f64", VReg_64>;
493
494defm DS_ADD_RTN_U32   : DS_1A1D_RET_mc<"ds_add_rtn_u32", VGPR_32, "ds_add_u32">;
495
496let SubtargetPredicate = HasLDSFPAtomics in {
497defm DS_ADD_RTN_F32   : DS_1A1D_RET_mc<"ds_add_rtn_f32", VGPR_32, "ds_add_f32">;
498}
499defm DS_SUB_RTN_U32   : DS_1A1D_RET_mc<"ds_sub_rtn_u32", VGPR_32, "ds_sub_u32">;
500defm DS_RSUB_RTN_U32  : DS_1A1D_RET_mc<"ds_rsub_rtn_u32", VGPR_32, "ds_rsub_u32">;
501defm DS_INC_RTN_U32   : DS_1A1D_RET_mc<"ds_inc_rtn_u32", VGPR_32, "ds_inc_u32">;
502defm DS_DEC_RTN_U32   : DS_1A1D_RET_mc<"ds_dec_rtn_u32", VGPR_32, "ds_dec_u32">;
503defm DS_MIN_RTN_I32   : DS_1A1D_RET_mc<"ds_min_rtn_i32", VGPR_32, "ds_min_i32">;
504defm DS_MAX_RTN_I32   : DS_1A1D_RET_mc<"ds_max_rtn_i32", VGPR_32, "ds_max_i32">;
505defm DS_MIN_RTN_U32   : DS_1A1D_RET_mc<"ds_min_rtn_u32", VGPR_32, "ds_min_u32">;
506defm DS_MAX_RTN_U32   : DS_1A1D_RET_mc<"ds_max_rtn_u32", VGPR_32, "ds_max_u32">;
507defm DS_AND_RTN_B32   : DS_1A1D_RET_mc<"ds_and_rtn_b32", VGPR_32, "ds_and_b32">;
508defm DS_OR_RTN_B32    : DS_1A1D_RET_mc<"ds_or_rtn_b32", VGPR_32, "ds_or_b32">;
509defm DS_XOR_RTN_B32   : DS_1A1D_RET_mc<"ds_xor_rtn_b32", VGPR_32, "ds_xor_b32">;
510defm DS_MSKOR_RTN_B32 : DS_1A2D_RET_mc<"ds_mskor_rtn_b32", VGPR_32, "ds_mskor_b32">;
511defm DS_CMPST_RTN_B32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_b32", VGPR_32, "ds_cmpst_b32">;
512defm DS_CMPST_RTN_F32 : DS_1A2D_RET_mc<"ds_cmpst_rtn_f32", VGPR_32, "ds_cmpst_f32">;
513defm DS_MIN_RTN_F32   : DS_1A1D_RET_mc<"ds_min_rtn_f32", VGPR_32, "ds_min_f32">;
514defm DS_MAX_RTN_F32   : DS_1A1D_RET_mc<"ds_max_rtn_f32", VGPR_32, "ds_max_f32">;
515
516defm DS_WRXCHG_RTN_B32 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b32">;
517defm DS_WRXCHG2_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b32", VReg_64, VGPR_32>;
518defm DS_WRXCHG2ST64_RTN_B32 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b32", VReg_64, VGPR_32>;
519
520defm DS_ADD_RTN_U64  : DS_1A1D_RET_mc<"ds_add_rtn_u64", VReg_64, "ds_add_u64">;
521defm DS_SUB_RTN_U64  : DS_1A1D_RET_mc<"ds_sub_rtn_u64", VReg_64, "ds_sub_u64">;
522defm DS_RSUB_RTN_U64  : DS_1A1D_RET_mc<"ds_rsub_rtn_u64", VReg_64, "ds_rsub_u64">;
523defm DS_INC_RTN_U64   : DS_1A1D_RET_mc<"ds_inc_rtn_u64", VReg_64, "ds_inc_u64">;
524defm DS_DEC_RTN_U64   : DS_1A1D_RET_mc<"ds_dec_rtn_u64", VReg_64, "ds_dec_u64">;
525defm DS_MIN_RTN_I64    : DS_1A1D_RET_mc<"ds_min_rtn_i64", VReg_64, "ds_min_i64">;
526defm DS_MAX_RTN_I64    : DS_1A1D_RET_mc<"ds_max_rtn_i64", VReg_64, "ds_max_i64">;
527defm DS_MIN_RTN_U64   : DS_1A1D_RET_mc<"ds_min_rtn_u64", VReg_64, "ds_min_u64">;
528defm DS_MAX_RTN_U64   : DS_1A1D_RET_mc<"ds_max_rtn_u64", VReg_64, "ds_max_u64">;
529defm DS_AND_RTN_B64    : DS_1A1D_RET_mc<"ds_and_rtn_b64", VReg_64, "ds_and_b64">;
530defm DS_OR_RTN_B64     : DS_1A1D_RET_mc<"ds_or_rtn_b64", VReg_64, "ds_or_b64">;
531defm DS_XOR_RTN_B64    : DS_1A1D_RET_mc<"ds_xor_rtn_b64", VReg_64, "ds_xor_b64">;
532defm DS_MSKOR_RTN_B64  : DS_1A2D_RET_mc<"ds_mskor_rtn_b64", VReg_64, "ds_mskor_b64">;
533defm DS_CMPST_RTN_B64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_b64", VReg_64, "ds_cmpst_b64">;
534defm DS_CMPST_RTN_F64  : DS_1A2D_RET_mc<"ds_cmpst_rtn_f64", VReg_64, "ds_cmpst_f64">;
535defm DS_MIN_RTN_F64    : DS_1A1D_RET_mc<"ds_min_rtn_f64", VReg_64, "ds_min_f64">;
536defm DS_MAX_RTN_F64    : DS_1A1D_RET_mc<"ds_max_rtn_f64", VReg_64, "ds_max_f64">;
537
538defm DS_WRXCHG_RTN_B64 : DS_1A1D_RET_mc<"ds_wrxchg_rtn_b64", VReg_64>;
539defm DS_WRXCHG2_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2_rtn_b64", VReg_128, VReg_64>;
540defm DS_WRXCHG2ST64_RTN_B64 : DS_1A2D_Off8_RET_mc<"ds_wrxchg2st64_rtn_b64", VReg_128, VReg_64>;
541
542let isConvergent = 1, usesCustomInserter = 1 in {
543def DS_GWS_INIT       : DS_GWS_1D<"ds_gws_init"> {
544  let mayLoad = 0;
545}
546def DS_GWS_SEMA_V     : DS_GWS_0D<"ds_gws_sema_v">;
547def DS_GWS_SEMA_BR    : DS_GWS_1D<"ds_gws_sema_br">;
548def DS_GWS_SEMA_P     : DS_GWS_0D<"ds_gws_sema_p">;
549def DS_GWS_BARRIER    : DS_GWS_1D<"ds_gws_barrier">;
550}
551
552let SubtargetPredicate = HasDsSrc2Insts in {
553def DS_ADD_SRC2_U32   : DS_1A<"ds_add_src2_u32">;
554def DS_SUB_SRC2_U32   : DS_1A<"ds_sub_src2_u32">;
555def DS_RSUB_SRC2_U32  : DS_1A<"ds_rsub_src2_u32">;
556def DS_INC_SRC2_U32   : DS_1A<"ds_inc_src2_u32">;
557def DS_DEC_SRC2_U32   : DS_1A<"ds_dec_src2_u32">;
558def DS_MIN_SRC2_I32   : DS_1A<"ds_min_src2_i32">;
559def DS_MAX_SRC2_I32   : DS_1A<"ds_max_src2_i32">;
560def DS_MIN_SRC2_U32   : DS_1A<"ds_min_src2_u32">;
561def DS_MAX_SRC2_U32   : DS_1A<"ds_max_src2_u32">;
562def DS_AND_SRC2_B32   : DS_1A<"ds_and_src2_b32">;
563def DS_OR_SRC2_B32    : DS_1A<"ds_or_src2_b32">;
564def DS_XOR_SRC2_B32   : DS_1A<"ds_xor_src2_b32">;
565def DS_MIN_SRC2_F32   : DS_1A<"ds_min_src2_f32">;
566def DS_MAX_SRC2_F32   : DS_1A<"ds_max_src2_f32">;
567
568def DS_ADD_SRC2_U64   : DS_1A<"ds_add_src2_u64">;
569def DS_SUB_SRC2_U64   : DS_1A<"ds_sub_src2_u64">;
570def DS_RSUB_SRC2_U64  : DS_1A<"ds_rsub_src2_u64">;
571def DS_INC_SRC2_U64   : DS_1A<"ds_inc_src2_u64">;
572def DS_DEC_SRC2_U64   : DS_1A<"ds_dec_src2_u64">;
573def DS_MIN_SRC2_I64   : DS_1A<"ds_min_src2_i64">;
574def DS_MAX_SRC2_I64   : DS_1A<"ds_max_src2_i64">;
575def DS_MIN_SRC2_U64   : DS_1A<"ds_min_src2_u64">;
576def DS_MAX_SRC2_U64   : DS_1A<"ds_max_src2_u64">;
577def DS_AND_SRC2_B64   : DS_1A<"ds_and_src2_b64">;
578def DS_OR_SRC2_B64    : DS_1A<"ds_or_src2_b64">;
579def DS_XOR_SRC2_B64   : DS_1A<"ds_xor_src2_b64">;
580def DS_MIN_SRC2_F64   : DS_1A<"ds_min_src2_f64">;
581def DS_MAX_SRC2_F64   : DS_1A<"ds_max_src2_f64">;
582
583def DS_WRITE_SRC2_B32 : DS_1A<"ds_write_src2_b32">;
584def DS_WRITE_SRC2_B64 : DS_1A<"ds_write_src2_b64">;
585} // End SubtargetPredicate = HasDsSrc2Insts
586
587let Uses = [EXEC], mayLoad = 0, mayStore = 0, isConvergent = 1 in {
588def DS_SWIZZLE_B32 : DS_1A_RET <"ds_swizzle_b32", VGPR_32, 0, SwizzleImm>;
589}
590
591let mayStore = 0 in {
592defm DS_READ_I8      : DS_1A_RET_mc<"ds_read_i8">;
593defm DS_READ_U8      : DS_1A_RET_mc<"ds_read_u8">;
594defm DS_READ_I16     : DS_1A_RET_mc<"ds_read_i16">;
595defm DS_READ_U16     : DS_1A_RET_mc<"ds_read_u16">;
596defm DS_READ_B32     : DS_1A_RET_mc<"ds_read_b32">;
597defm DS_READ_B64     : DS_1A_RET_mc<"ds_read_b64", VReg_64>;
598
599defm DS_READ2_B32    : DS_1A_Off8_RET_mc<"ds_read2_b32", VReg_64>;
600defm DS_READ2ST64_B32: DS_1A_Off8_RET_mc<"ds_read2st64_b32", VReg_64>;
601
602defm DS_READ2_B64    : DS_1A_Off8_RET_mc<"ds_read2_b64", VReg_128>;
603defm DS_READ2ST64_B64: DS_1A_Off8_RET_mc<"ds_read2st64_b64", VReg_128>;
604
605let has_m0_read = 0 in {
606let SubtargetPredicate = HasD16LoadStore in {
607def DS_READ_U8_D16     : DS_1A_RET_Tied<"ds_read_u8_d16">;
608def DS_READ_U8_D16_HI  : DS_1A_RET_Tied<"ds_read_u8_d16_hi">;
609def DS_READ_I8_D16     : DS_1A_RET_Tied<"ds_read_i8_d16">;
610def DS_READ_I8_D16_HI  : DS_1A_RET_Tied<"ds_read_i8_d16_hi">;
611def DS_READ_U16_D16    : DS_1A_RET_Tied<"ds_read_u16_d16">;
612def DS_READ_U16_D16_HI : DS_1A_RET_Tied<"ds_read_u16_d16_hi">;
613}
614} // End has_m0_read = 0
615
616let SubtargetPredicate = HasDSAddTid in {
617def DS_READ_ADDTID_B32 : DS_0A_RET<"ds_read_addtid_b32">;
618}
619
620} // End mayStore = 0
621
622def DS_CONSUME       : DS_0A_RET<"ds_consume">;
623def DS_APPEND        : DS_0A_RET<"ds_append">;
624def DS_ORDERED_COUNT : DS_1A_RET_GDS<"ds_ordered_count">;
625
626//===----------------------------------------------------------------------===//
627// Instruction definitions for CI and newer.
628//===----------------------------------------------------------------------===//
629
630let SubtargetPredicate = isGFX7Plus in {
631
632defm DS_WRAP_RTN_B32 : DS_1A2D_RET_mc<"ds_wrap_rtn_b32", VGPR_32>;
633defm DS_CONDXCHG32_RTN_B64 : DS_1A1D_RET_mc<"ds_condxchg32_rtn_b64", VReg_64>;
634
635let isConvergent = 1, usesCustomInserter = 1 in {
636def DS_GWS_SEMA_RELEASE_ALL : DS_GWS_0D<"ds_gws_sema_release_all">;
637}
638
639let mayStore = 0 in {
640defm DS_READ_B96 : DS_1A_RET_mc<"ds_read_b96", VReg_96>;
641defm DS_READ_B128: DS_1A_RET_mc<"ds_read_b128", VReg_128>;
642} // End mayStore = 0
643
644let mayLoad = 0 in {
645defm DS_WRITE_B96 : DS_1A1D_NORET_mc<"ds_write_b96", VReg_96>;
646defm DS_WRITE_B128 : DS_1A1D_NORET_mc<"ds_write_b128", VReg_128>;
647} // End mayLoad = 0
648
649def DS_NOP : DS_VOID<"ds_nop">;
650
651} // let SubtargetPredicate = isGFX7Plus
652
653//===----------------------------------------------------------------------===//
654// Instruction definitions for VI and newer.
655//===----------------------------------------------------------------------===//
656
657let SubtargetPredicate = isGFX8Plus in {
658
659let Uses = [EXEC] in {
660def DS_PERMUTE_B32  : DS_1A1D_PERMUTE <"ds_permute_b32",
661                                       int_amdgcn_ds_permute>;
662def DS_BPERMUTE_B32 : DS_1A1D_PERMUTE <"ds_bpermute_b32",
663                                       int_amdgcn_ds_bpermute>;
664}
665
666} // let SubtargetPredicate = isGFX8Plus
667
668let SubtargetPredicate = HasLDSFPAtomics, OtherPredicates = [HasDsSrc2Insts] in {
669def DS_ADD_SRC2_F32 : DS_1A<"ds_add_src2_f32">;
670}
671
672//===----------------------------------------------------------------------===//
673// DS Patterns
674//===----------------------------------------------------------------------===//
675
676def : GCNPat <
677  (int_amdgcn_ds_swizzle i32:$src, timm:$offset16),
678  (DS_SWIZZLE_B32 VGPR_32:$src, (as_i16timm $offset16), (i1 0))
679>;
680
681class DSReadPat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
682  (vt (frag (DS1Addr1Offset i32:$ptr, i16:$offset))),
683  (inst $ptr, offset:$offset, (i1 gds))
684>;
685
686multiclass DSReadPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
687
688  let OtherPredicates = [LDSRequiresM0Init] in {
689    def : DSReadPat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
690  }
691
692  let OtherPredicates = [NotLDSRequiresM0Init] in {
693    def : DSReadPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
694  }
695}
696
697class DSReadPat_D16 <DS_Pseudo inst, PatFrag frag, ValueType vt> : GCNPat <
698  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$in),
699  (inst $ptr, offset:$offset, (i1 0), $in)
700>;
701
702defm : DSReadPat_mc <DS_READ_I8, i32, "sextloadi8_local">;
703defm : DSReadPat_mc <DS_READ_I8,  i16, "sextloadi8_local">;
704defm : DSReadPat_mc <DS_READ_U8,  i32, "extloadi8_local">;
705defm : DSReadPat_mc <DS_READ_U8,  i32, "zextloadi8_local">;
706defm : DSReadPat_mc <DS_READ_U8,  i16, "extloadi8_local">;
707defm : DSReadPat_mc <DS_READ_U8,  i16, "zextloadi8_local">;
708defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
709defm : DSReadPat_mc <DS_READ_I16, i32, "sextloadi16_local">;
710defm : DSReadPat_mc <DS_READ_U16, i32, "extloadi16_local">;
711defm : DSReadPat_mc <DS_READ_U16, i32, "zextloadi16_local">;
712defm : DSReadPat_mc <DS_READ_U16, i16, "load_local">;
713
714foreach vt = Reg32Types.types in {
715defm : DSReadPat_mc <DS_READ_B32, vt, "load_local">;
716}
717
718defm : DSReadPat_mc <DS_READ_B32, i32, "atomic_load_32_local">;
719defm : DSReadPat_mc <DS_READ_B64, i64, "atomic_load_64_local">;
720
721let OtherPredicates = [D16PreservesUnusedBits] in {
722def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2i16>;
723def : DSReadPat_D16<DS_READ_U16_D16_HI, load_d16_hi_local, v2f16>;
724def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2i16>;
725def : DSReadPat_D16<DS_READ_U8_D16_HI, az_extloadi8_d16_hi_local, v2f16>;
726def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2i16>;
727def : DSReadPat_D16<DS_READ_I8_D16_HI, sextloadi8_d16_hi_local, v2f16>;
728
729def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2i16>;
730def : DSReadPat_D16<DS_READ_U16_D16, load_d16_lo_local, v2f16>;
731def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2i16>;
732def : DSReadPat_D16<DS_READ_U8_D16, az_extloadi8_d16_lo_local, v2f16>;
733def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2i16>;
734def : DSReadPat_D16<DS_READ_I8_D16, sextloadi8_d16_lo_local, v2f16>;
735}
736
737class DSWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag, int gds=0> : GCNPat <
738  (frag vt:$value, (DS1Addr1Offset i32:$ptr, i16:$offset)),
739  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
740>;
741
742multiclass DSWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
743  let OtherPredicates = [LDSRequiresM0Init] in {
744    def : DSWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
745  }
746
747  let OtherPredicates = [NotLDSRequiresM0Init] in {
748    def : DSWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
749  }
750}
751
752// Irritatingly, atomic_store reverses the order of operands from a
753// normal store.
754class DSAtomicWritePat <DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
755  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
756  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 0))
757>;
758
759multiclass DSAtomicWritePat_mc <DS_Pseudo inst, ValueType vt, string frag> {
760  let OtherPredicates = [LDSRequiresM0Init] in {
761    def : DSAtomicWritePat<inst, vt, !cast<PatFrag>(frag#"_m0")>;
762  }
763
764  let OtherPredicates = [NotLDSRequiresM0Init] in {
765    def : DSAtomicWritePat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt, !cast<PatFrag>(frag)>;
766  }
767}
768
769defm : DSWritePat_mc <DS_WRITE_B8, i32, "truncstorei8_local">;
770defm : DSWritePat_mc <DS_WRITE_B16, i32, "truncstorei16_local">;
771defm : DSWritePat_mc <DS_WRITE_B8, i16, "truncstorei8_local">;
772defm : DSWritePat_mc <DS_WRITE_B16, i16, "store_local">;
773
774foreach vt = Reg32Types.types in {
775defm : DSWritePat_mc <DS_WRITE_B32, vt, "store_local">;
776}
777
778defm : DSAtomicWritePat_mc <DS_WRITE_B32, i32, "atomic_store_local_32">;
779defm : DSAtomicWritePat_mc <DS_WRITE_B64, i64, "atomic_store_local_64">;
780
781let OtherPredicates = [D16PreservesUnusedBits] in {
782def : DSWritePat <DS_WRITE_B16_D16_HI, i32, store_hi16_local>;
783def : DSWritePat <DS_WRITE_B8_D16_HI, i32, truncstorei8_hi16_local>;
784}
785
786class DS64Bit4ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
787  (vt:$value (frag (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
788  (inst $ptr, $offset0, $offset1, (i1 0))
789>;
790
791class DS64Bit4ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
792  (frag vt:$value, (DS64Bit4ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
793  (inst $ptr, (i32 (EXTRACT_SUBREG VReg_64:$value, sub0)),
794              (i32 (EXTRACT_SUBREG VReg_64:$value, sub1)), $offset0, $offset1,
795              (i1 0))
796>;
797
798class DS128Bit8ByteAlignedReadPat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat <
799  (vt:$value (frag (DS128Bit8ByteAligned i32:$ptr, i8:$offset0, i8:$offset1))),
800  (inst $ptr, $offset0, $offset1, (i1 0))
801>;
802
803class DS128Bit8ByteAlignedWritePat<DS_Pseudo inst, ValueType vt, PatFrag frag> : GCNPat<
804  (frag vt:$value, (DS128Bit8ByteAligned i32:$ptr, i8:$offset0, i8:$offset1)),
805  (inst $ptr, (i64 (EXTRACT_SUBREG VReg_128:$value, sub0_sub1)),
806              (i64 (EXTRACT_SUBREG VReg_128:$value, sub2_sub3)), $offset0, $offset1,
807              (i1 0))
808>;
809
810multiclass DS64Bit4ByteAlignedPat_mc<ValueType vt> {
811  let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
812    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32, vt, load_local_m0>;
813    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32, vt, store_local_m0>;
814  }
815
816  let OtherPredicates = [NotLDSRequiresM0Init] in {
817    def : DS64Bit4ByteAlignedReadPat<DS_READ2_B32_gfx9, vt, load_local>;
818    def : DS64Bit4ByteAlignedWritePat<DS_WRITE2_B32_gfx9, vt, store_local>;
819  }
820}
821
822multiclass DS128Bit8ByteAlignedPat_mc<ValueType vt> {
823  let OtherPredicates = [LDSRequiresM0Init, isGFX7Plus] in {
824    def : DS128Bit8ByteAlignedReadPat<DS_READ2_B64, vt, load_local_m0>;
825    def : DS128Bit8ByteAlignedWritePat<DS_WRITE2_B64, vt, store_local_m0>;
826  }
827
828  let OtherPredicates = [NotLDSRequiresM0Init] in {
829    def : DS128Bit8ByteAlignedReadPat<DS_READ2_B64_gfx9, vt, load_local>;
830    def : DS128Bit8ByteAlignedWritePat<DS_WRITE2_B64_gfx9, vt, store_local>;
831  }
832}
833
834// v2i32 loads are split into i32 loads on SI during lowering, due to a bug
835// related to bounds checking.
836foreach vt = VReg_64.RegTypes in {
837defm : DS64Bit4ByteAlignedPat_mc<vt>;
838}
839
840foreach vt = VReg_128.RegTypes in {
841defm : DS128Bit8ByteAlignedPat_mc<vt>;
842}
843
844// Prefer ds_read over ds_read2 and ds_write over ds_write2, all other things
845// being equal, because it has a larger immediate offset range.
846let AddedComplexity = 100 in {
847
848foreach vt = VReg_64.RegTypes in {
849defm : DSReadPat_mc <DS_READ_B64, vt, "load_align8_local">;
850defm : DSWritePat_mc <DS_WRITE_B64, vt, "store_align8_local">;
851}
852
853let SubtargetPredicate = isGFX7Plus in {
854
855foreach vt = VReg_96.RegTypes in {
856defm : DSReadPat_mc <DS_READ_B96, vt, "load_align16_local">;
857defm : DSWritePat_mc <DS_WRITE_B96, vt, "store_align16_local">;
858}
859
860foreach vt = VReg_128.RegTypes in {
861defm : DSReadPat_mc <DS_READ_B128, vt, "load_align16_local">;
862defm : DSWritePat_mc <DS_WRITE_B128, vt, "store_align16_local">;
863}
864
865let SubtargetPredicate = HasUnalignedAccessMode in {
866
867// FIXME: From performance point of view, is ds_read_b96/ds_write_b96 better choice
868// for unaligned accesses?
869foreach vt = VReg_96.RegTypes in {
870defm : DSReadPat_mc <DS_READ_B96, vt, "load_local">;
871defm : DSWritePat_mc <DS_WRITE_B96, vt, "store_local">;
872}
873
874// For performance reasons, *do not* select ds_read_b128/ds_write_b128 for unaligned
875// accesses.
876
877} // End SubtargetPredicate = HasUnalignedAccessMode
878
879} // End SubtargetPredicate = isGFX7Plus
880
881} // End AddedComplexity = 100
882
883class DSAtomicRetPat<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
884  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$value),
885  (inst $ptr, getVregSrcForVT<vt>.ret:$value, offset:$offset, (i1 gds))
886>;
887
888multiclass DSAtomicRetPat_mc<DS_Pseudo inst, ValueType vt, string frag> {
889  let OtherPredicates = [LDSRequiresM0Init] in {
890    def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
891  }
892
893  let OtherPredicates = [NotLDSRequiresM0Init] in {
894    def : DSAtomicRetPat<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
895                         !cast<PatFrag>(frag#"_local_"#vt.Size)>;
896  }
897
898  def : DSAtomicRetPat<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
899}
900
901
902
903class DSAtomicCmpXChg<DS_Pseudo inst, ValueType vt, PatFrag frag, bit gds=0> : GCNPat <
904  (frag (DS1Addr1Offset i32:$ptr, i16:$offset), vt:$cmp, vt:$swap),
905  (inst $ptr, getVregSrcForVT<vt>.ret:$cmp, getVregSrcForVT<vt>.ret:$swap, offset:$offset, (i1 gds))
906>;
907
908multiclass DSAtomicCmpXChg_mc<DS_Pseudo inst, ValueType vt, string frag> {
909  let OtherPredicates = [LDSRequiresM0Init] in {
910    def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_local_m0_"#vt.Size)>;
911  }
912
913  let OtherPredicates = [NotLDSRequiresM0Init] in {
914    def : DSAtomicCmpXChg<!cast<DS_Pseudo>(!cast<string>(inst)#"_gfx9"), vt,
915                          !cast<PatFrag>(frag#"_local_"#vt.Size)>;
916  }
917
918  def : DSAtomicCmpXChg<inst, vt, !cast<PatFrag>(frag#"_region_m0_"#vt.Size), 1>;
919}
920
921
922
923// 32-bit atomics.
924defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B32, i32, "atomic_swap">;
925defm : DSAtomicRetPat_mc<DS_ADD_RTN_U32, i32, "atomic_load_add">;
926defm : DSAtomicRetPat_mc<DS_SUB_RTN_U32, i32, "atomic_load_sub">;
927defm : DSAtomicRetPat_mc<DS_INC_RTN_U32, i32, "atomic_inc">;
928defm : DSAtomicRetPat_mc<DS_DEC_RTN_U32, i32, "atomic_dec">;
929defm : DSAtomicRetPat_mc<DS_AND_RTN_B32, i32, "atomic_load_and">;
930defm : DSAtomicRetPat_mc<DS_OR_RTN_B32, i32, "atomic_load_or">;
931defm : DSAtomicRetPat_mc<DS_XOR_RTN_B32, i32, "atomic_load_xor">;
932defm : DSAtomicRetPat_mc<DS_MIN_RTN_I32, i32, "atomic_load_min">;
933defm : DSAtomicRetPat_mc<DS_MAX_RTN_I32, i32, "atomic_load_max">;
934defm : DSAtomicRetPat_mc<DS_MIN_RTN_U32, i32, "atomic_load_umin">;
935defm : DSAtomicRetPat_mc<DS_MAX_RTN_U32, i32, "atomic_load_umax">;
936defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B32, i32, "atomic_cmp_swap">;
937
938let SubtargetPredicate = HasLDSFPAtomics in {
939defm : DSAtomicRetPat_mc<DS_MIN_RTN_F32, f32, "atomic_load_fmin">;
940defm : DSAtomicRetPat_mc<DS_MAX_RTN_F32, f32, "atomic_load_fmax">;
941defm : DSAtomicRetPat_mc<DS_ADD_RTN_F32, f32, "atomic_load_fadd">;
942}
943
944// 64-bit atomics.
945defm : DSAtomicRetPat_mc<DS_WRXCHG_RTN_B64, i64, "atomic_swap">;
946defm : DSAtomicRetPat_mc<DS_ADD_RTN_U64, i64, "atomic_load_add">;
947defm : DSAtomicRetPat_mc<DS_SUB_RTN_U64, i64, "atomic_load_sub">;
948defm : DSAtomicRetPat_mc<DS_INC_RTN_U64, i64, "atomic_inc">;
949defm : DSAtomicRetPat_mc<DS_DEC_RTN_U64, i64, "atomic_dec">;
950defm : DSAtomicRetPat_mc<DS_AND_RTN_B64, i64, "atomic_load_and">;
951defm : DSAtomicRetPat_mc<DS_OR_RTN_B64, i64, "atomic_load_or">;
952defm : DSAtomicRetPat_mc<DS_XOR_RTN_B64, i64, "atomic_load_xor">;
953defm : DSAtomicRetPat_mc<DS_MIN_RTN_I64, i64, "atomic_load_min">;
954defm : DSAtomicRetPat_mc<DS_MAX_RTN_I64, i64, "atomic_load_max">;
955defm : DSAtomicRetPat_mc<DS_MIN_RTN_U64, i64, "atomic_load_umin">;
956defm : DSAtomicRetPat_mc<DS_MAX_RTN_U64, i64, "atomic_load_umax">;
957
958defm : DSAtomicCmpXChg_mc<DS_CMPST_RTN_B64, i64, "atomic_cmp_swap">;
959
960let SubtargetPredicate = isGFX90APlus in {
961def : DSAtomicRetPat<DS_ADD_RTN_F64, f64, atomic_load_fadd_local_64>;
962}
963
964def : Pat <
965  (SIds_ordered_count i32:$value, i16:$offset),
966  (DS_ORDERED_COUNT $value, (as_i16imm $offset))
967>;
968
969//===----------------------------------------------------------------------===//
970// Target-specific instruction encodings.
971//===----------------------------------------------------------------------===//
972
973//===----------------------------------------------------------------------===//
974// Base ENC_DS for GFX6, GFX7, GFX10.
975//===----------------------------------------------------------------------===//
976
977class Base_DS_Real_gfx6_gfx7_gfx10<bits<8> op, DS_Pseudo ps, int ef> :
978    DS_Real<ps>, SIMCInstr <ps.Mnemonic, ef> {
979
980  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
981  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
982  let Inst{17}    = !if(ps.has_gds, gds, ps.gdsValue);
983  let Inst{25-18} = op;
984  let Inst{31-26} = 0x36;
985  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0{7-0}, 0));
986  let Inst{47-40} = !if(ps.has_data0, data0{7-0}, 0);
987  let Inst{55-48} = !if(ps.has_data1, data1{7-0}, 0);
988  let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, 0);
989}
990
991//===----------------------------------------------------------------------===//
992// GFX10.
993//===----------------------------------------------------------------------===//
994
995let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
996  multiclass DS_Real_gfx10<bits<8> op>  {
997    def _gfx10 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
998                                              SIEncodingFamily.GFX10>;
999  }
1000} // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
1001
1002defm DS_ADD_F32          : DS_Real_gfx10<0x015>;
1003defm DS_ADD_RTN_F32      : DS_Real_gfx10<0x055>;
1004defm DS_ADD_SRC2_F32     : DS_Real_gfx10<0x095>;
1005defm DS_WRITE_B8_D16_HI  : DS_Real_gfx10<0x0a0>;
1006defm DS_WRITE_B16_D16_HI : DS_Real_gfx10<0x0a1>;
1007defm DS_READ_U8_D16      : DS_Real_gfx10<0x0a2>;
1008defm DS_READ_U8_D16_HI   : DS_Real_gfx10<0x0a3>;
1009defm DS_READ_I8_D16      : DS_Real_gfx10<0x0a4>;
1010defm DS_READ_I8_D16_HI   : DS_Real_gfx10<0x0a5>;
1011defm DS_READ_U16_D16     : DS_Real_gfx10<0x0a6>;
1012defm DS_READ_U16_D16_HI  : DS_Real_gfx10<0x0a7>;
1013defm DS_WRITE_ADDTID_B32 : DS_Real_gfx10<0x0b0>;
1014defm DS_READ_ADDTID_B32  : DS_Real_gfx10<0x0b1>;
1015defm DS_PERMUTE_B32      : DS_Real_gfx10<0x0b2>;
1016defm DS_BPERMUTE_B32     : DS_Real_gfx10<0x0b3>;
1017
1018//===----------------------------------------------------------------------===//
1019// GFX7, GFX10.
1020//===----------------------------------------------------------------------===//
1021
1022let AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7" in {
1023  multiclass DS_Real_gfx7<bits<8> op> {
1024    def _gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
1025                                             SIEncodingFamily.SI>;
1026  }
1027} // End AssemblerPredicate = isGFX7Only, DecoderNamespace = "GFX7"
1028
1029multiclass DS_Real_gfx7_gfx10<bits<8> op> :
1030  DS_Real_gfx7<op>, DS_Real_gfx10<op>;
1031
1032// FIXME-GFX7: Add tests when upstreaming this part.
1033defm DS_GWS_SEMA_RELEASE_ALL : DS_Real_gfx7_gfx10<0x018>;
1034defm DS_WRAP_RTN_B32         : DS_Real_gfx7_gfx10<0x034>;
1035defm DS_CONDXCHG32_RTN_B64   : DS_Real_gfx7_gfx10<0x07e>;
1036defm DS_WRITE_B96            : DS_Real_gfx7_gfx10<0x0de>;
1037defm DS_WRITE_B128           : DS_Real_gfx7_gfx10<0x0df>;
1038defm DS_READ_B96             : DS_Real_gfx7_gfx10<0x0fe>;
1039defm DS_READ_B128            : DS_Real_gfx7_gfx10<0x0ff>;
1040
1041//===----------------------------------------------------------------------===//
1042// GFX6, GFX7, GFX10.
1043//===----------------------------------------------------------------------===//
1044
1045let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
1046  multiclass DS_Real_gfx6_gfx7<bits<8> op> {
1047    def _gfx6_gfx7 : Base_DS_Real_gfx6_gfx7_gfx10<op, !cast<DS_Pseudo>(NAME),
1048                                                  SIEncodingFamily.SI>;
1049  }
1050} // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
1051
1052multiclass DS_Real_gfx6_gfx7_gfx10<bits<8> op> :
1053  DS_Real_gfx6_gfx7<op>, DS_Real_gfx10<op>;
1054
1055defm DS_ADD_U32             : DS_Real_gfx6_gfx7_gfx10<0x000>;
1056defm DS_SUB_U32             : DS_Real_gfx6_gfx7_gfx10<0x001>;
1057defm DS_RSUB_U32            : DS_Real_gfx6_gfx7_gfx10<0x002>;
1058defm DS_INC_U32             : DS_Real_gfx6_gfx7_gfx10<0x003>;
1059defm DS_DEC_U32             : DS_Real_gfx6_gfx7_gfx10<0x004>;
1060defm DS_MIN_I32             : DS_Real_gfx6_gfx7_gfx10<0x005>;
1061defm DS_MAX_I32             : DS_Real_gfx6_gfx7_gfx10<0x006>;
1062defm DS_MIN_U32             : DS_Real_gfx6_gfx7_gfx10<0x007>;
1063defm DS_MAX_U32             : DS_Real_gfx6_gfx7_gfx10<0x008>;
1064defm DS_AND_B32             : DS_Real_gfx6_gfx7_gfx10<0x009>;
1065defm DS_OR_B32              : DS_Real_gfx6_gfx7_gfx10<0x00a>;
1066defm DS_XOR_B32             : DS_Real_gfx6_gfx7_gfx10<0x00b>;
1067defm DS_MSKOR_B32           : DS_Real_gfx6_gfx7_gfx10<0x00c>;
1068defm DS_WRITE_B32           : DS_Real_gfx6_gfx7_gfx10<0x00d>;
1069defm DS_WRITE2_B32          : DS_Real_gfx6_gfx7_gfx10<0x00e>;
1070defm DS_WRITE2ST64_B32      : DS_Real_gfx6_gfx7_gfx10<0x00f>;
1071defm DS_CMPST_B32           : DS_Real_gfx6_gfx7_gfx10<0x010>;
1072defm DS_CMPST_F32           : DS_Real_gfx6_gfx7_gfx10<0x011>;
1073defm DS_MIN_F32             : DS_Real_gfx6_gfx7_gfx10<0x012>;
1074defm DS_MAX_F32             : DS_Real_gfx6_gfx7_gfx10<0x013>;
1075defm DS_NOP                 : DS_Real_gfx6_gfx7_gfx10<0x014>;
1076defm DS_GWS_INIT            : DS_Real_gfx6_gfx7_gfx10<0x019>;
1077defm DS_GWS_SEMA_V          : DS_Real_gfx6_gfx7_gfx10<0x01a>;
1078defm DS_GWS_SEMA_BR         : DS_Real_gfx6_gfx7_gfx10<0x01b>;
1079defm DS_GWS_SEMA_P          : DS_Real_gfx6_gfx7_gfx10<0x01c>;
1080defm DS_GWS_BARRIER         : DS_Real_gfx6_gfx7_gfx10<0x01d>;
1081defm DS_WRITE_B8            : DS_Real_gfx6_gfx7_gfx10<0x01e>;
1082defm DS_WRITE_B16           : DS_Real_gfx6_gfx7_gfx10<0x01f>;
1083defm DS_ADD_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x020>;
1084defm DS_SUB_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x021>;
1085defm DS_RSUB_RTN_U32        : DS_Real_gfx6_gfx7_gfx10<0x022>;
1086defm DS_INC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x023>;
1087defm DS_DEC_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x024>;
1088defm DS_MIN_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x025>;
1089defm DS_MAX_RTN_I32         : DS_Real_gfx6_gfx7_gfx10<0x026>;
1090defm DS_MIN_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x027>;
1091defm DS_MAX_RTN_U32         : DS_Real_gfx6_gfx7_gfx10<0x028>;
1092defm DS_AND_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x029>;
1093defm DS_OR_RTN_B32          : DS_Real_gfx6_gfx7_gfx10<0x02a>;
1094defm DS_XOR_RTN_B32         : DS_Real_gfx6_gfx7_gfx10<0x02b>;
1095defm DS_MSKOR_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x02c>;
1096defm DS_WRXCHG_RTN_B32      : DS_Real_gfx6_gfx7_gfx10<0x02d>;
1097defm DS_WRXCHG2_RTN_B32     : DS_Real_gfx6_gfx7_gfx10<0x02e>;
1098defm DS_WRXCHG2ST64_RTN_B32 : DS_Real_gfx6_gfx7_gfx10<0x02f>;
1099defm DS_CMPST_RTN_B32       : DS_Real_gfx6_gfx7_gfx10<0x030>;
1100defm DS_CMPST_RTN_F32       : DS_Real_gfx6_gfx7_gfx10<0x031>;
1101defm DS_MIN_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x032>;
1102defm DS_MAX_RTN_F32         : DS_Real_gfx6_gfx7_gfx10<0x033>;
1103defm DS_SWIZZLE_B32         : DS_Real_gfx6_gfx7_gfx10<0x035>;
1104defm DS_READ_B32            : DS_Real_gfx6_gfx7_gfx10<0x036>;
1105defm DS_READ2_B32           : DS_Real_gfx6_gfx7_gfx10<0x037>;
1106defm DS_READ2ST64_B32       : DS_Real_gfx6_gfx7_gfx10<0x038>;
1107defm DS_READ_I8             : DS_Real_gfx6_gfx7_gfx10<0x039>;
1108defm DS_READ_U8             : DS_Real_gfx6_gfx7_gfx10<0x03a>;
1109defm DS_READ_I16            : DS_Real_gfx6_gfx7_gfx10<0x03b>;
1110defm DS_READ_U16            : DS_Real_gfx6_gfx7_gfx10<0x03c>;
1111defm DS_CONSUME             : DS_Real_gfx6_gfx7_gfx10<0x03d>;
1112defm DS_APPEND              : DS_Real_gfx6_gfx7_gfx10<0x03e>;
1113defm DS_ORDERED_COUNT       : DS_Real_gfx6_gfx7_gfx10<0x03f>;
1114defm DS_ADD_U64             : DS_Real_gfx6_gfx7_gfx10<0x040>;
1115defm DS_SUB_U64             : DS_Real_gfx6_gfx7_gfx10<0x041>;
1116defm DS_RSUB_U64            : DS_Real_gfx6_gfx7_gfx10<0x042>;
1117defm DS_INC_U64             : DS_Real_gfx6_gfx7_gfx10<0x043>;
1118defm DS_DEC_U64             : DS_Real_gfx6_gfx7_gfx10<0x044>;
1119defm DS_MIN_I64             : DS_Real_gfx6_gfx7_gfx10<0x045>;
1120defm DS_MAX_I64             : DS_Real_gfx6_gfx7_gfx10<0x046>;
1121defm DS_MIN_U64             : DS_Real_gfx6_gfx7_gfx10<0x047>;
1122defm DS_MAX_U64             : DS_Real_gfx6_gfx7_gfx10<0x048>;
1123defm DS_AND_B64             : DS_Real_gfx6_gfx7_gfx10<0x049>;
1124defm DS_OR_B64              : DS_Real_gfx6_gfx7_gfx10<0x04a>;
1125defm DS_XOR_B64             : DS_Real_gfx6_gfx7_gfx10<0x04b>;
1126defm DS_MSKOR_B64           : DS_Real_gfx6_gfx7_gfx10<0x04c>;
1127defm DS_WRITE_B64           : DS_Real_gfx6_gfx7_gfx10<0x04d>;
1128defm DS_WRITE2_B64          : DS_Real_gfx6_gfx7_gfx10<0x04e>;
1129defm DS_WRITE2ST64_B64      : DS_Real_gfx6_gfx7_gfx10<0x04f>;
1130defm DS_CMPST_B64           : DS_Real_gfx6_gfx7_gfx10<0x050>;
1131defm DS_CMPST_F64           : DS_Real_gfx6_gfx7_gfx10<0x051>;
1132defm DS_MIN_F64             : DS_Real_gfx6_gfx7_gfx10<0x052>;
1133defm DS_MAX_F64             : DS_Real_gfx6_gfx7_gfx10<0x053>;
1134defm DS_ADD_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x060>;
1135defm DS_SUB_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x061>;
1136defm DS_RSUB_RTN_U64        : DS_Real_gfx6_gfx7_gfx10<0x062>;
1137defm DS_INC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x063>;
1138defm DS_DEC_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x064>;
1139defm DS_MIN_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x065>;
1140defm DS_MAX_RTN_I64         : DS_Real_gfx6_gfx7_gfx10<0x066>;
1141defm DS_MIN_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x067>;
1142defm DS_MAX_RTN_U64         : DS_Real_gfx6_gfx7_gfx10<0x068>;
1143defm DS_AND_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x069>;
1144defm DS_OR_RTN_B64          : DS_Real_gfx6_gfx7_gfx10<0x06a>;
1145defm DS_XOR_RTN_B64         : DS_Real_gfx6_gfx7_gfx10<0x06b>;
1146defm DS_MSKOR_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x06c>;
1147defm DS_WRXCHG_RTN_B64      : DS_Real_gfx6_gfx7_gfx10<0x06d>;
1148defm DS_WRXCHG2_RTN_B64     : DS_Real_gfx6_gfx7_gfx10<0x06e>;
1149defm DS_WRXCHG2ST64_RTN_B64 : DS_Real_gfx6_gfx7_gfx10<0x06f>;
1150defm DS_CMPST_RTN_B64       : DS_Real_gfx6_gfx7_gfx10<0x070>;
1151defm DS_CMPST_RTN_F64       : DS_Real_gfx6_gfx7_gfx10<0x071>;
1152defm DS_MIN_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x072>;
1153defm DS_MAX_RTN_F64         : DS_Real_gfx6_gfx7_gfx10<0x073>;
1154defm DS_READ_B64            : DS_Real_gfx6_gfx7_gfx10<0x076>;
1155defm DS_READ2_B64           : DS_Real_gfx6_gfx7_gfx10<0x077>;
1156defm DS_READ2ST64_B64       : DS_Real_gfx6_gfx7_gfx10<0x078>;
1157defm DS_ADD_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x080>;
1158defm DS_SUB_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x081>;
1159defm DS_RSUB_SRC2_U32       : DS_Real_gfx6_gfx7_gfx10<0x082>;
1160defm DS_INC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x083>;
1161defm DS_DEC_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x084>;
1162defm DS_MIN_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x085>;
1163defm DS_MAX_SRC2_I32        : DS_Real_gfx6_gfx7_gfx10<0x086>;
1164defm DS_MIN_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x087>;
1165defm DS_MAX_SRC2_U32        : DS_Real_gfx6_gfx7_gfx10<0x088>;
1166defm DS_AND_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x089>;
1167defm DS_OR_SRC2_B32         : DS_Real_gfx6_gfx7_gfx10<0x08a>;
1168defm DS_XOR_SRC2_B32        : DS_Real_gfx6_gfx7_gfx10<0x08b>;
1169defm DS_WRITE_SRC2_B32      : DS_Real_gfx6_gfx7_gfx10<0x08d>;
1170defm DS_MIN_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x092>;
1171defm DS_MAX_SRC2_F32        : DS_Real_gfx6_gfx7_gfx10<0x093>;
1172defm DS_ADD_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c0>;
1173defm DS_SUB_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c1>;
1174defm DS_RSUB_SRC2_U64       : DS_Real_gfx6_gfx7_gfx10<0x0c2>;
1175defm DS_INC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c3>;
1176defm DS_DEC_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c4>;
1177defm DS_MIN_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c5>;
1178defm DS_MAX_SRC2_I64        : DS_Real_gfx6_gfx7_gfx10<0x0c6>;
1179defm DS_MIN_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c7>;
1180defm DS_MAX_SRC2_U64        : DS_Real_gfx6_gfx7_gfx10<0x0c8>;
1181defm DS_AND_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0c9>;
1182defm DS_OR_SRC2_B64         : DS_Real_gfx6_gfx7_gfx10<0x0ca>;
1183defm DS_XOR_SRC2_B64        : DS_Real_gfx6_gfx7_gfx10<0x0cb>;
1184defm DS_WRITE_SRC2_B64      : DS_Real_gfx6_gfx7_gfx10<0x0cd>;
1185defm DS_MIN_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d2>;
1186defm DS_MAX_SRC2_F64        : DS_Real_gfx6_gfx7_gfx10<0x0d3>;
1187
1188//===----------------------------------------------------------------------===//
1189// GFX8, GFX9 (VI).
1190//===----------------------------------------------------------------------===//
1191
1192class DS_Real_vi <bits<8> op, DS_Pseudo ps> :
1193  DS_Real <ps>,
1194  SIMCInstr <ps.Mnemonic, SIEncodingFamily.VI> {
1195  let AssemblerPredicate = isGFX8GFX9;
1196  let DecoderNamespace = "GFX8";
1197
1198  // encoding
1199  let Inst{7-0}   = !if(ps.has_offset0, offset0, 0);
1200  let Inst{15-8}  = !if(ps.has_offset1, offset1, 0);
1201  let Inst{16}    = !if(ps.has_gds, gds, ps.gdsValue);
1202  let Inst{24-17} = op;
1203  let Inst{25}    = acc;
1204  let Inst{31-26} = 0x36; // ds prefix
1205  let Inst{39-32} = !if(ps.has_addr, addr, !if(ps.has_gws_data0, data0{7-0}, 0));
1206  let Inst{47-40} = !if(ps.has_data0, data0{7-0}, 0);
1207  let Inst{55-48} = !if(ps.has_data1, data1{7-0}, 0);
1208  let Inst{63-56} = !if(ps.has_vdst, vdst{7-0}, 0);
1209}
1210
1211def DS_ADD_U32_vi         : DS_Real_vi<0x0,  DS_ADD_U32>;
1212def DS_SUB_U32_vi         : DS_Real_vi<0x1,  DS_SUB_U32>;
1213def DS_RSUB_U32_vi        : DS_Real_vi<0x2,  DS_RSUB_U32>;
1214def DS_INC_U32_vi         : DS_Real_vi<0x3,  DS_INC_U32>;
1215def DS_DEC_U32_vi         : DS_Real_vi<0x4,  DS_DEC_U32>;
1216def DS_MIN_I32_vi         : DS_Real_vi<0x5,  DS_MIN_I32>;
1217def DS_MAX_I32_vi         : DS_Real_vi<0x6,  DS_MAX_I32>;
1218def DS_MIN_U32_vi         : DS_Real_vi<0x7,  DS_MIN_U32>;
1219def DS_MAX_U32_vi         : DS_Real_vi<0x8,  DS_MAX_U32>;
1220def DS_AND_B32_vi         : DS_Real_vi<0x9,  DS_AND_B32>;
1221def DS_OR_B32_vi          : DS_Real_vi<0xa,  DS_OR_B32>;
1222def DS_XOR_B32_vi         : DS_Real_vi<0xb,  DS_XOR_B32>;
1223def DS_MSKOR_B32_vi       : DS_Real_vi<0xc,  DS_MSKOR_B32>;
1224def DS_WRITE_B32_vi       : DS_Real_vi<0xd,  DS_WRITE_B32>;
1225def DS_WRITE2_B32_vi      : DS_Real_vi<0xe,  DS_WRITE2_B32>;
1226def DS_WRITE2ST64_B32_vi  : DS_Real_vi<0xf,  DS_WRITE2ST64_B32>;
1227def DS_CMPST_B32_vi       : DS_Real_vi<0x10, DS_CMPST_B32>;
1228def DS_CMPST_F32_vi       : DS_Real_vi<0x11, DS_CMPST_F32>;
1229def DS_MIN_F32_vi         : DS_Real_vi<0x12, DS_MIN_F32>;
1230def DS_MAX_F32_vi         : DS_Real_vi<0x13, DS_MAX_F32>;
1231def DS_NOP_vi             : DS_Real_vi<0x14, DS_NOP>;
1232def DS_ADD_F32_vi         : DS_Real_vi<0x15, DS_ADD_F32>;
1233def DS_GWS_INIT_vi        : DS_Real_vi<0x99, DS_GWS_INIT>;
1234def DS_GWS_SEMA_V_vi      : DS_Real_vi<0x9a, DS_GWS_SEMA_V>;
1235def DS_GWS_SEMA_BR_vi     : DS_Real_vi<0x9b, DS_GWS_SEMA_BR>;
1236def DS_GWS_SEMA_P_vi      : DS_Real_vi<0x9c, DS_GWS_SEMA_P>;
1237def DS_GWS_BARRIER_vi     : DS_Real_vi<0x9d, DS_GWS_BARRIER>;
1238def DS_WRITE_ADDTID_B32_vi : DS_Real_vi<0x1d, DS_WRITE_ADDTID_B32>;
1239def DS_WRITE_B8_vi        : DS_Real_vi<0x1e, DS_WRITE_B8>;
1240def DS_WRITE_B16_vi       : DS_Real_vi<0x1f, DS_WRITE_B16>;
1241def DS_ADD_RTN_U32_vi     : DS_Real_vi<0x20, DS_ADD_RTN_U32>;
1242def DS_SUB_RTN_U32_vi     : DS_Real_vi<0x21, DS_SUB_RTN_U32>;
1243def DS_RSUB_RTN_U32_vi    : DS_Real_vi<0x22, DS_RSUB_RTN_U32>;
1244def DS_INC_RTN_U32_vi     : DS_Real_vi<0x23, DS_INC_RTN_U32>;
1245def DS_DEC_RTN_U32_vi     : DS_Real_vi<0x24, DS_DEC_RTN_U32>;
1246def DS_MIN_RTN_I32_vi     : DS_Real_vi<0x25, DS_MIN_RTN_I32>;
1247def DS_MAX_RTN_I32_vi     : DS_Real_vi<0x26, DS_MAX_RTN_I32>;
1248def DS_MIN_RTN_U32_vi     : DS_Real_vi<0x27, DS_MIN_RTN_U32>;
1249def DS_MAX_RTN_U32_vi     : DS_Real_vi<0x28, DS_MAX_RTN_U32>;
1250def DS_AND_RTN_B32_vi     : DS_Real_vi<0x29, DS_AND_RTN_B32>;
1251def DS_OR_RTN_B32_vi      : DS_Real_vi<0x2a, DS_OR_RTN_B32>;
1252def DS_XOR_RTN_B32_vi     : DS_Real_vi<0x2b, DS_XOR_RTN_B32>;
1253def DS_MSKOR_RTN_B32_vi   : DS_Real_vi<0x2c, DS_MSKOR_RTN_B32>;
1254def DS_WRXCHG_RTN_B32_vi  : DS_Real_vi<0x2d, DS_WRXCHG_RTN_B32>;
1255def DS_WRXCHG2_RTN_B32_vi : DS_Real_vi<0x2e, DS_WRXCHG2_RTN_B32>;
1256def DS_WRXCHG2ST64_RTN_B32_vi : DS_Real_vi<0x2f, DS_WRXCHG2ST64_RTN_B32>;
1257def DS_CMPST_RTN_B32_vi   : DS_Real_vi<0x30, DS_CMPST_RTN_B32>;
1258def DS_CMPST_RTN_F32_vi   : DS_Real_vi<0x31, DS_CMPST_RTN_F32>;
1259def DS_MIN_RTN_F32_vi     : DS_Real_vi<0x32, DS_MIN_RTN_F32>;
1260def DS_MAX_RTN_F32_vi     : DS_Real_vi<0x33, DS_MAX_RTN_F32>;
1261def DS_WRAP_RTN_B32_vi    : DS_Real_vi<0x34, DS_WRAP_RTN_B32>;
1262def DS_ADD_RTN_F32_vi     : DS_Real_vi<0x35, DS_ADD_RTN_F32>;
1263def DS_READ_B32_vi        : DS_Real_vi<0x36, DS_READ_B32>;
1264def DS_READ2_B32_vi       : DS_Real_vi<0x37, DS_READ2_B32>;
1265def DS_READ2ST64_B32_vi   : DS_Real_vi<0x38, DS_READ2ST64_B32>;
1266def DS_READ_I8_vi         : DS_Real_vi<0x39, DS_READ_I8>;
1267def DS_READ_U8_vi         : DS_Real_vi<0x3a, DS_READ_U8>;
1268def DS_READ_I16_vi        : DS_Real_vi<0x3b, DS_READ_I16>;
1269def DS_READ_U16_vi        : DS_Real_vi<0x3c, DS_READ_U16>;
1270def DS_READ_ADDTID_B32_vi : DS_Real_vi<0xb6, DS_READ_ADDTID_B32>;
1271def DS_CONSUME_vi         : DS_Real_vi<0xbd, DS_CONSUME>;
1272def DS_APPEND_vi          : DS_Real_vi<0xbe, DS_APPEND>;
1273def DS_ORDERED_COUNT_vi   : DS_Real_vi<0xbf, DS_ORDERED_COUNT>;
1274def DS_SWIZZLE_B32_vi     : DS_Real_vi<0x3d, DS_SWIZZLE_B32>;
1275def DS_PERMUTE_B32_vi     : DS_Real_vi<0x3e, DS_PERMUTE_B32>;
1276def DS_BPERMUTE_B32_vi    : DS_Real_vi<0x3f, DS_BPERMUTE_B32>;
1277
1278def DS_ADD_U64_vi         : DS_Real_vi<0x40, DS_ADD_U64>;
1279def DS_SUB_U64_vi         : DS_Real_vi<0x41, DS_SUB_U64>;
1280def DS_RSUB_U64_vi        : DS_Real_vi<0x42, DS_RSUB_U64>;
1281def DS_INC_U64_vi         : DS_Real_vi<0x43, DS_INC_U64>;
1282def DS_DEC_U64_vi         : DS_Real_vi<0x44, DS_DEC_U64>;
1283def DS_MIN_I64_vi         : DS_Real_vi<0x45, DS_MIN_I64>;
1284def DS_MAX_I64_vi         : DS_Real_vi<0x46, DS_MAX_I64>;
1285def DS_MIN_U64_vi         : DS_Real_vi<0x47, DS_MIN_U64>;
1286def DS_MAX_U64_vi         : DS_Real_vi<0x48, DS_MAX_U64>;
1287def DS_AND_B64_vi         : DS_Real_vi<0x49, DS_AND_B64>;
1288def DS_OR_B64_vi          : DS_Real_vi<0x4a, DS_OR_B64>;
1289def DS_XOR_B64_vi         : DS_Real_vi<0x4b, DS_XOR_B64>;
1290def DS_MSKOR_B64_vi       : DS_Real_vi<0x4c, DS_MSKOR_B64>;
1291def DS_WRITE_B64_vi       : DS_Real_vi<0x4d, DS_WRITE_B64>;
1292def DS_WRITE2_B64_vi      : DS_Real_vi<0x4E, DS_WRITE2_B64>;
1293def DS_WRITE2ST64_B64_vi  : DS_Real_vi<0x4f, DS_WRITE2ST64_B64>;
1294def DS_CMPST_B64_vi       : DS_Real_vi<0x50, DS_CMPST_B64>;
1295def DS_CMPST_F64_vi       : DS_Real_vi<0x51, DS_CMPST_F64>;
1296def DS_MIN_F64_vi         : DS_Real_vi<0x52, DS_MIN_F64>;
1297def DS_MAX_F64_vi         : DS_Real_vi<0x53, DS_MAX_F64>;
1298
1299def DS_WRITE_B8_D16_HI_vi  : DS_Real_vi<0x54, DS_WRITE_B8_D16_HI>;
1300def DS_WRITE_B16_D16_HI_vi : DS_Real_vi<0x55, DS_WRITE_B16_D16_HI>;
1301
1302def DS_READ_U8_D16_vi     : DS_Real_vi<0x56, DS_READ_U8_D16>;
1303def DS_READ_U8_D16_HI_vi  : DS_Real_vi<0x57, DS_READ_U8_D16_HI>;
1304def DS_READ_I8_D16_vi     : DS_Real_vi<0x58, DS_READ_I8_D16>;
1305def DS_READ_I8_D16_HI_vi  : DS_Real_vi<0x59, DS_READ_I8_D16_HI>;
1306def DS_READ_U16_D16_vi    : DS_Real_vi<0x5a, DS_READ_U16_D16>;
1307def DS_READ_U16_D16_HI_vi : DS_Real_vi<0x5b, DS_READ_U16_D16_HI>;
1308
1309def DS_ADD_RTN_U64_vi     : DS_Real_vi<0x60, DS_ADD_RTN_U64>;
1310def DS_SUB_RTN_U64_vi     : DS_Real_vi<0x61, DS_SUB_RTN_U64>;
1311def DS_RSUB_RTN_U64_vi    : DS_Real_vi<0x62, DS_RSUB_RTN_U64>;
1312def DS_INC_RTN_U64_vi     : DS_Real_vi<0x63, DS_INC_RTN_U64>;
1313def DS_DEC_RTN_U64_vi     : DS_Real_vi<0x64, DS_DEC_RTN_U64>;
1314def DS_MIN_RTN_I64_vi     : DS_Real_vi<0x65, DS_MIN_RTN_I64>;
1315def DS_MAX_RTN_I64_vi     : DS_Real_vi<0x66, DS_MAX_RTN_I64>;
1316def DS_MIN_RTN_U64_vi     : DS_Real_vi<0x67, DS_MIN_RTN_U64>;
1317def DS_MAX_RTN_U64_vi     : DS_Real_vi<0x68, DS_MAX_RTN_U64>;
1318def DS_AND_RTN_B64_vi     : DS_Real_vi<0x69, DS_AND_RTN_B64>;
1319def DS_OR_RTN_B64_vi      : DS_Real_vi<0x6a, DS_OR_RTN_B64>;
1320def DS_XOR_RTN_B64_vi     : DS_Real_vi<0x6b, DS_XOR_RTN_B64>;
1321def DS_MSKOR_RTN_B64_vi   : DS_Real_vi<0x6c, DS_MSKOR_RTN_B64>;
1322def DS_WRXCHG_RTN_B64_vi  : DS_Real_vi<0x6d, DS_WRXCHG_RTN_B64>;
1323def DS_WRXCHG2_RTN_B64_vi : DS_Real_vi<0x6e, DS_WRXCHG2_RTN_B64>;
1324def DS_WRXCHG2ST64_RTN_B64_vi : DS_Real_vi<0x6f, DS_WRXCHG2ST64_RTN_B64>;
1325def DS_CONDXCHG32_RTN_B64_vi   : DS_Real_vi<0x7e, DS_CONDXCHG32_RTN_B64>;
1326def DS_GWS_SEMA_RELEASE_ALL_vi : DS_Real_vi<0x98, DS_GWS_SEMA_RELEASE_ALL>;
1327def DS_CMPST_RTN_B64_vi   : DS_Real_vi<0x70, DS_CMPST_RTN_B64>;
1328def DS_CMPST_RTN_F64_vi   : DS_Real_vi<0x71, DS_CMPST_RTN_F64>;
1329def DS_MIN_RTN_F64_vi     : DS_Real_vi<0x72, DS_MIN_RTN_F64>;
1330def DS_MAX_RTN_F64_vi     : DS_Real_vi<0x73, DS_MAX_RTN_F64>;
1331
1332def DS_READ_B64_vi        : DS_Real_vi<0x76, DS_READ_B64>;
1333def DS_READ2_B64_vi       : DS_Real_vi<0x77, DS_READ2_B64>;
1334def DS_READ2ST64_B64_vi   : DS_Real_vi<0x78, DS_READ2ST64_B64>;
1335
1336def DS_ADD_SRC2_U32_vi    : DS_Real_vi<0x80, DS_ADD_SRC2_U32>;
1337def DS_SUB_SRC2_U32_vi    : DS_Real_vi<0x81, DS_SUB_SRC2_U32>;
1338def DS_RSUB_SRC2_U32_vi   : DS_Real_vi<0x82, DS_RSUB_SRC2_U32>;
1339def DS_INC_SRC2_U32_vi    : DS_Real_vi<0x83, DS_INC_SRC2_U32>;
1340def DS_DEC_SRC2_U32_vi    : DS_Real_vi<0x84, DS_DEC_SRC2_U32>;
1341def DS_MIN_SRC2_I32_vi    : DS_Real_vi<0x85, DS_MIN_SRC2_I32>;
1342def DS_MAX_SRC2_I32_vi    : DS_Real_vi<0x86, DS_MAX_SRC2_I32>;
1343def DS_MIN_SRC2_U32_vi    : DS_Real_vi<0x87, DS_MIN_SRC2_U32>;
1344def DS_MAX_SRC2_U32_vi    : DS_Real_vi<0x88, DS_MAX_SRC2_U32>;
1345def DS_AND_SRC2_B32_vi    : DS_Real_vi<0x89, DS_AND_SRC2_B32>;
1346def DS_OR_SRC2_B32_vi     : DS_Real_vi<0x8a, DS_OR_SRC2_B32>;
1347def DS_XOR_SRC2_B32_vi    : DS_Real_vi<0x8b, DS_XOR_SRC2_B32>;
1348def DS_WRITE_SRC2_B32_vi  : DS_Real_vi<0x8d, DS_WRITE_SRC2_B32>;
1349def DS_MIN_SRC2_F32_vi    : DS_Real_vi<0x92, DS_MIN_SRC2_F32>;
1350def DS_MAX_SRC2_F32_vi    : DS_Real_vi<0x93, DS_MAX_SRC2_F32>;
1351def DS_ADD_SRC2_F32_vi    : DS_Real_vi<0x95, DS_ADD_SRC2_F32>;
1352def DS_ADD_SRC2_U64_vi    : DS_Real_vi<0xc0, DS_ADD_SRC2_U64>;
1353def DS_SUB_SRC2_U64_vi    : DS_Real_vi<0xc1, DS_SUB_SRC2_U64>;
1354def DS_RSUB_SRC2_U64_vi   : DS_Real_vi<0xc2, DS_RSUB_SRC2_U64>;
1355def DS_INC_SRC2_U64_vi    : DS_Real_vi<0xc3, DS_INC_SRC2_U64>;
1356def DS_DEC_SRC2_U64_vi    : DS_Real_vi<0xc4, DS_DEC_SRC2_U64>;
1357def DS_MIN_SRC2_I64_vi    : DS_Real_vi<0xc5, DS_MIN_SRC2_I64>;
1358def DS_MAX_SRC2_I64_vi    : DS_Real_vi<0xc6, DS_MAX_SRC2_I64>;
1359def DS_MIN_SRC2_U64_vi    : DS_Real_vi<0xc7, DS_MIN_SRC2_U64>;
1360def DS_MAX_SRC2_U64_vi    : DS_Real_vi<0xc8, DS_MAX_SRC2_U64>;
1361def DS_AND_SRC2_B64_vi    : DS_Real_vi<0xc9, DS_AND_SRC2_B64>;
1362def DS_OR_SRC2_B64_vi     : DS_Real_vi<0xca, DS_OR_SRC2_B64>;
1363def DS_XOR_SRC2_B64_vi    : DS_Real_vi<0xcb, DS_XOR_SRC2_B64>;
1364def DS_WRITE_SRC2_B64_vi  : DS_Real_vi<0xcd, DS_WRITE_SRC2_B64>;
1365def DS_MIN_SRC2_F64_vi    : DS_Real_vi<0xd2, DS_MIN_SRC2_F64>;
1366def DS_MAX_SRC2_F64_vi    : DS_Real_vi<0xd3, DS_MAX_SRC2_F64>;
1367def DS_WRITE_B96_vi       : DS_Real_vi<0xde, DS_WRITE_B96>;
1368def DS_WRITE_B128_vi      : DS_Real_vi<0xdf, DS_WRITE_B128>;
1369def DS_READ_B96_vi        : DS_Real_vi<0xfe, DS_READ_B96>;
1370def DS_READ_B128_vi       : DS_Real_vi<0xff, DS_READ_B128>;
1371
1372let SubtargetPredicate = isGFX90APlus in {
1373  def DS_ADD_F64_vi     : DS_Real_vi<0x5c, DS_ADD_F64>;
1374  def DS_ADD_RTN_F64_vi : DS_Real_vi<0x7c, DS_ADD_RTN_F64>;
1375} // End SubtargetPredicate = isGFX90APlus
1376