1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK --check-prefix=PRE-GFX8 %s 2; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK --check-prefix=GFX8 %s 3 4; CHECK-LABEL: {{^}}inline_asm: 5; CHECK: s_endpgm 6; CHECK: s_endpgm 7define amdgpu_kernel void @inline_asm(i32 addrspace(1)* %out) { 8entry: 9 store i32 5, i32 addrspace(1)* %out 10 call void asm sideeffect "s_endpgm", ""() 11 ret void 12} 13 14; CHECK-LABEL: {{^}}inline_asm_shader: 15; CHECK: s_endpgm 16; CHECK: s_endpgm 17define amdgpu_ps void @inline_asm_shader() { 18entry: 19 call void asm sideeffect "s_endpgm", ""() 20 ret void 21} 22 23 24; CHECK-LABEL: {{^}}branch_on_asm_vgpr: 25; Make sure VGPR inline assembly is treated as divergent. 26; CHECK: v_mov_b32 v{{[0-9]+}}, 0 27; CHECK: v_cmp_eq_u32 28; CHECK: s_and_saveexec_b64 29define amdgpu_kernel void @branch_on_asm_vgpr(i32 addrspace(1)* %out) { 30 %zero = call i32 asm "v_mov_b32 $0, 0", "=v"() 31 %cmp = icmp eq i32 %zero, 0 32 br i1 %cmp, label %if, label %endif 33 34if: 35 store i32 0, i32 addrspace(1)* %out 36 br label %endif 37 38endif: 39 ret void 40} 41 42; CHECK-LABEL: {{^}}branch_on_asm_sgpr: 43; Make sure SGPR inline assembly is treated as uniform 44; CHECK: s_mov_b32 s{{[0-9]+}}, 0 45; CHECK: s_cmp_lg_u32 46; CHECK: s_cbranch_scc0 47define amdgpu_kernel void @branch_on_asm_sgpr(i32 addrspace(1)* %out) { 48 %zero = call i32 asm "s_mov_b32 $0, 0", "=s"() 49 %cmp = icmp eq i32 %zero, 0 50 br i1 %cmp, label %if, label %endif 51 52if: 53 store i32 0, i32 addrspace(1)* %out 54 br label %endif 55 56endif: 57 ret void 58} 59 60; CHECK-LABEL: {{^}}v_cmp_asm: 61; CHECK: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}} 62; CHECK: v_cmp_ne_u32_e64 s{{\[}}[[MASK_LO:[0-9]+]]:[[MASK_HI:[0-9]+]]{{\]}}, 0, [[SRC]] 63; CHECK-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], s[[MASK_LO]] 64; CHECK-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], s[[MASK_HI]] 65; CHECK: buffer_store_dwordx2 v{{\[}}[[V_LO]]:[[V_HI]]{{\]}} 66define amdgpu_kernel void @v_cmp_asm(i64 addrspace(1)* %out, i32 %in) { 67 %sgpr = tail call i64 asm "v_cmp_ne_u32_e64 $0, 0, $1", "=s,v"(i32 %in) 68 store i64 %sgpr, i64 addrspace(1)* %out 69 ret void 70} 71 72; CHECK-LABEL: {{^}}code_size_inline_asm: 73; CHECK: codeLenInByte = 12 74define amdgpu_kernel void @code_size_inline_asm(i32 addrspace(1)* %out) { 75entry: 76 call void asm sideeffect "v_nop_e64", ""() 77 ret void 78} 79 80; All inlineasm instructions are assumed to be the maximum size 81; CHECK-LABEL: {{^}}code_size_inline_asm_small_inst: 82; CHECK: codeLenInByte = 12 83define amdgpu_kernel void @code_size_inline_asm_small_inst(i32 addrspace(1)* %out) { 84entry: 85 call void asm sideeffect "v_nop_e32", ""() 86 ret void 87} 88 89; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst: 90; CHECK: codeLenInByte = 20 91define amdgpu_kernel void @code_size_inline_asm_2_inst(i32 addrspace(1)* %out) { 92entry: 93 call void asm sideeffect " 94 v_nop_e64 95 v_nop_e64 96 ", ""() 97 ret void 98} 99 100; CHECK-LABEL: {{^}}code_size_inline_asm_2_inst_extra_newline: 101; CHECK: codeLenInByte = 20 102define amdgpu_kernel void @code_size_inline_asm_2_inst_extra_newline(i32 addrspace(1)* %out) { 103entry: 104 call void asm sideeffect " 105 v_nop_e64 106 107 v_nop_e64 108 ", ""() 109 ret void 110} 111 112; CHECK-LABEL: {{^}}code_size_inline_asm_0_inst: 113; CHECK: codeLenInByte = 4 114define amdgpu_kernel void @code_size_inline_asm_0_inst(i32 addrspace(1)* %out) { 115entry: 116 call void asm sideeffect "", ""() 117 ret void 118} 119 120; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment: 121; CHECK: codeLenInByte = 4 122define amdgpu_kernel void @code_size_inline_asm_1_comment(i32 addrspace(1)* %out) { 123entry: 124 call void asm sideeffect "; comment", ""() 125 ret void 126} 127 128; CHECK-LABEL: {{^}}code_size_inline_asm_newline_1_comment: 129; CHECK: codeLenInByte = 4 130define amdgpu_kernel void @code_size_inline_asm_newline_1_comment(i32 addrspace(1)* %out) { 131entry: 132 call void asm sideeffect " 133; comment", ""() 134 ret void 135} 136 137; CHECK-LABEL: {{^}}code_size_inline_asm_1_comment_newline: 138; CHECK: codeLenInByte = 4 139define amdgpu_kernel void @code_size_inline_asm_1_comment_newline(i32 addrspace(1)* %out) { 140entry: 141 call void asm sideeffect "; comment 142", ""() 143 ret void 144} 145 146; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line: 147; CHECK: codeLenInByte = 4 148define amdgpu_kernel void @code_size_inline_asm_2_comments_line(i32 addrspace(1)* %out) { 149entry: 150 call void asm sideeffect "; first comment ; second comment", ""() 151 ret void 152} 153 154; CHECK-LABEL: {{^}}code_size_inline_asm_2_comments_line_nospace: 155; CHECK: codeLenInByte = 4 156define amdgpu_kernel void @code_size_inline_asm_2_comments_line_nospace(i32 addrspace(1)* %out) { 157entry: 158 call void asm sideeffect "; first comment;second comment", ""() 159 ret void 160} 161 162; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments0: 163; CHECK: codeLenInByte = 20 164define amdgpu_kernel void @code_size_inline_asm_mixed_comments0(i32 addrspace(1)* %out) { 165entry: 166 call void asm sideeffect "; comment 167 v_nop_e64 ; inline comment 168; separate comment 169 v_nop_e64 170 171 ; trailing comment 172 ; extra comment 173 ", ""() 174 ret void 175} 176 177; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments1: 178; CHECK: codeLenInByte = 20 179define amdgpu_kernel void @code_size_inline_asm_mixed_comments1(i32 addrspace(1)* %out) { 180entry: 181 call void asm sideeffect "v_nop_e64 ; inline comment 182; separate comment 183 v_nop_e64 184 185 ; trailing comment 186 ; extra comment 187 ", ""() 188 ret void 189} 190 191; CHECK-LABEL: {{^}}code_size_inline_asm_mixed_comments_operands: 192; CHECK: codeLenInByte = 20 193define amdgpu_kernel void @code_size_inline_asm_mixed_comments_operands(i32 addrspace(1)* %out) { 194entry: 195 call void asm sideeffect "; comment 196 v_add_i32_e32 v0, vcc, v1, v2 ; inline comment 197; separate comment 198 v_bfrev_b32_e32 v0, 1 199 200 ; trailing comment 201 ; extra comment 202 ", ""() 203 ret void 204} 205 206; FIXME: Should not have intermediate sgprs 207; CHECK-LABEL: {{^}}i64_imm_input_phys_vgpr: 208; CHECK: s_mov_b64 s[0:1], 0x1e240 209; CHECK: v_mov_b32_e32 v0, s0 210; CHECK: v_mov_b32_e32 v1, s1 211; CHECK: use v[0:1] 212define amdgpu_kernel void @i64_imm_input_phys_vgpr() { 213entry: 214 call void asm sideeffect "; use $0 ", "{v[0:1]}"(i64 123456) 215 ret void 216} 217 218; CHECK-LABEL: {{^}}i1_imm_input_phys_vgpr: 219; CHECK: v_mov_b32_e32 v0, 1{{$}} 220; CHECK: ; use v0 221define amdgpu_kernel void @i1_imm_input_phys_vgpr() { 222entry: 223 call void asm sideeffect "; use $0 ", "{v0}"(i1 true) 224 ret void 225} 226 227 228; FIXME: This behavior is nonsense. We should probably disallow i1 asm 229 230; CHECK-LABEL: {{^}}i1_input_phys_vgpr: 231; CHECK: {{buffer|flat}}_load_ubyte [[LOAD:v[0-9]+]] 232; CHECK-NOT: [[LOAD]] 233; CHECK: ; use v0 234; CHECK: v_and_b32_e32 [[STORE:v[0-9]+]], 1, v1 235; CHECK: {{buffer|flat}}_store_byte [[STORE]], 236define amdgpu_kernel void @i1_input_phys_vgpr() { 237entry: 238 %val = load i1, i1 addrspace(1)* undef 239 %cc = call i1 asm sideeffect "; use $1, def $0 ", "={v1}, {v0}"(i1 %val) 240 store i1 %cc, i1 addrspace(1)* undef 241 ret void 242} 243 244; FIXME: Should prodbably be masking high bits of load. 245; CHECK-LABEL: {{^}}i1_input_phys_vgpr_x2: 246; CHECK: buffer_load_ubyte v0 247; CHECK-NEXT: s_waitcnt 248; CHECK-NEXT: buffer_load_ubyte v1 249; CHECK-NEXT: s_waitcnt 250; CHECK-NEXT: ASMSTART 251define amdgpu_kernel void @i1_input_phys_vgpr_x2() { 252entry: 253 %val0 = load volatile i1, i1 addrspace(1)* undef 254 %val1 = load volatile i1, i1 addrspace(1)* undef 255 call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1) 256 ret void 257} 258 259; CHECK-LABEL: {{^}}muliple_def_phys_vgpr: 260; CHECK: ; def v0 261; CHECK: v_mov_b32_e32 v1, v0 262; CHECK: ; def v0 263; PRE-GFX8: v_lshl_b32_e32 v{{[0-9]+}}, v1, v0 264; GFX8: v_lshlrev_b32_e32 v{{[0-9]+}}, v0, v1 265define amdgpu_kernel void @muliple_def_phys_vgpr() { 266entry: 267 %def0 = call i32 asm sideeffect "; def $0 ", "={v0}"() 268 %def1 = call i32 asm sideeffect "; def $0 ", "={v0}"() 269 %add = shl i32 %def0, %def1 270 store i32 %add, i32 addrspace(1)* undef 271 ret void 272} 273 274; CHECK-LABEL: {{^}}asm_constraint_c_n: 275; CHECK: s_trap 10{{$}} 276define amdgpu_kernel void @asm_constraint_c_n() { 277entry: 278 tail call void asm sideeffect "s_trap ${0:c}", "n"(i32 10) #1 279 ret void 280} 281 282; CHECK-LABEL: {{^}}asm_constraint_n_n: 283; CHECK: s_trap -10{{$}} 284define amdgpu_kernel void @asm_constraint_n_n() { 285entry: 286 tail call void asm sideeffect "s_trap ${0:n}", "n"(i32 10) #1 287 ret void 288} 289 290; Make sure tuples of 3 SGPRs are printed with the [] syntax instead 291; of the tablegen default. 292; CHECK-LABEL: {{^}}sgpr96_name_format: 293; CHECK: ; sgpr96 s[0:2] 294define amdgpu_kernel void @sgpr96_name_format() { 295entry: 296 tail call void asm sideeffect "; sgpr96 $0", "s"(<3 x i32> <i32 10, i32 11, i32 12>) #1 297 ret void 298} 299 300; Check aggregate types are handled properly. 301; CHECK-LABEL: mad_u64 302; CHECK: v_mad_u64_u32 303define void @mad_u64(i32 %x) { 304entry: 305 br i1 undef, label %exit, label %false 306 307false: 308 %s0 = tail call { i64, i64 } asm sideeffect "v_mad_u64_u32 $0, $1, $2, $3, $4", "=v,=s,v,v,v"(i32 -766435501, i32 %x, i64 0) 309 br label %exit 310 311exit: 312 %s1 = phi { i64, i64} [ undef, %entry ], [ %s0, %false] 313 %v0 = extractvalue { i64, i64 } %s1, 0 314 %v1 = extractvalue { i64, i64 } %s1, 1 315 tail call void asm sideeffect "; use $0", "v"(i64 %v0) 316 tail call void asm sideeffect "; use $0", "v"(i64 %v1) 317 ret void 318} 319