1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
2
3;;; Test pack intrinsic instructions
4;;;
5;;; Note:
6;;;   We test pack_f32p and pack_f32a pseudo instruction.
7
8; Function Attrs: nounwind readonly
9define fastcc i64 @pack_f32p(float* readonly %0, float* readonly %1) {
10; CHECK-LABEL: pack_f32p:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    ldu %s0, (, %s0)
13; CHECK-NEXT:    ldl.zx %s1, (, %s1)
14; CHECK-NEXT:    or %s0, %s0, %s1
15; CHECK-NEXT:    b.l.t (, %s10)
16  %3 = bitcast float* %0 to i8*
17  %4 = bitcast float* %1 to i8*
18  %5 = tail call i64 @llvm.ve.vl.pack.f32p(i8* %3, i8* %4)
19  ret i64 %5
20}
21
22; Function Attrs: nounwind readonly
23declare i64 @llvm.ve.vl.pack.f32p(i8*, i8*)
24
25; Function Attrs: nounwind readonly
26define fastcc i64 @pack_f32a(float* readonly %0) {
27; CHECK-LABEL: pack_f32a:
28; CHECK:       # %bb.0:
29; CHECK-NEXT:    ldl.zx %s0, (, %s0)
30; CHECK-NEXT:    lea %s1, 1
31; CHECK-NEXT:    and %s1, %s1, (32)0
32; CHECK-NEXT:    lea.sl %s1, 1(, %s1)
33; CHECK-NEXT:    mulu.l %s0, %s0, %s1
34; CHECK-NEXT:    b.l.t (, %s10)
35  %2 = bitcast float* %0 to i8*
36  %3 = tail call i64 @llvm.ve.vl.pack.f32a(i8* %2)
37  ret i64 %3
38}
39
40; Function Attrs: nounwind readonly
41declare i64 @llvm.ve.vl.pack.f32a(i8*)
42