1; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s 2 3;;; Test vector convert to fixed point intrinsic instructions 4;;; 5;;; Note: 6;;; We test VCVT*vl, VCVT*vl_v, VCVT*vml_v, PVCVT*vl, PVCVT*vl_v, and 7;;; PVCVT*vml_v instructions. 8 9; Function Attrs: nounwind readnone 10define fastcc <256 x double> @vcvtwdsx_vvl(<256 x double> %0) { 11; CHECK-LABEL: vcvtwdsx_vvl: 12; CHECK: # %bb.0: 13; CHECK-NEXT: lea %s0, 256 14; CHECK-NEXT: lvl %s0 15; CHECK-NEXT: vcvt.w.d.sx %v0, %v0 16; CHECK-NEXT: b.l.t (, %s10) 17 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdsx.vvl(<256 x double> %0, i32 256) 18 ret <256 x double> %2 19} 20 21; Function Attrs: nounwind readnone 22declare <256 x double> @llvm.ve.vl.vcvtwdsx.vvl(<256 x double>, i32) 23 24; Function Attrs: nounwind readnone 25define fastcc <256 x double> @vcvtwdsx_vvvl(<256 x double> %0, <256 x double> %1) { 26; CHECK-LABEL: vcvtwdsx_vvvl: 27; CHECK: # %bb.0: 28; CHECK-NEXT: lea %s0, 128 29; CHECK-NEXT: lvl %s0 30; CHECK-NEXT: vcvt.w.d.sx %v1, %v0 31; CHECK-NEXT: lea %s16, 256 32; CHECK-NEXT: lvl %s16 33; CHECK-NEXT: vor %v0, (0)1, %v1 34; CHECK-NEXT: b.l.t (, %s10) 35 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdsx.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 36 ret <256 x double> %3 37} 38 39; Function Attrs: nounwind readnone 40declare <256 x double> @llvm.ve.vl.vcvtwdsx.vvvl(<256 x double>, <256 x double>, i32) 41 42; Function Attrs: nounwind readnone 43define fastcc <256 x double> @vcvtwdsx_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 44; CHECK-LABEL: vcvtwdsx_vvmvl: 45; CHECK: # %bb.0: 46; CHECK-NEXT: lea %s0, 128 47; CHECK-NEXT: lvl %s0 48; CHECK-NEXT: vcvt.w.d.sx %v1, %v0, %vm1 49; CHECK-NEXT: lea %s16, 256 50; CHECK-NEXT: lvl %s16 51; CHECK-NEXT: vor %v0, (0)1, %v1 52; CHECK-NEXT: b.l.t (, %s10) 53 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdsx.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 54 ret <256 x double> %4 55} 56 57; Function Attrs: nounwind readnone 58declare <256 x double> @llvm.ve.vl.vcvtwdsx.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 59 60; Function Attrs: nounwind readnone 61define fastcc <256 x double> @vcvtwdsxrz_vvl(<256 x double> %0) { 62; CHECK-LABEL: vcvtwdsxrz_vvl: 63; CHECK: # %bb.0: 64; CHECK-NEXT: lea %s0, 256 65; CHECK-NEXT: lvl %s0 66; CHECK-NEXT: vcvt.w.d.sx.rz %v0, %v0 67; CHECK-NEXT: b.l.t (, %s10) 68 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdsxrz.vvl(<256 x double> %0, i32 256) 69 ret <256 x double> %2 70} 71 72; Function Attrs: nounwind readnone 73declare <256 x double> @llvm.ve.vl.vcvtwdsxrz.vvl(<256 x double>, i32) 74 75; Function Attrs: nounwind readnone 76define fastcc <256 x double> @vcvtwdsxrz_vvvl(<256 x double> %0, <256 x double> %1) { 77; CHECK-LABEL: vcvtwdsxrz_vvvl: 78; CHECK: # %bb.0: 79; CHECK-NEXT: lea %s0, 128 80; CHECK-NEXT: lvl %s0 81; CHECK-NEXT: vcvt.w.d.sx.rz %v1, %v0 82; CHECK-NEXT: lea %s16, 256 83; CHECK-NEXT: lvl %s16 84; CHECK-NEXT: vor %v0, (0)1, %v1 85; CHECK-NEXT: b.l.t (, %s10) 86 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdsxrz.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 87 ret <256 x double> %3 88} 89 90; Function Attrs: nounwind readnone 91declare <256 x double> @llvm.ve.vl.vcvtwdsxrz.vvvl(<256 x double>, <256 x double>, i32) 92 93; Function Attrs: nounwind readnone 94define fastcc <256 x double> @vcvtwdsxrz_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 95; CHECK-LABEL: vcvtwdsxrz_vvmvl: 96; CHECK: # %bb.0: 97; CHECK-NEXT: lea %s0, 128 98; CHECK-NEXT: lvl %s0 99; CHECK-NEXT: vcvt.w.d.sx.rz %v1, %v0, %vm1 100; CHECK-NEXT: lea %s16, 256 101; CHECK-NEXT: lvl %s16 102; CHECK-NEXT: vor %v0, (0)1, %v1 103; CHECK-NEXT: b.l.t (, %s10) 104 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdsxrz.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 105 ret <256 x double> %4 106} 107 108; Function Attrs: nounwind readnone 109declare <256 x double> @llvm.ve.vl.vcvtwdsxrz.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 110 111; Function Attrs: nounwind readnone 112define fastcc <256 x double> @vcvtwdzx_vvl(<256 x double> %0) { 113; CHECK-LABEL: vcvtwdzx_vvl: 114; CHECK: # %bb.0: 115; CHECK-NEXT: lea %s0, 256 116; CHECK-NEXT: lvl %s0 117; CHECK-NEXT: vcvt.w.d.zx %v0, %v0 118; CHECK-NEXT: b.l.t (, %s10) 119 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdzx.vvl(<256 x double> %0, i32 256) 120 ret <256 x double> %2 121} 122 123; Function Attrs: nounwind readnone 124declare <256 x double> @llvm.ve.vl.vcvtwdzx.vvl(<256 x double>, i32) 125 126; Function Attrs: nounwind readnone 127define fastcc <256 x double> @vcvtwdzx_vvvl(<256 x double> %0, <256 x double> %1) { 128; CHECK-LABEL: vcvtwdzx_vvvl: 129; CHECK: # %bb.0: 130; CHECK-NEXT: lea %s0, 128 131; CHECK-NEXT: lvl %s0 132; CHECK-NEXT: vcvt.w.d.zx %v1, %v0 133; CHECK-NEXT: lea %s16, 256 134; CHECK-NEXT: lvl %s16 135; CHECK-NEXT: vor %v0, (0)1, %v1 136; CHECK-NEXT: b.l.t (, %s10) 137 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdzx.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 138 ret <256 x double> %3 139} 140 141; Function Attrs: nounwind readnone 142declare <256 x double> @llvm.ve.vl.vcvtwdzx.vvvl(<256 x double>, <256 x double>, i32) 143 144; Function Attrs: nounwind readnone 145define fastcc <256 x double> @vcvtwdzx_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 146; CHECK-LABEL: vcvtwdzx_vvmvl: 147; CHECK: # %bb.0: 148; CHECK-NEXT: lea %s0, 128 149; CHECK-NEXT: lvl %s0 150; CHECK-NEXT: vcvt.w.d.zx %v1, %v0, %vm1 151; CHECK-NEXT: lea %s16, 256 152; CHECK-NEXT: lvl %s16 153; CHECK-NEXT: vor %v0, (0)1, %v1 154; CHECK-NEXT: b.l.t (, %s10) 155 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdzx.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 156 ret <256 x double> %4 157} 158 159; Function Attrs: nounwind readnone 160declare <256 x double> @llvm.ve.vl.vcvtwdzx.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 161 162; Function Attrs: nounwind readnone 163define fastcc <256 x double> @vcvtwdzxrz_vvl(<256 x double> %0) { 164; CHECK-LABEL: vcvtwdzxrz_vvl: 165; CHECK: # %bb.0: 166; CHECK-NEXT: lea %s0, 256 167; CHECK-NEXT: lvl %s0 168; CHECK-NEXT: vcvt.w.d.zx.rz %v0, %v0 169; CHECK-NEXT: b.l.t (, %s10) 170 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdzxrz.vvl(<256 x double> %0, i32 256) 171 ret <256 x double> %2 172} 173 174; Function Attrs: nounwind readnone 175declare <256 x double> @llvm.ve.vl.vcvtwdzxrz.vvl(<256 x double>, i32) 176 177; Function Attrs: nounwind readnone 178define fastcc <256 x double> @vcvtwdzxrz_vvvl(<256 x double> %0, <256 x double> %1) { 179; CHECK-LABEL: vcvtwdzxrz_vvvl: 180; CHECK: # %bb.0: 181; CHECK-NEXT: lea %s0, 128 182; CHECK-NEXT: lvl %s0 183; CHECK-NEXT: vcvt.w.d.zx.rz %v1, %v0 184; CHECK-NEXT: lea %s16, 256 185; CHECK-NEXT: lvl %s16 186; CHECK-NEXT: vor %v0, (0)1, %v1 187; CHECK-NEXT: b.l.t (, %s10) 188 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdzxrz.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 189 ret <256 x double> %3 190} 191 192; Function Attrs: nounwind readnone 193declare <256 x double> @llvm.ve.vl.vcvtwdzxrz.vvvl(<256 x double>, <256 x double>, i32) 194 195; Function Attrs: nounwind readnone 196define fastcc <256 x double> @vcvtwdzxrz_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 197; CHECK-LABEL: vcvtwdzxrz_vvmvl: 198; CHECK: # %bb.0: 199; CHECK-NEXT: lea %s0, 128 200; CHECK-NEXT: lvl %s0 201; CHECK-NEXT: vcvt.w.d.zx.rz %v1, %v0, %vm1 202; CHECK-NEXT: lea %s16, 256 203; CHECK-NEXT: lvl %s16 204; CHECK-NEXT: vor %v0, (0)1, %v1 205; CHECK-NEXT: b.l.t (, %s10) 206 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtwdzxrz.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 207 ret <256 x double> %4 208} 209 210; Function Attrs: nounwind readnone 211declare <256 x double> @llvm.ve.vl.vcvtwdzxrz.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 212 213; Function Attrs: nounwind readnone 214define fastcc <256 x double> @vcvtwssx_vvl(<256 x double> %0) { 215; CHECK-LABEL: vcvtwssx_vvl: 216; CHECK: # %bb.0: 217; CHECK-NEXT: lea %s0, 256 218; CHECK-NEXT: lvl %s0 219; CHECK-NEXT: vcvt.w.s.sx %v0, %v0 220; CHECK-NEXT: b.l.t (, %s10) 221 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtwssx.vvl(<256 x double> %0, i32 256) 222 ret <256 x double> %2 223} 224 225; Function Attrs: nounwind readnone 226declare <256 x double> @llvm.ve.vl.vcvtwssx.vvl(<256 x double>, i32) 227 228; Function Attrs: nounwind readnone 229define fastcc <256 x double> @vcvtwssx_vvvl(<256 x double> %0, <256 x double> %1) { 230; CHECK-LABEL: vcvtwssx_vvvl: 231; CHECK: # %bb.0: 232; CHECK-NEXT: lea %s0, 128 233; CHECK-NEXT: lvl %s0 234; CHECK-NEXT: vcvt.w.s.sx %v1, %v0 235; CHECK-NEXT: lea %s16, 256 236; CHECK-NEXT: lvl %s16 237; CHECK-NEXT: vor %v0, (0)1, %v1 238; CHECK-NEXT: b.l.t (, %s10) 239 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtwssx.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 240 ret <256 x double> %3 241} 242 243; Function Attrs: nounwind readnone 244declare <256 x double> @llvm.ve.vl.vcvtwssx.vvvl(<256 x double>, <256 x double>, i32) 245 246; Function Attrs: nounwind readnone 247define fastcc <256 x double> @vcvtwssx_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 248; CHECK-LABEL: vcvtwssx_vvmvl: 249; CHECK: # %bb.0: 250; CHECK-NEXT: lea %s0, 128 251; CHECK-NEXT: lvl %s0 252; CHECK-NEXT: vcvt.w.s.sx %v1, %v0, %vm1 253; CHECK-NEXT: lea %s16, 256 254; CHECK-NEXT: lvl %s16 255; CHECK-NEXT: vor %v0, (0)1, %v1 256; CHECK-NEXT: b.l.t (, %s10) 257 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtwssx.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 258 ret <256 x double> %4 259} 260 261; Function Attrs: nounwind readnone 262declare <256 x double> @llvm.ve.vl.vcvtwssx.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 263 264; Function Attrs: nounwind readnone 265define fastcc <256 x double> @vcvtwssxrz_vvl(<256 x double> %0) { 266; CHECK-LABEL: vcvtwssxrz_vvl: 267; CHECK: # %bb.0: 268; CHECK-NEXT: lea %s0, 256 269; CHECK-NEXT: lvl %s0 270; CHECK-NEXT: vcvt.w.s.sx.rz %v0, %v0 271; CHECK-NEXT: b.l.t (, %s10) 272 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtwssxrz.vvl(<256 x double> %0, i32 256) 273 ret <256 x double> %2 274} 275 276; Function Attrs: nounwind readnone 277declare <256 x double> @llvm.ve.vl.vcvtwssxrz.vvl(<256 x double>, i32) 278 279; Function Attrs: nounwind readnone 280define fastcc <256 x double> @vcvtwssxrz_vvvl(<256 x double> %0, <256 x double> %1) { 281; CHECK-LABEL: vcvtwssxrz_vvvl: 282; CHECK: # %bb.0: 283; CHECK-NEXT: lea %s0, 128 284; CHECK-NEXT: lvl %s0 285; CHECK-NEXT: vcvt.w.s.sx.rz %v1, %v0 286; CHECK-NEXT: lea %s16, 256 287; CHECK-NEXT: lvl %s16 288; CHECK-NEXT: vor %v0, (0)1, %v1 289; CHECK-NEXT: b.l.t (, %s10) 290 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtwssxrz.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 291 ret <256 x double> %3 292} 293 294; Function Attrs: nounwind readnone 295declare <256 x double> @llvm.ve.vl.vcvtwssxrz.vvvl(<256 x double>, <256 x double>, i32) 296 297; Function Attrs: nounwind readnone 298define fastcc <256 x double> @vcvtwssxrz_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 299; CHECK-LABEL: vcvtwssxrz_vvmvl: 300; CHECK: # %bb.0: 301; CHECK-NEXT: lea %s0, 128 302; CHECK-NEXT: lvl %s0 303; CHECK-NEXT: vcvt.w.s.sx.rz %v1, %v0, %vm1 304; CHECK-NEXT: lea %s16, 256 305; CHECK-NEXT: lvl %s16 306; CHECK-NEXT: vor %v0, (0)1, %v1 307; CHECK-NEXT: b.l.t (, %s10) 308 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtwssxrz.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 309 ret <256 x double> %4 310} 311 312; Function Attrs: nounwind readnone 313declare <256 x double> @llvm.ve.vl.vcvtwssxrz.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 314 315; Function Attrs: nounwind readnone 316define fastcc <256 x double> @vcvtwszx_vvl(<256 x double> %0) { 317; CHECK-LABEL: vcvtwszx_vvl: 318; CHECK: # %bb.0: 319; CHECK-NEXT: lea %s0, 256 320; CHECK-NEXT: lvl %s0 321; CHECK-NEXT: vcvt.w.s.zx %v0, %v0 322; CHECK-NEXT: b.l.t (, %s10) 323 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtwszx.vvl(<256 x double> %0, i32 256) 324 ret <256 x double> %2 325} 326 327; Function Attrs: nounwind readnone 328declare <256 x double> @llvm.ve.vl.vcvtwszx.vvl(<256 x double>, i32) 329 330; Function Attrs: nounwind readnone 331define fastcc <256 x double> @vcvtwszx_vvvl(<256 x double> %0, <256 x double> %1) { 332; CHECK-LABEL: vcvtwszx_vvvl: 333; CHECK: # %bb.0: 334; CHECK-NEXT: lea %s0, 128 335; CHECK-NEXT: lvl %s0 336; CHECK-NEXT: vcvt.w.s.zx %v1, %v0 337; CHECK-NEXT: lea %s16, 256 338; CHECK-NEXT: lvl %s16 339; CHECK-NEXT: vor %v0, (0)1, %v1 340; CHECK-NEXT: b.l.t (, %s10) 341 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtwszx.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 342 ret <256 x double> %3 343} 344 345; Function Attrs: nounwind readnone 346declare <256 x double> @llvm.ve.vl.vcvtwszx.vvvl(<256 x double>, <256 x double>, i32) 347 348; Function Attrs: nounwind readnone 349define fastcc <256 x double> @vcvtwszx_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 350; CHECK-LABEL: vcvtwszx_vvmvl: 351; CHECK: # %bb.0: 352; CHECK-NEXT: lea %s0, 128 353; CHECK-NEXT: lvl %s0 354; CHECK-NEXT: vcvt.w.s.zx %v1, %v0, %vm1 355; CHECK-NEXT: lea %s16, 256 356; CHECK-NEXT: lvl %s16 357; CHECK-NEXT: vor %v0, (0)1, %v1 358; CHECK-NEXT: b.l.t (, %s10) 359 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtwszx.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 360 ret <256 x double> %4 361} 362 363; Function Attrs: nounwind readnone 364declare <256 x double> @llvm.ve.vl.vcvtwszx.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 365 366; Function Attrs: nounwind readnone 367define fastcc <256 x double> @vcvtwszxrz_vvl(<256 x double> %0) { 368; CHECK-LABEL: vcvtwszxrz_vvl: 369; CHECK: # %bb.0: 370; CHECK-NEXT: lea %s0, 256 371; CHECK-NEXT: lvl %s0 372; CHECK-NEXT: vcvt.w.s.zx.rz %v0, %v0 373; CHECK-NEXT: b.l.t (, %s10) 374 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtwszxrz.vvl(<256 x double> %0, i32 256) 375 ret <256 x double> %2 376} 377 378; Function Attrs: nounwind readnone 379declare <256 x double> @llvm.ve.vl.vcvtwszxrz.vvl(<256 x double>, i32) 380 381; Function Attrs: nounwind readnone 382define fastcc <256 x double> @vcvtwszxrz_vvvl(<256 x double> %0, <256 x double> %1) { 383; CHECK-LABEL: vcvtwszxrz_vvvl: 384; CHECK: # %bb.0: 385; CHECK-NEXT: lea %s0, 128 386; CHECK-NEXT: lvl %s0 387; CHECK-NEXT: vcvt.w.s.zx.rz %v1, %v0 388; CHECK-NEXT: lea %s16, 256 389; CHECK-NEXT: lvl %s16 390; CHECK-NEXT: vor %v0, (0)1, %v1 391; CHECK-NEXT: b.l.t (, %s10) 392 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtwszxrz.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 393 ret <256 x double> %3 394} 395 396; Function Attrs: nounwind readnone 397declare <256 x double> @llvm.ve.vl.vcvtwszxrz.vvvl(<256 x double>, <256 x double>, i32) 398 399; Function Attrs: nounwind readnone 400define fastcc <256 x double> @vcvtwszxrz_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 401; CHECK-LABEL: vcvtwszxrz_vvmvl: 402; CHECK: # %bb.0: 403; CHECK-NEXT: lea %s0, 128 404; CHECK-NEXT: lvl %s0 405; CHECK-NEXT: vcvt.w.s.zx.rz %v1, %v0, %vm1 406; CHECK-NEXT: lea %s16, 256 407; CHECK-NEXT: lvl %s16 408; CHECK-NEXT: vor %v0, (0)1, %v1 409; CHECK-NEXT: b.l.t (, %s10) 410 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtwszxrz.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 411 ret <256 x double> %4 412} 413 414; Function Attrs: nounwind readnone 415declare <256 x double> @llvm.ve.vl.vcvtwszxrz.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 416 417; Function Attrs: nounwind readnone 418define fastcc <256 x double> @vcvtld_vvl(<256 x double> %0) { 419; CHECK-LABEL: vcvtld_vvl: 420; CHECK: # %bb.0: 421; CHECK-NEXT: lea %s0, 256 422; CHECK-NEXT: lvl %s0 423; CHECK-NEXT: vcvt.l.d %v0, %v0 424; CHECK-NEXT: b.l.t (, %s10) 425 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtld.vvl(<256 x double> %0, i32 256) 426 ret <256 x double> %2 427} 428 429; Function Attrs: nounwind readnone 430declare <256 x double> @llvm.ve.vl.vcvtld.vvl(<256 x double>, i32) 431 432; Function Attrs: nounwind readnone 433define fastcc <256 x double> @vcvtld_vvvl(<256 x double> %0, <256 x double> %1) { 434; CHECK-LABEL: vcvtld_vvvl: 435; CHECK: # %bb.0: 436; CHECK-NEXT: lea %s0, 128 437; CHECK-NEXT: lvl %s0 438; CHECK-NEXT: vcvt.l.d %v1, %v0 439; CHECK-NEXT: lea %s16, 256 440; CHECK-NEXT: lvl %s16 441; CHECK-NEXT: vor %v0, (0)1, %v1 442; CHECK-NEXT: b.l.t (, %s10) 443 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtld.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 444 ret <256 x double> %3 445} 446 447; Function Attrs: nounwind readnone 448declare <256 x double> @llvm.ve.vl.vcvtld.vvvl(<256 x double>, <256 x double>, i32) 449 450; Function Attrs: nounwind readnone 451define fastcc <256 x double> @vcvtld_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 452; CHECK-LABEL: vcvtld_vvmvl: 453; CHECK: # %bb.0: 454; CHECK-NEXT: lea %s0, 128 455; CHECK-NEXT: lvl %s0 456; CHECK-NEXT: vcvt.l.d %v1, %v0, %vm1 457; CHECK-NEXT: lea %s16, 256 458; CHECK-NEXT: lvl %s16 459; CHECK-NEXT: vor %v0, (0)1, %v1 460; CHECK-NEXT: b.l.t (, %s10) 461 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtld.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 462 ret <256 x double> %4 463} 464 465; Function Attrs: nounwind readnone 466declare <256 x double> @llvm.ve.vl.vcvtld.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 467 468; Function Attrs: nounwind readnone 469define fastcc <256 x double> @vcvtldrz_vvl(<256 x double> %0) { 470; CHECK-LABEL: vcvtldrz_vvl: 471; CHECK: # %bb.0: 472; CHECK-NEXT: lea %s0, 256 473; CHECK-NEXT: lvl %s0 474; CHECK-NEXT: vcvt.l.d.rz %v0, %v0 475; CHECK-NEXT: b.l.t (, %s10) 476 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtldrz.vvl(<256 x double> %0, i32 256) 477 ret <256 x double> %2 478} 479 480; Function Attrs: nounwind readnone 481declare <256 x double> @llvm.ve.vl.vcvtldrz.vvl(<256 x double>, i32) 482 483; Function Attrs: nounwind readnone 484define fastcc <256 x double> @vcvtldrz_vvvl(<256 x double> %0, <256 x double> %1) { 485; CHECK-LABEL: vcvtldrz_vvvl: 486; CHECK: # %bb.0: 487; CHECK-NEXT: lea %s0, 128 488; CHECK-NEXT: lvl %s0 489; CHECK-NEXT: vcvt.l.d.rz %v1, %v0 490; CHECK-NEXT: lea %s16, 256 491; CHECK-NEXT: lvl %s16 492; CHECK-NEXT: vor %v0, (0)1, %v1 493; CHECK-NEXT: b.l.t (, %s10) 494 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtldrz.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 495 ret <256 x double> %3 496} 497 498; Function Attrs: nounwind readnone 499declare <256 x double> @llvm.ve.vl.vcvtldrz.vvvl(<256 x double>, <256 x double>, i32) 500 501; Function Attrs: nounwind readnone 502define fastcc <256 x double> @vcvtldrz_vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2) { 503; CHECK-LABEL: vcvtldrz_vvmvl: 504; CHECK: # %bb.0: 505; CHECK-NEXT: lea %s0, 128 506; CHECK-NEXT: lvl %s0 507; CHECK-NEXT: vcvt.l.d.rz %v1, %v0, %vm1 508; CHECK-NEXT: lea %s16, 256 509; CHECK-NEXT: lvl %s16 510; CHECK-NEXT: vor %v0, (0)1, %v1 511; CHECK-NEXT: b.l.t (, %s10) 512 %4 = tail call fast <256 x double> @llvm.ve.vl.vcvtldrz.vvmvl(<256 x double> %0, <256 x i1> %1, <256 x double> %2, i32 128) 513 ret <256 x double> %4 514} 515 516; Function Attrs: nounwind readnone 517declare <256 x double> @llvm.ve.vl.vcvtldrz.vvmvl(<256 x double>, <256 x i1>, <256 x double>, i32) 518 519; Function Attrs: nounwind readnone 520define fastcc <256 x double> @vcvtdw_vvl(<256 x double> %0) { 521; CHECK-LABEL: vcvtdw_vvl: 522; CHECK: # %bb.0: 523; CHECK-NEXT: lea %s0, 256 524; CHECK-NEXT: lvl %s0 525; CHECK-NEXT: vcvt.d.w %v0, %v0 526; CHECK-NEXT: b.l.t (, %s10) 527 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtdw.vvl(<256 x double> %0, i32 256) 528 ret <256 x double> %2 529} 530 531; Function Attrs: nounwind readnone 532declare <256 x double> @llvm.ve.vl.vcvtdw.vvl(<256 x double>, i32) 533 534; Function Attrs: nounwind readnone 535define fastcc <256 x double> @vcvtdw_vvvl(<256 x double> %0, <256 x double> %1) { 536; CHECK-LABEL: vcvtdw_vvvl: 537; CHECK: # %bb.0: 538; CHECK-NEXT: lea %s0, 128 539; CHECK-NEXT: lvl %s0 540; CHECK-NEXT: vcvt.d.w %v1, %v0 541; CHECK-NEXT: lea %s16, 256 542; CHECK-NEXT: lvl %s16 543; CHECK-NEXT: vor %v0, (0)1, %v1 544; CHECK-NEXT: b.l.t (, %s10) 545 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtdw.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 546 ret <256 x double> %3 547} 548 549; Function Attrs: nounwind readnone 550declare <256 x double> @llvm.ve.vl.vcvtdw.vvvl(<256 x double>, <256 x double>, i32) 551 552; Function Attrs: nounwind readnone 553define fastcc <256 x double> @vcvtsw_vvl(<256 x double> %0) { 554; CHECK-LABEL: vcvtsw_vvl: 555; CHECK: # %bb.0: 556; CHECK-NEXT: lea %s0, 256 557; CHECK-NEXT: lvl %s0 558; CHECK-NEXT: vcvt.s.w %v0, %v0 559; CHECK-NEXT: b.l.t (, %s10) 560 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtsw.vvl(<256 x double> %0, i32 256) 561 ret <256 x double> %2 562} 563 564; Function Attrs: nounwind readnone 565declare <256 x double> @llvm.ve.vl.vcvtsw.vvl(<256 x double>, i32) 566 567; Function Attrs: nounwind readnone 568define fastcc <256 x double> @vcvtsw_vvvl(<256 x double> %0, <256 x double> %1) { 569; CHECK-LABEL: vcvtsw_vvvl: 570; CHECK: # %bb.0: 571; CHECK-NEXT: lea %s0, 128 572; CHECK-NEXT: lvl %s0 573; CHECK-NEXT: vcvt.s.w %v1, %v0 574; CHECK-NEXT: lea %s16, 256 575; CHECK-NEXT: lvl %s16 576; CHECK-NEXT: vor %v0, (0)1, %v1 577; CHECK-NEXT: b.l.t (, %s10) 578 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtsw.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 579 ret <256 x double> %3 580} 581 582; Function Attrs: nounwind readnone 583declare <256 x double> @llvm.ve.vl.vcvtsw.vvvl(<256 x double>, <256 x double>, i32) 584 585; Function Attrs: nounwind readnone 586define fastcc <256 x double> @vcvtdl_vvl(<256 x double> %0) { 587; CHECK-LABEL: vcvtdl_vvl: 588; CHECK: # %bb.0: 589; CHECK-NEXT: lea %s0, 256 590; CHECK-NEXT: lvl %s0 591; CHECK-NEXT: vcvt.d.l %v0, %v0 592; CHECK-NEXT: b.l.t (, %s10) 593 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtdl.vvl(<256 x double> %0, i32 256) 594 ret <256 x double> %2 595} 596 597; Function Attrs: nounwind readnone 598declare <256 x double> @llvm.ve.vl.vcvtdl.vvl(<256 x double>, i32) 599 600; Function Attrs: nounwind readnone 601define fastcc <256 x double> @vcvtdl_vvvl(<256 x double> %0, <256 x double> %1) { 602; CHECK-LABEL: vcvtdl_vvvl: 603; CHECK: # %bb.0: 604; CHECK-NEXT: lea %s0, 128 605; CHECK-NEXT: lvl %s0 606; CHECK-NEXT: vcvt.d.l %v1, %v0 607; CHECK-NEXT: lea %s16, 256 608; CHECK-NEXT: lvl %s16 609; CHECK-NEXT: vor %v0, (0)1, %v1 610; CHECK-NEXT: b.l.t (, %s10) 611 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtdl.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 612 ret <256 x double> %3 613} 614 615; Function Attrs: nounwind readnone 616declare <256 x double> @llvm.ve.vl.vcvtdl.vvvl(<256 x double>, <256 x double>, i32) 617 618; Function Attrs: nounwind readnone 619define fastcc <256 x double> @vcvtds_vvl(<256 x double> %0) { 620; CHECK-LABEL: vcvtds_vvl: 621; CHECK: # %bb.0: 622; CHECK-NEXT: lea %s0, 256 623; CHECK-NEXT: lvl %s0 624; CHECK-NEXT: vcvt.d.s %v0, %v0 625; CHECK-NEXT: b.l.t (, %s10) 626 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtds.vvl(<256 x double> %0, i32 256) 627 ret <256 x double> %2 628} 629 630; Function Attrs: nounwind readnone 631declare <256 x double> @llvm.ve.vl.vcvtds.vvl(<256 x double>, i32) 632 633; Function Attrs: nounwind readnone 634define fastcc <256 x double> @vcvtds_vvvl(<256 x double> %0, <256 x double> %1) { 635; CHECK-LABEL: vcvtds_vvvl: 636; CHECK: # %bb.0: 637; CHECK-NEXT: lea %s0, 128 638; CHECK-NEXT: lvl %s0 639; CHECK-NEXT: vcvt.d.s %v1, %v0 640; CHECK-NEXT: lea %s16, 256 641; CHECK-NEXT: lvl %s16 642; CHECK-NEXT: vor %v0, (0)1, %v1 643; CHECK-NEXT: b.l.t (, %s10) 644 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtds.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 645 ret <256 x double> %3 646} 647 648; Function Attrs: nounwind readnone 649declare <256 x double> @llvm.ve.vl.vcvtds.vvvl(<256 x double>, <256 x double>, i32) 650 651; Function Attrs: nounwind readnone 652define fastcc <256 x double> @vcvtsd_vvl(<256 x double> %0) { 653; CHECK-LABEL: vcvtsd_vvl: 654; CHECK: # %bb.0: 655; CHECK-NEXT: lea %s0, 256 656; CHECK-NEXT: lvl %s0 657; CHECK-NEXT: vcvt.s.d %v0, %v0 658; CHECK-NEXT: b.l.t (, %s10) 659 %2 = tail call fast <256 x double> @llvm.ve.vl.vcvtsd.vvl(<256 x double> %0, i32 256) 660 ret <256 x double> %2 661} 662 663; Function Attrs: nounwind readnone 664declare <256 x double> @llvm.ve.vl.vcvtsd.vvl(<256 x double>, i32) 665 666; Function Attrs: nounwind readnone 667define fastcc <256 x double> @vcvtsd_vvvl(<256 x double> %0, <256 x double> %1) { 668; CHECK-LABEL: vcvtsd_vvvl: 669; CHECK: # %bb.0: 670; CHECK-NEXT: lea %s0, 128 671; CHECK-NEXT: lvl %s0 672; CHECK-NEXT: vcvt.s.d %v1, %v0 673; CHECK-NEXT: lea %s16, 256 674; CHECK-NEXT: lvl %s16 675; CHECK-NEXT: vor %v0, (0)1, %v1 676; CHECK-NEXT: b.l.t (, %s10) 677 %3 = tail call fast <256 x double> @llvm.ve.vl.vcvtsd.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 678 ret <256 x double> %3 679} 680 681; Function Attrs: nounwind readnone 682declare <256 x double> @llvm.ve.vl.vcvtsd.vvvl(<256 x double>, <256 x double>, i32) 683 684; Function Attrs: nounwind readnone 685define fastcc <256 x double> @pvcvtws_vvl(<256 x double> %0) { 686; CHECK-LABEL: pvcvtws_vvl: 687; CHECK: # %bb.0: 688; CHECK-NEXT: lea %s0, 256 689; CHECK-NEXT: lvl %s0 690; CHECK-NEXT: pvcvt.w.s %v0, %v0 691; CHECK-NEXT: b.l.t (, %s10) 692 %2 = tail call fast <256 x double> @llvm.ve.vl.pvcvtws.vvl(<256 x double> %0, i32 256) 693 ret <256 x double> %2 694} 695 696; Function Attrs: nounwind readnone 697declare <256 x double> @llvm.ve.vl.pvcvtws.vvl(<256 x double>, i32) 698 699; Function Attrs: nounwind readnone 700define fastcc <256 x double> @pvcvtws_vvvl(<256 x double> %0, <256 x double> %1) { 701; CHECK-LABEL: pvcvtws_vvvl: 702; CHECK: # %bb.0: 703; CHECK-NEXT: lea %s0, 128 704; CHECK-NEXT: lvl %s0 705; CHECK-NEXT: pvcvt.w.s %v1, %v0 706; CHECK-NEXT: lea %s16, 256 707; CHECK-NEXT: lvl %s16 708; CHECK-NEXT: vor %v0, (0)1, %v1 709; CHECK-NEXT: b.l.t (, %s10) 710 %3 = tail call fast <256 x double> @llvm.ve.vl.pvcvtws.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 711 ret <256 x double> %3 712} 713 714; Function Attrs: nounwind readnone 715declare <256 x double> @llvm.ve.vl.pvcvtws.vvvl(<256 x double>, <256 x double>, i32) 716 717; Function Attrs: nounwind readnone 718define fastcc <256 x double> @pvcvtws_vvMvl(<256 x double> %0, <512 x i1> %1, <256 x double> %2) { 719; CHECK-LABEL: pvcvtws_vvMvl: 720; CHECK: # %bb.0: 721; CHECK-NEXT: lea %s0, 128 722; CHECK-NEXT: lvl %s0 723; CHECK-NEXT: pvcvt.w.s %v1, %v0, %vm2 724; CHECK-NEXT: lea %s16, 256 725; CHECK-NEXT: lvl %s16 726; CHECK-NEXT: vor %v0, (0)1, %v1 727; CHECK-NEXT: b.l.t (, %s10) 728 %4 = tail call fast <256 x double> @llvm.ve.vl.pvcvtws.vvMvl(<256 x double> %0, <512 x i1> %1, <256 x double> %2, i32 128) 729 ret <256 x double> %4 730} 731 732; Function Attrs: nounwind readnone 733declare <256 x double> @llvm.ve.vl.pvcvtws.vvMvl(<256 x double>, <512 x i1>, <256 x double>, i32) 734 735; Function Attrs: nounwind readnone 736define fastcc <256 x double> @pvcvtwsrz_vvl(<256 x double> %0) { 737; CHECK-LABEL: pvcvtwsrz_vvl: 738; CHECK: # %bb.0: 739; CHECK-NEXT: lea %s0, 256 740; CHECK-NEXT: lvl %s0 741; CHECK-NEXT: pvcvt.w.s.rz %v0, %v0 742; CHECK-NEXT: b.l.t (, %s10) 743 %2 = tail call fast <256 x double> @llvm.ve.vl.pvcvtwsrz.vvl(<256 x double> %0, i32 256) 744 ret <256 x double> %2 745} 746 747; Function Attrs: nounwind readnone 748declare <256 x double> @llvm.ve.vl.pvcvtwsrz.vvl(<256 x double>, i32) 749 750; Function Attrs: nounwind readnone 751define fastcc <256 x double> @pvcvtwsrz_vvvl(<256 x double> %0, <256 x double> %1) { 752; CHECK-LABEL: pvcvtwsrz_vvvl: 753; CHECK: # %bb.0: 754; CHECK-NEXT: lea %s0, 128 755; CHECK-NEXT: lvl %s0 756; CHECK-NEXT: pvcvt.w.s.rz %v1, %v0 757; CHECK-NEXT: lea %s16, 256 758; CHECK-NEXT: lvl %s16 759; CHECK-NEXT: vor %v0, (0)1, %v1 760; CHECK-NEXT: b.l.t (, %s10) 761 %3 = tail call fast <256 x double> @llvm.ve.vl.pvcvtwsrz.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 762 ret <256 x double> %3 763} 764 765; Function Attrs: nounwind readnone 766declare <256 x double> @llvm.ve.vl.pvcvtwsrz.vvvl(<256 x double>, <256 x double>, i32) 767 768; Function Attrs: nounwind readnone 769define fastcc <256 x double> @pvcvtwsrz_vvMvl(<256 x double> %0, <512 x i1> %1, <256 x double> %2) { 770; CHECK-LABEL: pvcvtwsrz_vvMvl: 771; CHECK: # %bb.0: 772; CHECK-NEXT: lea %s0, 128 773; CHECK-NEXT: lvl %s0 774; CHECK-NEXT: pvcvt.w.s.rz %v1, %v0, %vm2 775; CHECK-NEXT: lea %s16, 256 776; CHECK-NEXT: lvl %s16 777; CHECK-NEXT: vor %v0, (0)1, %v1 778; CHECK-NEXT: b.l.t (, %s10) 779 %4 = tail call fast <256 x double> @llvm.ve.vl.pvcvtwsrz.vvMvl(<256 x double> %0, <512 x i1> %1, <256 x double> %2, i32 128) 780 ret <256 x double> %4 781} 782 783; Function Attrs: nounwind readnone 784declare <256 x double> @llvm.ve.vl.pvcvtwsrz.vvMvl(<256 x double>, <512 x i1>, <256 x double>, i32) 785 786; Function Attrs: nounwind readnone 787define fastcc <256 x double> @pvcvtsw_vvl(<256 x double> %0) { 788; CHECK-LABEL: pvcvtsw_vvl: 789; CHECK: # %bb.0: 790; CHECK-NEXT: lea %s0, 256 791; CHECK-NEXT: lvl %s0 792; CHECK-NEXT: pvcvt.s.w %v0, %v0 793; CHECK-NEXT: b.l.t (, %s10) 794 %2 = tail call fast <256 x double> @llvm.ve.vl.pvcvtsw.vvl(<256 x double> %0, i32 256) 795 ret <256 x double> %2 796} 797 798; Function Attrs: nounwind readnone 799declare <256 x double> @llvm.ve.vl.pvcvtsw.vvl(<256 x double>, i32) 800 801; Function Attrs: nounwind readnone 802define fastcc <256 x double> @pvcvtsw_vvvl(<256 x double> %0, <256 x double> %1) { 803; CHECK-LABEL: pvcvtsw_vvvl: 804; CHECK: # %bb.0: 805; CHECK-NEXT: lea %s0, 128 806; CHECK-NEXT: lvl %s0 807; CHECK-NEXT: pvcvt.s.w %v1, %v0 808; CHECK-NEXT: lea %s16, 256 809; CHECK-NEXT: lvl %s16 810; CHECK-NEXT: vor %v0, (0)1, %v1 811; CHECK-NEXT: b.l.t (, %s10) 812 %3 = tail call fast <256 x double> @llvm.ve.vl.pvcvtsw.vvvl(<256 x double> %0, <256 x double> %1, i32 128) 813 ret <256 x double> %3 814} 815 816; Function Attrs: nounwind readnone 817declare <256 x double> @llvm.ve.vl.pvcvtsw.vvvl(<256 x double>, <256 x double>, i32) 818