1// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
2
3// --------------------------------------------------------------------------//
4// Immediate not compatible with encode/decode function.
5
6orn z5.b, z5.b, #0xfa
7// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
8// CHECK-NEXT: orn z5.b, z5.b, #0xfa
9// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
10
11orn z5.b, z5.b, #0xfff9
12// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
13// CHECK-NEXT: orn z5.b, z5.b, #0xfff9
14// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
15
16orn z5.h, z5.h, #0xfffa
17// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
18// CHECK-NEXT: orn z5.h, z5.h, #0xfffa
19// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
20
21orn z5.h, z5.h, #0xfffffff9
22// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
23// CHECK-NEXT: orn z5.h, z5.h, #0xfffffff9
24// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
25
26orn z5.s, z5.s, #0xfffffffa
27// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
28// CHECK-NEXT: orn z5.s, z5.s, #0xfffffffa
29// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
30
31orn z5.s, z5.s, #0xffffffffffffff9
32// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
33// CHECK-NEXT: orn z5.s, z5.s, #0xffffffffffffff9
34// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
35
36orn z15.d, z15.d, #0xfffffffffffffffa
37// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: expected compatible register or logical immediate
38// CHECK-NEXT: orn z15.d, z15.d, #0xfffffffffffffffa
39// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
40
41// --------------------------------------------------------------------------//
42// Source and Destination Registers must match
43
44orn z7.d, z8.d, #254
45// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
46// CHECK-NEXT: orn z7.d, z8.d, #254
47// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
48
49orn z7.d, z8.d, #254
50// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
51// CHECK-NEXT: orn z7.d, z8.d, #254
52// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
53
54
55// --------------------------------------------------------------------------//
56// Predicate register must have .b suffix
57
58orn p0.h, p0/z, p0.h, p1.h
59// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
60// CHECK-NEXT: orn p0.h, p0/z, p0.h, p1.h
61// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
62
63orn p0.s, p0/z, p0.s, p1.s
64// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
65// CHECK-NEXT: orn p0.s, p0/z, p0.s, p1.s
66// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
67
68orn p0.d, p0/z, p0.d, p1.d
69// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid predicate register.
70// CHECK-NEXT: orn p0.d, p0/z, p0.d, p1.d
71// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
72
73// --------------------------------------------------------------------------//
74// Operation only has zeroing predicate behaviour (p0/z).
75
76orn p0.b, p0/m, p1.b, p2.b
77// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
78// CHECK-NEXT: orn p0.b, p0/m, p1.b, p2.b
79// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
80
81
82// --------------------------------------------------------------------------//
83// Negative tests for instructions that are incompatible with movprfx
84
85movprfx z0.d, p0/z, z7.d
86orn     z0.d, z0.d, #0x6
87// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: instruction is unpredictable when following a predicated movprfx, suggest using unpredicated movprfx
88// CHECK-NEXT: orn     z0.d, z0.d, #0x6
89// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
90