1// RUN: llvm-tblgen -gen-compress-inst-emitter -I %p/../../include %s | \ 2// RUN: FileCheck --check-prefix=COMPRESS %s 3 4// Check that combining conditions in AssemblerPredicate generates the correct 5// output when using both the (all_of) AND operator, and the (any_of) OR 6// operator in the RISC-V specific instruction compressor. 7 8include "llvm/Target/Target.td" 9 10def archInstrInfo : InstrInfo { } 11def archAsmWriter : AsmWriter { 12 int PassSubtarget = 1; 13} 14 15def arch : Target { 16 let InstructionSet = archInstrInfo; 17 let AssemblyWriters = [archAsmWriter]; 18} 19 20let Namespace = "arch" in { 21 def R0 : Register<"r0">; 22} 23def Regs : RegisterClass<"Regs", [i32], 32, (add R0)>; 24 25class RVInst<int Opc, list<Predicate> Preds> : Instruction { 26 let Size = 4; 27 let OutOperandList = (outs); 28 let InOperandList = (ins Regs:$r); 29 field bits<32> Inst; 30 let Inst = Opc; 31 let AsmString = NAME # " $r"; 32 field bits<32> SoftFail = 0; 33 let Predicates = Preds; 34} 35class RVInst16<int Opc, list<Predicate> Preds> : Instruction { 36 let Size = 2; 37 let OutOperandList = (outs); 38 let InOperandList = (ins Regs:$r); 39 field bits<16> Inst; 40 let Inst = Opc; 41 let AsmString = NAME # " $r"; 42 field bits<16> SoftFail = 0; 43 let Predicates = Preds; 44} 45 46def AsmCond1 : SubtargetFeature<"cond1", "cond1", "true", "">; 47def AsmCond2a: SubtargetFeature<"cond2a", "cond2a", "true", "">; 48def AsmCond2b: SubtargetFeature<"cond2b", "cond2b", "true", "">; 49def AsmCond3a: SubtargetFeature<"cond3a", "cond3a", "true", "">; 50def AsmCond3b: SubtargetFeature<"cond3b", "cond3b", "true", "">; 51 52def AsmPred1 : Predicate<"Pred1">, AssemblerPredicate<(all_of AsmCond1)>; 53def AsmPred2 : Predicate<"Pred2">, AssemblerPredicate<(all_of AsmCond2a, AsmCond2b)>; 54def AsmPred3 : Predicate<"Pred3">, AssemblerPredicate<(any_of AsmCond3a, AsmCond3b)>; 55 56def BigInst : RVInst<1, [AsmPred1]>; 57 58class CompressPat<dag input, dag output, list<Predicate> predicates> { 59 dag Input = input; 60 dag Output = output; 61 list<Predicate> Predicates = predicates; 62 bit isCompressOnly = false; 63} 64 65// COMPRESS-LABEL: static bool compressInst 66// COMPRESS: case arch::BigInst 67def SmallInst1 : RVInst16<1, []>; 68def : CompressPat<(BigInst Regs:$r), (SmallInst1 Regs:$r), [AsmPred1]>; 69// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && 70// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { 71// COMPRESS-NEXT: // SmallInst1 $r 72 73def SmallInst2 : RVInst16<2, []>; 74def : CompressPat<(BigInst Regs:$r), (SmallInst2 Regs:$r), [AsmPred2]>; 75// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond2a] && 76// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] && 77// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { 78// COMPRESS-NEXT: // SmallInst2 $r 79 80def SmallInst3 : RVInst16<2, []>; 81def : CompressPat<(BigInst Regs:$r), (SmallInst3 Regs:$r), [AsmPred3]>; 82// COMPRESS: if ((STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) && 83// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { 84// COMPRESS-NEXT: // SmallInst3 $r 85 86def SmallInst4 : RVInst16<2, []>; 87def : CompressPat<(BigInst Regs:$r), (SmallInst4 Regs:$r), [AsmPred1, AsmPred2]>; 88// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && 89// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2a] && 90// COMPRESS-NEXT: STI.getFeatureBits()[arch::AsmCond2b] && 91// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { 92// COMPRESS-NEXT: // SmallInst4 $r 93 94def SmallInst5 : RVInst16<2, []>; 95def : CompressPat<(BigInst Regs:$r), (SmallInst5 Regs:$r), [AsmPred1, AsmPred3]>; 96// COMPRESS: if (STI.getFeatureBits()[arch::AsmCond1] && 97// COMPRESS-NEXT: (STI.getFeatureBits()[arch::AsmCond3a] || STI.getFeatureBits()[arch::AsmCond3b]) && 98// COMPRESS-NEXT: (MRI.getRegClass(arch::RegsRegClassID).contains(MI.getOperand(0).getReg()))) { 99// COMPRESS-NEXT: // SmallInst5 $r 100 101// COMPRESS-LABEL: static bool uncompressInst 102