1import("//llvm/utils/TableGen/tablegen.gni")
2
3tablegen("AMDGPUGenAsmMatcher") {
4  visibility = [ ":LLVMAMDGPUCodeGen" ]
5  args = [ "-gen-asm-matcher" ]
6  td_file = "AMDGPU.td"
7}
8
9tablegen("AMDGPUGenCallingConv") {
10  visibility = [ ":LLVMAMDGPUCodeGen" ]
11  args = [ "-gen-callingconv" ]
12  td_file = "AMDGPU.td"
13}
14
15tablegen("AMDGPUGenDAGISel") {
16  visibility = [ ":LLVMAMDGPUCodeGen" ]
17  args = [ "-gen-dag-isel" ]
18  td_file = "AMDGPU.td"
19}
20
21tablegen("AMDGPUGenGlobalISel") {
22  visibility = [ ":LLVMAMDGPUCodeGen" ]
23  args = [ "-gen-global-isel" ]
24  td_file = "AMDGPUGISel.td"
25}
26
27tablegen("AMDGPUGenPreLegalizeGICombiner") {
28  visibility = [ ":LLVMAMDGPUCodeGen" ]
29  args = [
30    "-gen-global-isel-combiner",
31    "-combiners=AMDGPUPreLegalizerCombinerHelper",
32  ]
33  td_file = "AMDGPUGISel.td"
34}
35
36tablegen("AMDGPUGenPostLegalizeGICombiner") {
37  visibility = [ ":LLVMAMDGPUCodeGen" ]
38  args = [
39    "-gen-global-isel-combiner",
40    "-combiners=AMDGPUPostLegalizerCombinerHelper",
41  ]
42  td_file = "AMDGPUGISel.td"
43}
44
45tablegen("AMDGPUGenRegBankGICombiner") {
46  visibility = [ ":LLVMAMDGPUCodeGen" ]
47  args = [
48    "-gen-global-isel-combiner",
49    "-combiners=AMDGPURegBankCombinerHelper",
50  ]
51  td_file = "AMDGPUGISel.td"
52}
53
54tablegen("AMDGPUGenMCPseudoLowering") {
55  visibility = [ ":LLVMAMDGPUCodeGen" ]
56  args = [ "-gen-pseudo-lowering" ]
57  td_file = "AMDGPU.td"
58}
59
60tablegen("AMDGPUGenRegisterBank") {
61  visibility = [ ":LLVMAMDGPUCodeGen" ]
62  args = [ "-gen-register-bank" ]
63  td_file = "AMDGPU.td"
64}
65
66tablegen("InstCombineTables") {
67  visibility = [ ":LLVMAMDGPUCodeGen" ]
68  args = [ "-gen-searchable-tables" ]
69}
70
71tablegen("R600GenCallingConv") {
72  visibility = [ ":LLVMAMDGPUCodeGen" ]
73  args = [ "-gen-callingconv" ]
74  td_file = "R600.td"
75}
76
77tablegen("R600GenDAGISel") {
78  visibility = [ ":LLVMAMDGPUCodeGen" ]
79  args = [ "-gen-dag-isel" ]
80  td_file = "R600.td"
81}
82
83tablegen("R600GenDFAPacketizer") {
84  visibility = [ ":LLVMAMDGPUCodeGen" ]
85  args = [ "-gen-dfa-packetizer" ]
86  td_file = "R600.td"
87}
88
89static_library("LLVMAMDGPUCodeGen") {
90  deps = [
91    ":AMDGPUGenAsmMatcher",
92    ":AMDGPUGenCallingConv",
93    ":AMDGPUGenDAGISel",
94    ":AMDGPUGenGlobalISel",
95    ":AMDGPUGenMCPseudoLowering",
96    ":AMDGPUGenPostLegalizeGICombiner",
97    ":AMDGPUGenPreLegalizeGICombiner",
98    ":AMDGPUGenRegBankGICombiner",
99    ":AMDGPUGenRegisterBank",
100    ":InstCombineTables",
101    ":R600GenCallingConv",
102    ":R600GenDAGISel",
103    ":R600GenDFAPacketizer",
104    "MCTargetDesc",
105    "TargetInfo",
106    "Utils",
107    "//llvm/lib/Analysis",
108    "//llvm/lib/CodeGen",
109    "//llvm/lib/CodeGen/AsmPrinter",
110    "//llvm/lib/CodeGen/GlobalISel",
111    "//llvm/lib/CodeGen/MIRParser",
112    "//llvm/lib/CodeGen/SelectionDAG",
113    "//llvm/lib/IR",
114    "//llvm/lib/MC",
115    "//llvm/lib/Passes",
116    "//llvm/lib/Support",
117    "//llvm/lib/Target",
118    "//llvm/lib/Transforms/IPO",
119    "//llvm/lib/Transforms/Scalar",
120    "//llvm/lib/Transforms/Utils",
121  ]
122  include_dirs = [ "." ]
123  sources = [
124    "AMDGPUAliasAnalysis.cpp",
125    "AMDGPUAlwaysInlinePass.cpp",
126    "AMDGPUAnnotateKernelFeatures.cpp",
127    "AMDGPUAnnotateUniformValues.cpp",
128    "AMDGPUArgumentUsageInfo.cpp",
129    "AMDGPUAsmPrinter.cpp",
130    "AMDGPUAtomicOptimizer.cpp",
131    "AMDGPUAttributor.cpp",
132    "AMDGPUCallLowering.cpp",
133    "AMDGPUCodeGenPrepare.cpp",
134    "AMDGPUExportClustering.cpp",
135    "AMDGPUFixFunctionBitcasts.cpp",
136    "AMDGPUFrameLowering.cpp",
137    "AMDGPUGlobalISelUtils.cpp",
138    "AMDGPUHSAMetadataStreamer.cpp",
139    "AMDGPUISelDAGToDAG.cpp",
140    "AMDGPUISelLowering.cpp",
141    "AMDGPUInstCombineIntrinsic.cpp",
142    "AMDGPUInstrInfo.cpp",
143    "AMDGPUInstructionSelector.cpp",
144    "AMDGPULateCodeGenPrepare.cpp",
145    "AMDGPULegalizerInfo.cpp",
146    "AMDGPULibCalls.cpp",
147    "AMDGPULibFunc.cpp",
148    "AMDGPULowerIntrinsics.cpp",
149    "AMDGPULowerKernelArguments.cpp",
150    "AMDGPULowerKernelAttributes.cpp",
151    "AMDGPULowerModuleLDSPass.cpp",
152    "AMDGPUMCInstLower.cpp",
153    "AMDGPUMIRFormatter.cpp",
154    "AMDGPUMachineCFGStructurizer.cpp",
155    "AMDGPUMachineFunction.cpp",
156    "AMDGPUMachineModuleInfo.cpp",
157    "AMDGPUMacroFusion.cpp",
158    "AMDGPUOpenCLEnqueuedBlockLowering.cpp",
159    "AMDGPUPerfHintAnalysis.cpp",
160    "AMDGPUPostLegalizerCombiner.cpp",
161    "AMDGPUPreLegalizerCombiner.cpp",
162    "AMDGPUPrintfRuntimeBinding.cpp",
163    "AMDGPUPromoteAlloca.cpp",
164    "AMDGPUPropagateAttributes.cpp",
165    "AMDGPURegBankCombiner.cpp",
166    "AMDGPURegisterBankInfo.cpp",
167    "AMDGPUReplaceLDSUseWithPointer.cpp",
168    "AMDGPUResourceUsageAnalysis.cpp",
169    "AMDGPURewriteOutArguments.cpp",
170    "AMDGPUSubtarget.cpp",
171    "AMDGPUTargetMachine.cpp",
172    "AMDGPUTargetObjectFile.cpp",
173    "AMDGPUTargetTransformInfo.cpp",
174    "AMDGPUUnifyDivergentExitNodes.cpp",
175    "AMDGPUUnifyMetadata.cpp",
176    "AMDILCFGStructurizer.cpp",
177    "GCNDPPCombine.cpp",
178    "GCNHazardRecognizer.cpp",
179    "GCNILPSched.cpp",
180    "GCNIterativeScheduler.cpp",
181    "GCNMinRegStrategy.cpp",
182    "GCNNSAReassign.cpp",
183    "GCNPreRAOptimizations.cpp",
184    "GCNRegPressure.cpp",
185    "GCNSchedStrategy.cpp",
186    "R600AsmPrinter.cpp",
187    "R600ClauseMergePass.cpp",
188    "R600ControlFlowFinalizer.cpp",
189    "R600EmitClauseMarkers.cpp",
190    "R600ExpandSpecialInstrs.cpp",
191    "R600FrameLowering.cpp",
192    "R600ISelLowering.cpp",
193    "R600InstrInfo.cpp",
194    "R600MachineFunctionInfo.cpp",
195    "R600MachineScheduler.cpp",
196    "R600OpenCLImageTypeLoweringPass.cpp",
197    "R600OptimizeVectorRegisters.cpp",
198    "R600Packetizer.cpp",
199    "R600RegisterInfo.cpp",
200    "SIAnnotateControlFlow.cpp",
201    "SIFixSGPRCopies.cpp",
202    "SIFixVGPRCopies.cpp",
203    "SIFoldOperands.cpp",
204    "SIFormMemoryClauses.cpp",
205    "SIFrameLowering.cpp",
206    "SIISelLowering.cpp",
207    "SIInsertHardClauses.cpp",
208    "SIInsertWaitcnts.cpp",
209    "SIInstrInfo.cpp",
210    "SILateBranchLowering.cpp",
211    "SILoadStoreOptimizer.cpp",
212    "SILowerControlFlow.cpp",
213    "SILowerI1Copies.cpp",
214    "SILowerSGPRSpills.cpp",
215    "SIMachineFunctionInfo.cpp",
216    "SIMachineScheduler.cpp",
217    "SIMemoryLegalizer.cpp",
218    "SIModeRegister.cpp",
219    "SIOptimizeExecMasking.cpp",
220    "SIOptimizeExecMaskingPreRA.cpp",
221    "SIOptimizeVGPRLiveRange.cpp",
222    "SIPeepholeSDWA.cpp",
223    "SIPostRABundler.cpp",
224    "SIPreAllocateWWMRegs.cpp",
225    "SIPreEmitPeephole.cpp",
226    "SIProgramInfo.cpp",
227    "SIRegisterInfo.cpp",
228    "SIShrinkInstructions.cpp",
229    "SIWholeQuadMode.cpp",
230  ]
231}
232
233# This is a bit different from most build files: Due to this group
234# having the directory's name, "//llvm/lib/Target/AMDGPU" will refer to this
235# target, which pulls in the code in this directory *and all subdirectories*.
236# For most other directories, "//llvm/lib/Foo" only pulls in the code directly
237# in "llvm/lib/Foo". The forwarding targets in //llvm/lib/Target expect this
238# different behavior.
239group("AMDGPU") {
240  deps = [
241    ":LLVMAMDGPUCodeGen",
242    "AsmParser",
243    "Disassembler",
244    "MCTargetDesc",
245    "TargetInfo",
246    "Utils",
247  ]
248}
249