1 //===--- X86.cpp - Implement X86 target feature support -------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements X86 TargetInfo objects.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86.h"
14 #include "clang/Basic/Builtins.h"
15 #include "clang/Basic/Diagnostic.h"
16 #include "clang/Basic/TargetBuiltins.h"
17 #include "llvm/ADT/StringExtras.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/Support/X86TargetParser.h"
21 
22 namespace clang {
23 namespace targets {
24 
25 const Builtin::Info BuiltinInfoX86[] = {
26 #define BUILTIN(ID, TYPE, ATTRS)                                               \
27   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
28 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
29   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
30 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
31   {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
32 #include "clang/Basic/BuiltinsX86.def"
33 
34 #define BUILTIN(ID, TYPE, ATTRS)                                               \
35   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr},
36 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE)                               \
37   {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE},
38 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE)         \
39   {#ID, TYPE, ATTRS, HEADER, LANGS, FEATURE},
40 #include "clang/Basic/BuiltinsX86_64.def"
41 };
42 
43 static const char *const GCCRegNames[] = {
44     "ax",    "dx",    "cx",    "bx",    "si",      "di",    "bp",    "sp",
45     "st",    "st(1)", "st(2)", "st(3)", "st(4)",   "st(5)", "st(6)", "st(7)",
46     "argp",  "flags", "fpcr",  "fpsr",  "dirflag", "frame", "xmm0",  "xmm1",
47     "xmm2",  "xmm3",  "xmm4",  "xmm5",  "xmm6",    "xmm7",  "mm0",   "mm1",
48     "mm2",   "mm3",   "mm4",   "mm5",   "mm6",     "mm7",   "r8",    "r9",
49     "r10",   "r11",   "r12",   "r13",   "r14",     "r15",   "xmm8",  "xmm9",
50     "xmm10", "xmm11", "xmm12", "xmm13", "xmm14",   "xmm15", "ymm0",  "ymm1",
51     "ymm2",  "ymm3",  "ymm4",  "ymm5",  "ymm6",    "ymm7",  "ymm8",  "ymm9",
52     "ymm10", "ymm11", "ymm12", "ymm13", "ymm14",   "ymm15", "xmm16", "xmm17",
53     "xmm18", "xmm19", "xmm20", "xmm21", "xmm22",   "xmm23", "xmm24", "xmm25",
54     "xmm26", "xmm27", "xmm28", "xmm29", "xmm30",   "xmm31", "ymm16", "ymm17",
55     "ymm18", "ymm19", "ymm20", "ymm21", "ymm22",   "ymm23", "ymm24", "ymm25",
56     "ymm26", "ymm27", "ymm28", "ymm29", "ymm30",   "ymm31", "zmm0",  "zmm1",
57     "zmm2",  "zmm3",  "zmm4",  "zmm5",  "zmm6",    "zmm7",  "zmm8",  "zmm9",
58     "zmm10", "zmm11", "zmm12", "zmm13", "zmm14",   "zmm15", "zmm16", "zmm17",
59     "zmm18", "zmm19", "zmm20", "zmm21", "zmm22",   "zmm23", "zmm24", "zmm25",
60     "zmm26", "zmm27", "zmm28", "zmm29", "zmm30",   "zmm31", "k0",    "k1",
61     "k2",    "k3",    "k4",    "k5",    "k6",      "k7",
62     "cr0",   "cr2",   "cr3",   "cr4",   "cr8",
63     "dr0",   "dr1",   "dr2",   "dr3",   "dr6",     "dr7",
64     "bnd0",  "bnd1",  "bnd2",  "bnd3",
65     "tmm0",  "tmm1",  "tmm2",  "tmm3",  "tmm4",    "tmm5",  "tmm6",  "tmm7",
66 };
67 
68 const TargetInfo::AddlRegName AddlRegNames[] = {
69     {{"al", "ah", "eax", "rax"}, 0},
70     {{"bl", "bh", "ebx", "rbx"}, 3},
71     {{"cl", "ch", "ecx", "rcx"}, 2},
72     {{"dl", "dh", "edx", "rdx"}, 1},
73     {{"esi", "rsi"}, 4},
74     {{"edi", "rdi"}, 5},
75     {{"esp", "rsp"}, 7},
76     {{"ebp", "rbp"}, 6},
77     {{"r8d", "r8w", "r8b"}, 38},
78     {{"r9d", "r9w", "r9b"}, 39},
79     {{"r10d", "r10w", "r10b"}, 40},
80     {{"r11d", "r11w", "r11b"}, 41},
81     {{"r12d", "r12w", "r12b"}, 42},
82     {{"r13d", "r13w", "r13b"}, 43},
83     {{"r14d", "r14w", "r14b"}, 44},
84     {{"r15d", "r15w", "r15b"}, 45},
85 };
86 
87 } // namespace targets
88 } // namespace clang
89 
90 using namespace clang;
91 using namespace clang::targets;
92 
setFPMath(StringRef Name)93 bool X86TargetInfo::setFPMath(StringRef Name) {
94   if (Name == "387") {
95     FPMath = FP_387;
96     return true;
97   }
98   if (Name == "sse") {
99     FPMath = FP_SSE;
100     return true;
101   }
102   return false;
103 }
104 
initFeatureMap(llvm::StringMap<bool> & Features,DiagnosticsEngine & Diags,StringRef CPU,const std::vector<std::string> & FeaturesVec) const105 bool X86TargetInfo::initFeatureMap(
106     llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU,
107     const std::vector<std::string> &FeaturesVec) const {
108   // FIXME: This *really* should not be here.
109   // X86_64 always has SSE2.
110   if (getTriple().getArch() == llvm::Triple::x86_64)
111     setFeatureEnabled(Features, "sse2", true);
112 
113   using namespace llvm::X86;
114 
115   SmallVector<StringRef, 16> CPUFeatures;
116   getFeaturesForCPU(CPU, CPUFeatures);
117   for (auto &F : CPUFeatures)
118     setFeatureEnabled(Features, F, true);
119 
120   std::vector<std::string> UpdatedFeaturesVec;
121   for (const auto &Feature : FeaturesVec) {
122     // Expand general-regs-only to -x86, -mmx and -sse
123     if (Feature == "+general-regs-only") {
124       UpdatedFeaturesVec.push_back("-x87");
125       UpdatedFeaturesVec.push_back("-mmx");
126       UpdatedFeaturesVec.push_back("-sse");
127       continue;
128     }
129 
130     UpdatedFeaturesVec.push_back(Feature);
131   }
132 
133   if (!TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec))
134     return false;
135 
136   // Can't do this earlier because we need to be able to explicitly enable
137   // or disable these features and the things that they depend upon.
138 
139   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
140   auto I = Features.find("sse4.2");
141   if (I != Features.end() && I->getValue() &&
142       llvm::find(UpdatedFeaturesVec, "-popcnt") == UpdatedFeaturesVec.end())
143     Features["popcnt"] = true;
144 
145   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
146   // then enable MMX.
147   I = Features.find("sse");
148   if (I != Features.end() && I->getValue() &&
149       llvm::find(UpdatedFeaturesVec, "-mmx") == UpdatedFeaturesVec.end())
150     Features["mmx"] = true;
151 
152   // Enable xsave if avx is enabled and xsave is not explicitly disabled.
153   I = Features.find("avx");
154   if (I != Features.end() && I->getValue() &&
155       llvm::find(UpdatedFeaturesVec, "-xsave") == UpdatedFeaturesVec.end())
156     Features["xsave"] = true;
157 
158   return true;
159 }
160 
setFeatureEnabled(llvm::StringMap<bool> & Features,StringRef Name,bool Enabled) const161 void X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
162                                       StringRef Name, bool Enabled) const {
163   if (Name == "sse4") {
164     // We can get here via the __target__ attribute since that's not controlled
165     // via the -msse4/-mno-sse4 command line alias. Handle this the same way
166     // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if
167     // disabled.
168     if (Enabled)
169       Name = "sse4.2";
170     else
171       Name = "sse4.1";
172   }
173 
174   Features[Name] = Enabled;
175   llvm::X86::updateImpliedFeatures(Name, Enabled, Features);
176 }
177 
178 /// handleTargetFeatures - Perform initialization based on the user
179 /// configured set of features.
handleTargetFeatures(std::vector<std::string> & Features,DiagnosticsEngine & Diags)180 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
181                                          DiagnosticsEngine &Diags) {
182   for (const auto &Feature : Features) {
183     if (Feature[0] != '+')
184       continue;
185 
186     if (Feature == "+aes") {
187       HasAES = true;
188     } else if (Feature == "+vaes") {
189       HasVAES = true;
190     } else if (Feature == "+pclmul") {
191       HasPCLMUL = true;
192     } else if (Feature == "+vpclmulqdq") {
193       HasVPCLMULQDQ = true;
194     } else if (Feature == "+lzcnt") {
195       HasLZCNT = true;
196     } else if (Feature == "+rdrnd") {
197       HasRDRND = true;
198     } else if (Feature == "+fsgsbase") {
199       HasFSGSBASE = true;
200     } else if (Feature == "+bmi") {
201       HasBMI = true;
202     } else if (Feature == "+bmi2") {
203       HasBMI2 = true;
204     } else if (Feature == "+popcnt") {
205       HasPOPCNT = true;
206     } else if (Feature == "+rtm") {
207       HasRTM = true;
208     } else if (Feature == "+prfchw") {
209       HasPRFCHW = true;
210     } else if (Feature == "+rdseed") {
211       HasRDSEED = true;
212     } else if (Feature == "+adx") {
213       HasADX = true;
214     } else if (Feature == "+tbm") {
215       HasTBM = true;
216     } else if (Feature == "+lwp") {
217       HasLWP = true;
218     } else if (Feature == "+fma") {
219       HasFMA = true;
220     } else if (Feature == "+f16c") {
221       HasF16C = true;
222     } else if (Feature == "+gfni") {
223       HasGFNI = true;
224     } else if (Feature == "+avx512cd") {
225       HasAVX512CD = true;
226     } else if (Feature == "+avx512vpopcntdq") {
227       HasAVX512VPOPCNTDQ = true;
228     } else if (Feature == "+avx512vnni") {
229       HasAVX512VNNI = true;
230     } else if (Feature == "+avx512bf16") {
231       HasAVX512BF16 = true;
232     } else if (Feature == "+avx512er") {
233       HasAVX512ER = true;
234     } else if (Feature == "+avx512pf") {
235       HasAVX512PF = true;
236     } else if (Feature == "+avx512dq") {
237       HasAVX512DQ = true;
238     } else if (Feature == "+avx512bitalg") {
239       HasAVX512BITALG = true;
240     } else if (Feature == "+avx512bw") {
241       HasAVX512BW = true;
242     } else if (Feature == "+avx512vl") {
243       HasAVX512VL = true;
244     } else if (Feature == "+avx512vbmi") {
245       HasAVX512VBMI = true;
246     } else if (Feature == "+avx512vbmi2") {
247       HasAVX512VBMI2 = true;
248     } else if (Feature == "+avx512ifma") {
249       HasAVX512IFMA = true;
250     } else if (Feature == "+avx512vp2intersect") {
251       HasAVX512VP2INTERSECT = true;
252     } else if (Feature == "+sha") {
253       HasSHA = true;
254     } else if (Feature == "+shstk") {
255       HasSHSTK = true;
256     } else if (Feature == "+movbe") {
257       HasMOVBE = true;
258     } else if (Feature == "+sgx") {
259       HasSGX = true;
260     } else if (Feature == "+cx8") {
261       HasCX8 = true;
262     } else if (Feature == "+cx16") {
263       HasCX16 = true;
264     } else if (Feature == "+fxsr") {
265       HasFXSR = true;
266     } else if (Feature == "+xsave") {
267       HasXSAVE = true;
268     } else if (Feature == "+xsaveopt") {
269       HasXSAVEOPT = true;
270     } else if (Feature == "+xsavec") {
271       HasXSAVEC = true;
272     } else if (Feature == "+xsaves") {
273       HasXSAVES = true;
274     } else if (Feature == "+mwaitx") {
275       HasMWAITX = true;
276     } else if (Feature == "+pku") {
277       HasPKU = true;
278     } else if (Feature == "+clflushopt") {
279       HasCLFLUSHOPT = true;
280     } else if (Feature == "+clwb") {
281       HasCLWB = true;
282     } else if (Feature == "+wbnoinvd") {
283       HasWBNOINVD = true;
284     } else if (Feature == "+prefetchwt1") {
285       HasPREFETCHWT1 = true;
286     } else if (Feature == "+clzero") {
287       HasCLZERO = true;
288     } else if (Feature == "+cldemote") {
289       HasCLDEMOTE = true;
290     } else if (Feature == "+rdpid") {
291       HasRDPID = true;
292     } else if (Feature == "+kl") {
293       HasKL = true;
294     } else if (Feature == "+widekl") {
295       HasWIDEKL = true;
296     } else if (Feature == "+retpoline-external-thunk") {
297       HasRetpolineExternalThunk = true;
298     } else if (Feature == "+sahf") {
299       HasLAHFSAHF = true;
300     } else if (Feature == "+waitpkg") {
301       HasWAITPKG = true;
302     } else if (Feature == "+movdiri") {
303       HasMOVDIRI = true;
304     } else if (Feature == "+movdir64b") {
305       HasMOVDIR64B = true;
306     } else if (Feature == "+pconfig") {
307       HasPCONFIG = true;
308     } else if (Feature == "+ptwrite") {
309       HasPTWRITE = true;
310     } else if (Feature == "+invpcid") {
311       HasINVPCID = true;
312     } else if (Feature == "+enqcmd") {
313       HasENQCMD = true;
314     } else if (Feature == "+hreset") {
315       HasHRESET = true;
316     } else if (Feature == "+amx-bf16") {
317       HasAMXBF16 = true;
318     } else if (Feature == "+amx-int8") {
319       HasAMXINT8 = true;
320     } else if (Feature == "+amx-tile") {
321       HasAMXTILE = true;
322     } else if (Feature == "+avxvnni") {
323       HasAVXVNNI = true;
324     } else if (Feature == "+serialize") {
325       HasSERIALIZE = true;
326     } else if (Feature == "+tsxldtrk") {
327       HasTSXLDTRK = true;
328     } else if (Feature == "+uintr") {
329       HasUINTR = true;
330     }
331 
332     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
333                            .Case("+avx512f", AVX512F)
334                            .Case("+avx2", AVX2)
335                            .Case("+avx", AVX)
336                            .Case("+sse4.2", SSE42)
337                            .Case("+sse4.1", SSE41)
338                            .Case("+ssse3", SSSE3)
339                            .Case("+sse3", SSE3)
340                            .Case("+sse2", SSE2)
341                            .Case("+sse", SSE1)
342                            .Default(NoSSE);
343     SSELevel = std::max(SSELevel, Level);
344 
345     MMX3DNowEnum ThreeDNowLevel = llvm::StringSwitch<MMX3DNowEnum>(Feature)
346                                       .Case("+3dnowa", AMD3DNowAthlon)
347                                       .Case("+3dnow", AMD3DNow)
348                                       .Case("+mmx", MMX)
349                                       .Default(NoMMX3DNow);
350     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
351 
352     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
353                          .Case("+xop", XOP)
354                          .Case("+fma4", FMA4)
355                          .Case("+sse4a", SSE4A)
356                          .Default(NoXOP);
357     XOPLevel = std::max(XOPLevel, XLevel);
358   }
359 
360   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
361   // matches the selected sse level.
362   if ((FPMath == FP_SSE && SSELevel < SSE1) ||
363       (FPMath == FP_387 && SSELevel >= SSE1)) {
364     Diags.Report(diag::err_target_unsupported_fpmath)
365         << (FPMath == FP_SSE ? "sse" : "387");
366     return false;
367   }
368 
369   SimdDefaultAlign =
370       hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
371   return true;
372 }
373 
374 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
375 /// definitions for this particular subtarget.
getTargetDefines(const LangOptions & Opts,MacroBuilder & Builder) const376 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
377                                      MacroBuilder &Builder) const {
378   // Inline assembly supports X86 flag outputs.
379   Builder.defineMacro("__GCC_ASM_FLAG_OUTPUTS__");
380 
381   std::string CodeModel = getTargetOpts().CodeModel;
382   if (CodeModel == "default")
383     CodeModel = "small";
384   Builder.defineMacro("__code_model_" + CodeModel + "__");
385 
386   // Target identification.
387   if (getTriple().getArch() == llvm::Triple::x86_64) {
388     Builder.defineMacro("__amd64__");
389     Builder.defineMacro("__amd64");
390     Builder.defineMacro("__x86_64");
391     Builder.defineMacro("__x86_64__");
392     if (getTriple().getArchName() == "x86_64h") {
393       Builder.defineMacro("__x86_64h");
394       Builder.defineMacro("__x86_64h__");
395     }
396   } else {
397     DefineStd(Builder, "i386", Opts);
398   }
399 
400   Builder.defineMacro("__SEG_GS");
401   Builder.defineMacro("__SEG_FS");
402   Builder.defineMacro("__seg_gs", "__attribute__((address_space(256)))");
403   Builder.defineMacro("__seg_fs", "__attribute__((address_space(257)))");
404 
405   // Subtarget options.
406   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
407   // truly should be based on -mtune options.
408   using namespace llvm::X86;
409   switch (CPU) {
410   case CK_None:
411     break;
412   case CK_i386:
413     // The rest are coming from the i386 define above.
414     Builder.defineMacro("__tune_i386__");
415     break;
416   case CK_i486:
417   case CK_WinChipC6:
418   case CK_WinChip2:
419   case CK_C3:
420     defineCPUMacros(Builder, "i486");
421     break;
422   case CK_PentiumMMX:
423     Builder.defineMacro("__pentium_mmx__");
424     Builder.defineMacro("__tune_pentium_mmx__");
425     LLVM_FALLTHROUGH;
426   case CK_i586:
427   case CK_Pentium:
428     defineCPUMacros(Builder, "i586");
429     defineCPUMacros(Builder, "pentium");
430     break;
431   case CK_Pentium3:
432   case CK_PentiumM:
433     Builder.defineMacro("__tune_pentium3__");
434     LLVM_FALLTHROUGH;
435   case CK_Pentium2:
436   case CK_C3_2:
437     Builder.defineMacro("__tune_pentium2__");
438     LLVM_FALLTHROUGH;
439   case CK_PentiumPro:
440   case CK_i686:
441     defineCPUMacros(Builder, "i686");
442     defineCPUMacros(Builder, "pentiumpro");
443     break;
444   case CK_Pentium4:
445     defineCPUMacros(Builder, "pentium4");
446     break;
447   case CK_Yonah:
448   case CK_Prescott:
449   case CK_Nocona:
450     defineCPUMacros(Builder, "nocona");
451     break;
452   case CK_Core2:
453   case CK_Penryn:
454     defineCPUMacros(Builder, "core2");
455     break;
456   case CK_Bonnell:
457     defineCPUMacros(Builder, "atom");
458     break;
459   case CK_Silvermont:
460     defineCPUMacros(Builder, "slm");
461     break;
462   case CK_Goldmont:
463     defineCPUMacros(Builder, "goldmont");
464     break;
465   case CK_GoldmontPlus:
466     defineCPUMacros(Builder, "goldmont_plus");
467     break;
468   case CK_Tremont:
469     defineCPUMacros(Builder, "tremont");
470     break;
471   case CK_Nehalem:
472   case CK_Westmere:
473   case CK_SandyBridge:
474   case CK_IvyBridge:
475   case CK_Haswell:
476   case CK_Broadwell:
477   case CK_SkylakeClient:
478   case CK_SkylakeServer:
479   case CK_Cascadelake:
480   case CK_Cooperlake:
481   case CK_Cannonlake:
482   case CK_IcelakeClient:
483   case CK_Rocketlake:
484   case CK_IcelakeServer:
485   case CK_Tigerlake:
486   case CK_SapphireRapids:
487   case CK_Alderlake:
488     // FIXME: Historically, we defined this legacy name, it would be nice to
489     // remove it at some point. We've never exposed fine-grained names for
490     // recent primary x86 CPUs, and we should keep it that way.
491     defineCPUMacros(Builder, "corei7");
492     break;
493   case CK_KNL:
494     defineCPUMacros(Builder, "knl");
495     break;
496   case CK_KNM:
497     break;
498   case CK_Lakemont:
499     defineCPUMacros(Builder, "i586", /*Tuning*/false);
500     defineCPUMacros(Builder, "pentium", /*Tuning*/false);
501     Builder.defineMacro("__tune_lakemont__");
502     break;
503   case CK_K6_2:
504     Builder.defineMacro("__k6_2__");
505     Builder.defineMacro("__tune_k6_2__");
506     LLVM_FALLTHROUGH;
507   case CK_K6_3:
508     if (CPU != CK_K6_2) { // In case of fallthrough
509       // FIXME: GCC may be enabling these in cases where some other k6
510       // architecture is specified but -m3dnow is explicitly provided. The
511       // exact semantics need to be determined and emulated here.
512       Builder.defineMacro("__k6_3__");
513       Builder.defineMacro("__tune_k6_3__");
514     }
515     LLVM_FALLTHROUGH;
516   case CK_K6:
517     defineCPUMacros(Builder, "k6");
518     break;
519   case CK_Athlon:
520   case CK_AthlonXP:
521     defineCPUMacros(Builder, "athlon");
522     if (SSELevel != NoSSE) {
523       Builder.defineMacro("__athlon_sse__");
524       Builder.defineMacro("__tune_athlon_sse__");
525     }
526     break;
527   case CK_K8:
528   case CK_K8SSE3:
529   case CK_x86_64:
530     defineCPUMacros(Builder, "k8");
531     break;
532   case CK_x86_64_v2:
533   case CK_x86_64_v3:
534   case CK_x86_64_v4:
535     break;
536   case CK_AMDFAM10:
537     defineCPUMacros(Builder, "amdfam10");
538     break;
539   case CK_BTVER1:
540     defineCPUMacros(Builder, "btver1");
541     break;
542   case CK_BTVER2:
543     defineCPUMacros(Builder, "btver2");
544     break;
545   case CK_BDVER1:
546     defineCPUMacros(Builder, "bdver1");
547     break;
548   case CK_BDVER2:
549     defineCPUMacros(Builder, "bdver2");
550     break;
551   case CK_BDVER3:
552     defineCPUMacros(Builder, "bdver3");
553     break;
554   case CK_BDVER4:
555     defineCPUMacros(Builder, "bdver4");
556     break;
557   case CK_ZNVER1:
558     defineCPUMacros(Builder, "znver1");
559     break;
560   case CK_ZNVER2:
561     defineCPUMacros(Builder, "znver2");
562     break;
563   case CK_ZNVER3:
564     defineCPUMacros(Builder, "znver3");
565     break;
566   case CK_Geode:
567     defineCPUMacros(Builder, "geode");
568     break;
569   }
570 
571   // Target properties.
572   Builder.defineMacro("__REGISTER_PREFIX__", "");
573 
574   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
575   // functions in glibc header files that use FP Stack inline asm which the
576   // backend can't deal with (PR879).
577   Builder.defineMacro("__NO_MATH_INLINES");
578 
579   if (HasAES)
580     Builder.defineMacro("__AES__");
581 
582   if (HasVAES)
583     Builder.defineMacro("__VAES__");
584 
585   if (HasPCLMUL)
586     Builder.defineMacro("__PCLMUL__");
587 
588   if (HasVPCLMULQDQ)
589     Builder.defineMacro("__VPCLMULQDQ__");
590 
591   // Note, in 32-bit mode, GCC does not define the macro if -mno-sahf. In LLVM,
592   // the feature flag only applies to 64-bit mode.
593   if (HasLAHFSAHF || getTriple().getArch() == llvm::Triple::x86)
594     Builder.defineMacro("__LAHF_SAHF__");
595 
596   if (HasLZCNT)
597     Builder.defineMacro("__LZCNT__");
598 
599   if (HasRDRND)
600     Builder.defineMacro("__RDRND__");
601 
602   if (HasFSGSBASE)
603     Builder.defineMacro("__FSGSBASE__");
604 
605   if (HasBMI)
606     Builder.defineMacro("__BMI__");
607 
608   if (HasBMI2)
609     Builder.defineMacro("__BMI2__");
610 
611   if (HasPOPCNT)
612     Builder.defineMacro("__POPCNT__");
613 
614   if (HasRTM)
615     Builder.defineMacro("__RTM__");
616 
617   if (HasPRFCHW)
618     Builder.defineMacro("__PRFCHW__");
619 
620   if (HasRDSEED)
621     Builder.defineMacro("__RDSEED__");
622 
623   if (HasADX)
624     Builder.defineMacro("__ADX__");
625 
626   if (HasTBM)
627     Builder.defineMacro("__TBM__");
628 
629   if (HasLWP)
630     Builder.defineMacro("__LWP__");
631 
632   if (HasMWAITX)
633     Builder.defineMacro("__MWAITX__");
634 
635   if (HasMOVBE)
636     Builder.defineMacro("__MOVBE__");
637 
638   switch (XOPLevel) {
639   case XOP:
640     Builder.defineMacro("__XOP__");
641     LLVM_FALLTHROUGH;
642   case FMA4:
643     Builder.defineMacro("__FMA4__");
644     LLVM_FALLTHROUGH;
645   case SSE4A:
646     Builder.defineMacro("__SSE4A__");
647     LLVM_FALLTHROUGH;
648   case NoXOP:
649     break;
650   }
651 
652   if (HasFMA)
653     Builder.defineMacro("__FMA__");
654 
655   if (HasF16C)
656     Builder.defineMacro("__F16C__");
657 
658   if (HasGFNI)
659     Builder.defineMacro("__GFNI__");
660 
661   if (HasAVX512CD)
662     Builder.defineMacro("__AVX512CD__");
663   if (HasAVX512VPOPCNTDQ)
664     Builder.defineMacro("__AVX512VPOPCNTDQ__");
665   if (HasAVX512VNNI)
666     Builder.defineMacro("__AVX512VNNI__");
667   if (HasAVX512BF16)
668     Builder.defineMacro("__AVX512BF16__");
669   if (HasAVX512ER)
670     Builder.defineMacro("__AVX512ER__");
671   if (HasAVX512PF)
672     Builder.defineMacro("__AVX512PF__");
673   if (HasAVX512DQ)
674     Builder.defineMacro("__AVX512DQ__");
675   if (HasAVX512BITALG)
676     Builder.defineMacro("__AVX512BITALG__");
677   if (HasAVX512BW)
678     Builder.defineMacro("__AVX512BW__");
679   if (HasAVX512VL)
680     Builder.defineMacro("__AVX512VL__");
681   if (HasAVX512VBMI)
682     Builder.defineMacro("__AVX512VBMI__");
683   if (HasAVX512VBMI2)
684     Builder.defineMacro("__AVX512VBMI2__");
685   if (HasAVX512IFMA)
686     Builder.defineMacro("__AVX512IFMA__");
687   if (HasAVX512VP2INTERSECT)
688     Builder.defineMacro("__AVX512VP2INTERSECT__");
689   if (HasSHA)
690     Builder.defineMacro("__SHA__");
691 
692   if (HasFXSR)
693     Builder.defineMacro("__FXSR__");
694   if (HasXSAVE)
695     Builder.defineMacro("__XSAVE__");
696   if (HasXSAVEOPT)
697     Builder.defineMacro("__XSAVEOPT__");
698   if (HasXSAVEC)
699     Builder.defineMacro("__XSAVEC__");
700   if (HasXSAVES)
701     Builder.defineMacro("__XSAVES__");
702   if (HasPKU)
703     Builder.defineMacro("__PKU__");
704   if (HasCLFLUSHOPT)
705     Builder.defineMacro("__CLFLUSHOPT__");
706   if (HasCLWB)
707     Builder.defineMacro("__CLWB__");
708   if (HasWBNOINVD)
709     Builder.defineMacro("__WBNOINVD__");
710   if (HasSHSTK)
711     Builder.defineMacro("__SHSTK__");
712   if (HasSGX)
713     Builder.defineMacro("__SGX__");
714   if (HasPREFETCHWT1)
715     Builder.defineMacro("__PREFETCHWT1__");
716   if (HasCLZERO)
717     Builder.defineMacro("__CLZERO__");
718   if (HasKL)
719     Builder.defineMacro("__KL__");
720   if (HasWIDEKL)
721     Builder.defineMacro("__WIDEKL__");
722   if (HasRDPID)
723     Builder.defineMacro("__RDPID__");
724   if (HasCLDEMOTE)
725     Builder.defineMacro("__CLDEMOTE__");
726   if (HasWAITPKG)
727     Builder.defineMacro("__WAITPKG__");
728   if (HasMOVDIRI)
729     Builder.defineMacro("__MOVDIRI__");
730   if (HasMOVDIR64B)
731     Builder.defineMacro("__MOVDIR64B__");
732   if (HasPCONFIG)
733     Builder.defineMacro("__PCONFIG__");
734   if (HasPTWRITE)
735     Builder.defineMacro("__PTWRITE__");
736   if (HasINVPCID)
737     Builder.defineMacro("__INVPCID__");
738   if (HasENQCMD)
739     Builder.defineMacro("__ENQCMD__");
740   if (HasHRESET)
741     Builder.defineMacro("__HRESET__");
742   if (HasAMXTILE)
743     Builder.defineMacro("__AMXTILE__");
744   if (HasAMXINT8)
745     Builder.defineMacro("__AMXINT8__");
746   if (HasAMXBF16)
747     Builder.defineMacro("__AMXBF16__");
748   if (HasAVXVNNI)
749     Builder.defineMacro("__AVXVNNI__");
750   if (HasSERIALIZE)
751     Builder.defineMacro("__SERIALIZE__");
752   if (HasTSXLDTRK)
753     Builder.defineMacro("__TSXLDTRK__");
754   if (HasUINTR)
755     Builder.defineMacro("__UINTR__");
756 
757   // Each case falls through to the previous one here.
758   switch (SSELevel) {
759   case AVX512F:
760     Builder.defineMacro("__AVX512F__");
761     LLVM_FALLTHROUGH;
762   case AVX2:
763     Builder.defineMacro("__AVX2__");
764     LLVM_FALLTHROUGH;
765   case AVX:
766     Builder.defineMacro("__AVX__");
767     LLVM_FALLTHROUGH;
768   case SSE42:
769     Builder.defineMacro("__SSE4_2__");
770     LLVM_FALLTHROUGH;
771   case SSE41:
772     Builder.defineMacro("__SSE4_1__");
773     LLVM_FALLTHROUGH;
774   case SSSE3:
775     Builder.defineMacro("__SSSE3__");
776     LLVM_FALLTHROUGH;
777   case SSE3:
778     Builder.defineMacro("__SSE3__");
779     LLVM_FALLTHROUGH;
780   case SSE2:
781     Builder.defineMacro("__SSE2__");
782     Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied.
783     LLVM_FALLTHROUGH;
784   case SSE1:
785     Builder.defineMacro("__SSE__");
786     Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied.
787     LLVM_FALLTHROUGH;
788   case NoSSE:
789     break;
790   }
791 
792   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
793     switch (SSELevel) {
794     case AVX512F:
795     case AVX2:
796     case AVX:
797     case SSE42:
798     case SSE41:
799     case SSSE3:
800     case SSE3:
801     case SSE2:
802       Builder.defineMacro("_M_IX86_FP", Twine(2));
803       break;
804     case SSE1:
805       Builder.defineMacro("_M_IX86_FP", Twine(1));
806       break;
807     default:
808       Builder.defineMacro("_M_IX86_FP", Twine(0));
809       break;
810     }
811   }
812 
813   // Each case falls through to the previous one here.
814   switch (MMX3DNowLevel) {
815   case AMD3DNowAthlon:
816     Builder.defineMacro("__3dNOW_A__");
817     LLVM_FALLTHROUGH;
818   case AMD3DNow:
819     Builder.defineMacro("__3dNOW__");
820     LLVM_FALLTHROUGH;
821   case MMX:
822     Builder.defineMacro("__MMX__");
823     LLVM_FALLTHROUGH;
824   case NoMMX3DNow:
825     break;
826   }
827 
828   if (CPU >= CK_i486 || CPU == CK_None) {
829     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
830     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
831     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
832   }
833   if (HasCX8)
834     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
835   if (HasCX16 && getTriple().getArch() == llvm::Triple::x86_64)
836     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
837 
838   if (HasFloat128)
839     Builder.defineMacro("__SIZEOF_FLOAT128__", "16");
840 }
841 
isValidFeatureName(StringRef Name) const842 bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
843   return llvm::StringSwitch<bool>(Name)
844       .Case("3dnow", true)
845       .Case("3dnowa", true)
846       .Case("adx", true)
847       .Case("aes", true)
848       .Case("amx-bf16", true)
849       .Case("amx-int8", true)
850       .Case("amx-tile", true)
851       .Case("avx", true)
852       .Case("avx2", true)
853       .Case("avx512f", true)
854       .Case("avx512cd", true)
855       .Case("avx512vpopcntdq", true)
856       .Case("avx512vnni", true)
857       .Case("avx512bf16", true)
858       .Case("avx512er", true)
859       .Case("avx512pf", true)
860       .Case("avx512dq", true)
861       .Case("avx512bitalg", true)
862       .Case("avx512bw", true)
863       .Case("avx512vl", true)
864       .Case("avx512vbmi", true)
865       .Case("avx512vbmi2", true)
866       .Case("avx512ifma", true)
867       .Case("avx512vp2intersect", true)
868       .Case("avxvnni", true)
869       .Case("bmi", true)
870       .Case("bmi2", true)
871       .Case("cldemote", true)
872       .Case("clflushopt", true)
873       .Case("clwb", true)
874       .Case("clzero", true)
875       .Case("cx16", true)
876       .Case("enqcmd", true)
877       .Case("f16c", true)
878       .Case("fma", true)
879       .Case("fma4", true)
880       .Case("fsgsbase", true)
881       .Case("fxsr", true)
882       .Case("general-regs-only", true)
883       .Case("gfni", true)
884       .Case("hreset", true)
885       .Case("invpcid", true)
886       .Case("kl", true)
887       .Case("widekl", true)
888       .Case("lwp", true)
889       .Case("lzcnt", true)
890       .Case("mmx", true)
891       .Case("movbe", true)
892       .Case("movdiri", true)
893       .Case("movdir64b", true)
894       .Case("mwaitx", true)
895       .Case("pclmul", true)
896       .Case("pconfig", true)
897       .Case("pku", true)
898       .Case("popcnt", true)
899       .Case("prefetchwt1", true)
900       .Case("prfchw", true)
901       .Case("ptwrite", true)
902       .Case("rdpid", true)
903       .Case("rdrnd", true)
904       .Case("rdseed", true)
905       .Case("rtm", true)
906       .Case("sahf", true)
907       .Case("serialize", true)
908       .Case("sgx", true)
909       .Case("sha", true)
910       .Case("shstk", true)
911       .Case("sse", true)
912       .Case("sse2", true)
913       .Case("sse3", true)
914       .Case("ssse3", true)
915       .Case("sse4", true)
916       .Case("sse4.1", true)
917       .Case("sse4.2", true)
918       .Case("sse4a", true)
919       .Case("tbm", true)
920       .Case("tsxldtrk", true)
921       .Case("uintr", true)
922       .Case("vaes", true)
923       .Case("vpclmulqdq", true)
924       .Case("wbnoinvd", true)
925       .Case("waitpkg", true)
926       .Case("x87", true)
927       .Case("xop", true)
928       .Case("xsave", true)
929       .Case("xsavec", true)
930       .Case("xsaves", true)
931       .Case("xsaveopt", true)
932       .Default(false);
933 }
934 
hasFeature(StringRef Feature) const935 bool X86TargetInfo::hasFeature(StringRef Feature) const {
936   return llvm::StringSwitch<bool>(Feature)
937       .Case("adx", HasADX)
938       .Case("aes", HasAES)
939       .Case("amx-bf16", HasAMXBF16)
940       .Case("amx-int8", HasAMXINT8)
941       .Case("amx-tile", HasAMXTILE)
942       .Case("avxvnni", HasAVXVNNI)
943       .Case("avx", SSELevel >= AVX)
944       .Case("avx2", SSELevel >= AVX2)
945       .Case("avx512f", SSELevel >= AVX512F)
946       .Case("avx512cd", HasAVX512CD)
947       .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ)
948       .Case("avx512vnni", HasAVX512VNNI)
949       .Case("avx512bf16", HasAVX512BF16)
950       .Case("avx512er", HasAVX512ER)
951       .Case("avx512pf", HasAVX512PF)
952       .Case("avx512dq", HasAVX512DQ)
953       .Case("avx512bitalg", HasAVX512BITALG)
954       .Case("avx512bw", HasAVX512BW)
955       .Case("avx512vl", HasAVX512VL)
956       .Case("avx512vbmi", HasAVX512VBMI)
957       .Case("avx512vbmi2", HasAVX512VBMI2)
958       .Case("avx512ifma", HasAVX512IFMA)
959       .Case("avx512vp2intersect", HasAVX512VP2INTERSECT)
960       .Case("bmi", HasBMI)
961       .Case("bmi2", HasBMI2)
962       .Case("cldemote", HasCLDEMOTE)
963       .Case("clflushopt", HasCLFLUSHOPT)
964       .Case("clwb", HasCLWB)
965       .Case("clzero", HasCLZERO)
966       .Case("cx8", HasCX8)
967       .Case("cx16", HasCX16)
968       .Case("enqcmd", HasENQCMD)
969       .Case("f16c", HasF16C)
970       .Case("fma", HasFMA)
971       .Case("fma4", XOPLevel >= FMA4)
972       .Case("fsgsbase", HasFSGSBASE)
973       .Case("fxsr", HasFXSR)
974       .Case("gfni", HasGFNI)
975       .Case("hreset", HasHRESET)
976       .Case("invpcid", HasINVPCID)
977       .Case("kl", HasKL)
978       .Case("widekl", HasWIDEKL)
979       .Case("lwp", HasLWP)
980       .Case("lzcnt", HasLZCNT)
981       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
982       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
983       .Case("mmx", MMX3DNowLevel >= MMX)
984       .Case("movbe", HasMOVBE)
985       .Case("movdiri", HasMOVDIRI)
986       .Case("movdir64b", HasMOVDIR64B)
987       .Case("mwaitx", HasMWAITX)
988       .Case("pclmul", HasPCLMUL)
989       .Case("pconfig", HasPCONFIG)
990       .Case("pku", HasPKU)
991       .Case("popcnt", HasPOPCNT)
992       .Case("prefetchwt1", HasPREFETCHWT1)
993       .Case("prfchw", HasPRFCHW)
994       .Case("ptwrite", HasPTWRITE)
995       .Case("rdpid", HasRDPID)
996       .Case("rdrnd", HasRDRND)
997       .Case("rdseed", HasRDSEED)
998       .Case("retpoline-external-thunk", HasRetpolineExternalThunk)
999       .Case("rtm", HasRTM)
1000       .Case("sahf", HasLAHFSAHF)
1001       .Case("serialize", HasSERIALIZE)
1002       .Case("sgx", HasSGX)
1003       .Case("sha", HasSHA)
1004       .Case("shstk", HasSHSTK)
1005       .Case("sse", SSELevel >= SSE1)
1006       .Case("sse2", SSELevel >= SSE2)
1007       .Case("sse3", SSELevel >= SSE3)
1008       .Case("ssse3", SSELevel >= SSSE3)
1009       .Case("sse4.1", SSELevel >= SSE41)
1010       .Case("sse4.2", SSELevel >= SSE42)
1011       .Case("sse4a", XOPLevel >= SSE4A)
1012       .Case("tbm", HasTBM)
1013       .Case("tsxldtrk", HasTSXLDTRK)
1014       .Case("uintr", HasUINTR)
1015       .Case("vaes", HasVAES)
1016       .Case("vpclmulqdq", HasVPCLMULQDQ)
1017       .Case("wbnoinvd", HasWBNOINVD)
1018       .Case("waitpkg", HasWAITPKG)
1019       .Case("x86", true)
1020       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
1021       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
1022       .Case("xop", XOPLevel >= XOP)
1023       .Case("xsave", HasXSAVE)
1024       .Case("xsavec", HasXSAVEC)
1025       .Case("xsaves", HasXSAVES)
1026       .Case("xsaveopt", HasXSAVEOPT)
1027       .Default(false);
1028 }
1029 
1030 // We can't use a generic validation scheme for the features accepted here
1031 // versus subtarget features accepted in the target attribute because the
1032 // bitfield structure that's initialized in the runtime only supports the
1033 // below currently rather than the full range of subtarget features. (See
1034 // X86TargetInfo::hasFeature for a somewhat comprehensive list).
validateCpuSupports(StringRef FeatureStr) const1035 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const {
1036   return llvm::StringSwitch<bool>(FeatureStr)
1037 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, true)
1038 #include "llvm/Support/X86TargetParser.def"
1039       .Default(false);
1040 }
1041 
getFeature(StringRef Name)1042 static llvm::X86::ProcessorFeatures getFeature(StringRef Name) {
1043   return llvm::StringSwitch<llvm::X86::ProcessorFeatures>(Name)
1044 #define X86_FEATURE_COMPAT(ENUM, STR) .Case(STR, llvm::X86::FEATURE_##ENUM)
1045 #include "llvm/Support/X86TargetParser.def"
1046       ;
1047   // Note, this function should only be used after ensuring the value is
1048   // correct, so it asserts if the value is out of range.
1049 }
1050 
getFeaturePriority(llvm::X86::ProcessorFeatures Feat)1051 static unsigned getFeaturePriority(llvm::X86::ProcessorFeatures Feat) {
1052   enum class FeatPriority {
1053 #define FEATURE(FEAT) FEAT,
1054 #include "clang/Basic/X86Target.def"
1055   };
1056   switch (Feat) {
1057 #define FEATURE(FEAT)                                                          \
1058   case llvm::X86::FEAT:                                                        \
1059     return static_cast<unsigned>(FeatPriority::FEAT);
1060 #include "clang/Basic/X86Target.def"
1061   default:
1062     llvm_unreachable("No Feature Priority for non-CPUSupports Features");
1063   }
1064 }
1065 
multiVersionSortPriority(StringRef Name) const1066 unsigned X86TargetInfo::multiVersionSortPriority(StringRef Name) const {
1067   // Valid CPUs have a 'key feature' that compares just better than its key
1068   // feature.
1069   using namespace llvm::X86;
1070   CPUKind Kind = parseArchX86(Name);
1071   if (Kind != CK_None) {
1072     ProcessorFeatures KeyFeature = getKeyFeature(Kind);
1073     return (getFeaturePriority(KeyFeature) << 1) + 1;
1074   }
1075 
1076   // Now we know we have a feature, so get its priority and shift it a few so
1077   // that we have sufficient room for the CPUs (above).
1078   return getFeaturePriority(getFeature(Name)) << 1;
1079 }
1080 
validateCPUSpecificCPUDispatch(StringRef Name) const1081 bool X86TargetInfo::validateCPUSpecificCPUDispatch(StringRef Name) const {
1082   return llvm::StringSwitch<bool>(Name)
1083 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, true)
1084 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, true)
1085 #include "clang/Basic/X86Target.def"
1086       .Default(false);
1087 }
1088 
CPUSpecificCPUDispatchNameDealias(StringRef Name)1089 static StringRef CPUSpecificCPUDispatchNameDealias(StringRef Name) {
1090   return llvm::StringSwitch<StringRef>(Name)
1091 #define CPU_SPECIFIC_ALIAS(NEW_NAME, NAME) .Case(NEW_NAME, NAME)
1092 #include "clang/Basic/X86Target.def"
1093       .Default(Name);
1094 }
1095 
CPUSpecificManglingCharacter(StringRef Name) const1096 char X86TargetInfo::CPUSpecificManglingCharacter(StringRef Name) const {
1097   return llvm::StringSwitch<char>(CPUSpecificCPUDispatchNameDealias(Name))
1098 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, MANGLING)
1099 #include "clang/Basic/X86Target.def"
1100       .Default(0);
1101 }
1102 
getCPUSpecificCPUDispatchFeatures(StringRef Name,llvm::SmallVectorImpl<StringRef> & Features) const1103 void X86TargetInfo::getCPUSpecificCPUDispatchFeatures(
1104     StringRef Name, llvm::SmallVectorImpl<StringRef> &Features) const {
1105   StringRef WholeList =
1106       llvm::StringSwitch<StringRef>(CPUSpecificCPUDispatchNameDealias(Name))
1107 #define CPU_SPECIFIC(NAME, MANGLING, FEATURES) .Case(NAME, FEATURES)
1108 #include "clang/Basic/X86Target.def"
1109           .Default("");
1110   WholeList.split(Features, ',', /*MaxSplit=*/-1, /*KeepEmpty=*/false);
1111 }
1112 
1113 // We can't use a generic validation scheme for the cpus accepted here
1114 // versus subtarget cpus accepted in the target attribute because the
1115 // variables intitialized by the runtime only support the below currently
1116 // rather than the full range of cpus.
validateCpuIs(StringRef FeatureStr) const1117 bool X86TargetInfo::validateCpuIs(StringRef FeatureStr) const {
1118   return llvm::StringSwitch<bool>(FeatureStr)
1119 #define X86_VENDOR(ENUM, STRING) .Case(STRING, true)
1120 #define X86_CPU_TYPE_ALIAS(ENUM, ALIAS) .Case(ALIAS, true)
1121 #define X86_CPU_TYPE(ENUM, STR) .Case(STR, true)
1122 #define X86_CPU_SUBTYPE(ENUM, STR) .Case(STR, true)
1123 #include "llvm/Support/X86TargetParser.def"
1124       .Default(false);
1125 }
1126 
matchAsmCCConstraint(const char * & Name)1127 static unsigned matchAsmCCConstraint(const char *&Name) {
1128   auto RV = llvm::StringSwitch<unsigned>(Name)
1129                 .Case("@cca", 4)
1130                 .Case("@ccae", 5)
1131                 .Case("@ccb", 4)
1132                 .Case("@ccbe", 5)
1133                 .Case("@ccc", 4)
1134                 .Case("@cce", 4)
1135                 .Case("@ccz", 4)
1136                 .Case("@ccg", 4)
1137                 .Case("@ccge", 5)
1138                 .Case("@ccl", 4)
1139                 .Case("@ccle", 5)
1140                 .Case("@ccna", 5)
1141                 .Case("@ccnae", 6)
1142                 .Case("@ccnb", 5)
1143                 .Case("@ccnbe", 6)
1144                 .Case("@ccnc", 5)
1145                 .Case("@ccne", 5)
1146                 .Case("@ccnz", 5)
1147                 .Case("@ccng", 5)
1148                 .Case("@ccnge", 6)
1149                 .Case("@ccnl", 5)
1150                 .Case("@ccnle", 6)
1151                 .Case("@ccno", 5)
1152                 .Case("@ccnp", 5)
1153                 .Case("@ccns", 5)
1154                 .Case("@cco", 4)
1155                 .Case("@ccp", 4)
1156                 .Case("@ccs", 4)
1157                 .Default(0);
1158   return RV;
1159 }
1160 
validateAsmConstraint(const char * & Name,TargetInfo::ConstraintInfo & Info) const1161 bool X86TargetInfo::validateAsmConstraint(
1162     const char *&Name, TargetInfo::ConstraintInfo &Info) const {
1163   switch (*Name) {
1164   default:
1165     return false;
1166   // Constant constraints.
1167   case 'e': // 32-bit signed integer constant for use with sign-extending x86_64
1168             // instructions.
1169   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
1170             // x86_64 instructions.
1171   case 's':
1172     Info.setRequiresImmediate();
1173     return true;
1174   case 'I':
1175     Info.setRequiresImmediate(0, 31);
1176     return true;
1177   case 'J':
1178     Info.setRequiresImmediate(0, 63);
1179     return true;
1180   case 'K':
1181     Info.setRequiresImmediate(-128, 127);
1182     return true;
1183   case 'L':
1184     Info.setRequiresImmediate({int(0xff), int(0xffff), int(0xffffffff)});
1185     return true;
1186   case 'M':
1187     Info.setRequiresImmediate(0, 3);
1188     return true;
1189   case 'N':
1190     Info.setRequiresImmediate(0, 255);
1191     return true;
1192   case 'O':
1193     Info.setRequiresImmediate(0, 127);
1194     return true;
1195   // Register constraints.
1196   case 'Y': // 'Y' is the first character for several 2-character constraints.
1197     // Shift the pointer to the second character of the constraint.
1198     Name++;
1199     switch (*Name) {
1200     default:
1201       return false;
1202     case 'z': // First SSE register.
1203     case '2':
1204     case 't': // Any SSE register, when SSE2 is enabled.
1205     case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
1206     case 'm': // Any MMX register, when inter-unit moves enabled.
1207     case 'k': // AVX512 arch mask registers: k1-k7.
1208       Info.setAllowsRegister();
1209       return true;
1210     }
1211   case 'f': // Any x87 floating point stack register.
1212     // Constraint 'f' cannot be used for output operands.
1213     if (Info.ConstraintStr[0] == '=')
1214       return false;
1215     Info.setAllowsRegister();
1216     return true;
1217   case 'a': // eax.
1218   case 'b': // ebx.
1219   case 'c': // ecx.
1220   case 'd': // edx.
1221   case 'S': // esi.
1222   case 'D': // edi.
1223   case 'A': // edx:eax.
1224   case 't': // Top of floating point stack.
1225   case 'u': // Second from top of floating point stack.
1226   case 'q': // Any register accessible as [r]l: a, b, c, and d.
1227   case 'y': // Any MMX register.
1228   case 'v': // Any {X,Y,Z}MM register (Arch & context dependent)
1229   case 'x': // Any SSE register.
1230   case 'k': // Any AVX512 mask register (same as Yk, additionally allows k0
1231             // for intermideate k reg operations).
1232   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
1233   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
1234   case 'l': // "Index" registers: any general register that can be used as an
1235             // index in a base+index memory access.
1236     Info.setAllowsRegister();
1237     return true;
1238   // Floating point constant constraints.
1239   case 'C': // SSE floating point constant.
1240   case 'G': // x87 floating point constant.
1241     return true;
1242   case '@':
1243     // CC condition changes.
1244     if (auto Len = matchAsmCCConstraint(Name)) {
1245       Name += Len - 1;
1246       Info.setAllowsRegister();
1247       return true;
1248     }
1249     return false;
1250   }
1251 }
1252 
1253 // Below is based on the following information:
1254 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1255 // |           Processor Name           | Cache Line Size (Bytes) |                                                                            Source                                                                            |
1256 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
1257 // | i386                               |                      64 | https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf                                          |
1258 // | i486                               |                      16 | "four doublewords" (doubleword = 32 bits, 4 bits * 32 bits = 16 bytes) https://en.wikichip.org/w/images/d/d3/i486_MICROPROCESSOR_HARDWARE_REFERENCE_MANUAL_%281990%29.pdf and http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.126.4216&rep=rep1&type=pdf (page 29) |
1259 // | i586/Pentium MMX                   |                      32 | https://www.7-cpu.com/cpu/P-MMX.html                                                                                                                         |
1260 // | i686/Pentium                       |                      32 | https://www.7-cpu.com/cpu/P6.html                                                                                                                            |
1261 // | Netburst/Pentium4                  |                      64 | https://www.7-cpu.com/cpu/P4-180.html                                                                                                                        |
1262 // | Atom                               |                      64 | https://www.7-cpu.com/cpu/Atom.html                                                                                                                          |
1263 // | Westmere                           |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/sandy_bridge_(client) "Cache Architecture"                                                             |
1264 // | Sandy Bridge                       |                      64 | https://en.wikipedia.org/wiki/Sandy_Bridge and https://www.7-cpu.com/cpu/SandyBridge.html                                                                    |
1265 // | Ivy Bridge                         |                      64 | https://blog.stuffedcow.net/2013/01/ivb-cache-replacement/ and https://www.7-cpu.com/cpu/IvyBridge.html                                                      |
1266 // | Haswell                            |                      64 | https://www.7-cpu.com/cpu/Haswell.html                                                                                                                       |
1267 // | Boadwell                           |                      64 | https://www.7-cpu.com/cpu/Broadwell.html                                                                                                                     |
1268 // | Skylake (including skylake-avx512) |                      64 | https://www.nas.nasa.gov/hecc/support/kb/skylake-processors_550.html "Cache Hierarchy"                                                                       |
1269 // | Cascade Lake                       |                      64 | https://www.nas.nasa.gov/hecc/support/kb/cascade-lake-processors_579.html "Cache Hierarchy"                                                                  |
1270 // | Skylake                            |                      64 | https://en.wikichip.org/wiki/intel/microarchitectures/kaby_lake "Memory Hierarchy"                                                                           |
1271 // | Ice Lake                           |                      64 | https://www.7-cpu.com/cpu/Ice_Lake.html                                                                                                                      |
1272 // | Knights Landing                    |                      64 | https://software.intel.com/en-us/articles/intel-xeon-phi-processor-7200-family-memory-management-optimizations "The Intel® Xeon Phi™ Processor Architecture" |
1273 // | Knights Mill                       |                      64 | https://software.intel.com/sites/default/files/managed/9e/bc/64-ia-32-architectures-optimization-manual.pdf?countrylabel=Colombia "2.5.5.2 L1 DCache "       |
1274 // +------------------------------------+-------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
getCPUCacheLineSize() const1275 Optional<unsigned> X86TargetInfo::getCPUCacheLineSize() const {
1276   using namespace llvm::X86;
1277   switch (CPU) {
1278     // i386
1279     case CK_i386:
1280     // i486
1281     case CK_i486:
1282     case CK_WinChipC6:
1283     case CK_WinChip2:
1284     case CK_C3:
1285     // Lakemont
1286     case CK_Lakemont:
1287       return 16;
1288 
1289     // i586
1290     case CK_i586:
1291     case CK_Pentium:
1292     case CK_PentiumMMX:
1293     // i686
1294     case CK_PentiumPro:
1295     case CK_i686:
1296     case CK_Pentium2:
1297     case CK_Pentium3:
1298     case CK_PentiumM:
1299     case CK_C3_2:
1300     // K6
1301     case CK_K6:
1302     case CK_K6_2:
1303     case CK_K6_3:
1304     // Geode
1305     case CK_Geode:
1306       return 32;
1307 
1308     // Netburst
1309     case CK_Pentium4:
1310     case CK_Prescott:
1311     case CK_Nocona:
1312     // Atom
1313     case CK_Bonnell:
1314     case CK_Silvermont:
1315     case CK_Goldmont:
1316     case CK_GoldmontPlus:
1317     case CK_Tremont:
1318 
1319     case CK_Westmere:
1320     case CK_SandyBridge:
1321     case CK_IvyBridge:
1322     case CK_Haswell:
1323     case CK_Broadwell:
1324     case CK_SkylakeClient:
1325     case CK_SkylakeServer:
1326     case CK_Cascadelake:
1327     case CK_Nehalem:
1328     case CK_Cooperlake:
1329     case CK_Cannonlake:
1330     case CK_Tigerlake:
1331     case CK_SapphireRapids:
1332     case CK_IcelakeClient:
1333     case CK_Rocketlake:
1334     case CK_IcelakeServer:
1335     case CK_Alderlake:
1336     case CK_KNL:
1337     case CK_KNM:
1338     // K7
1339     case CK_Athlon:
1340     case CK_AthlonXP:
1341     // K8
1342     case CK_K8:
1343     case CK_K8SSE3:
1344     case CK_AMDFAM10:
1345     // Bobcat
1346     case CK_BTVER1:
1347     case CK_BTVER2:
1348     // Bulldozer
1349     case CK_BDVER1:
1350     case CK_BDVER2:
1351     case CK_BDVER3:
1352     case CK_BDVER4:
1353     // Zen
1354     case CK_ZNVER1:
1355     case CK_ZNVER2:
1356     case CK_ZNVER3:
1357     // Deprecated
1358     case CK_x86_64:
1359     case CK_x86_64_v2:
1360     case CK_x86_64_v3:
1361     case CK_x86_64_v4:
1362     case CK_Yonah:
1363     case CK_Penryn:
1364     case CK_Core2:
1365       return 64;
1366 
1367     // The following currently have unknown cache line sizes (but they are probably all 64):
1368     // Core
1369     case CK_None:
1370       return None;
1371   }
1372   llvm_unreachable("Unknown CPU kind");
1373 }
1374 
validateOutputSize(const llvm::StringMap<bool> & FeatureMap,StringRef Constraint,unsigned Size) const1375 bool X86TargetInfo::validateOutputSize(const llvm::StringMap<bool> &FeatureMap,
1376                                        StringRef Constraint,
1377                                        unsigned Size) const {
1378   // Strip off constraint modifiers.
1379   while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
1380     Constraint = Constraint.substr(1);
1381 
1382   return validateOperandSize(FeatureMap, Constraint, Size);
1383 }
1384 
validateInputSize(const llvm::StringMap<bool> & FeatureMap,StringRef Constraint,unsigned Size) const1385 bool X86TargetInfo::validateInputSize(const llvm::StringMap<bool> &FeatureMap,
1386                                       StringRef Constraint,
1387                                       unsigned Size) const {
1388   return validateOperandSize(FeatureMap, Constraint, Size);
1389 }
1390 
validateOperandSize(const llvm::StringMap<bool> & FeatureMap,StringRef Constraint,unsigned Size) const1391 bool X86TargetInfo::validateOperandSize(const llvm::StringMap<bool> &FeatureMap,
1392                                         StringRef Constraint,
1393                                         unsigned Size) const {
1394   switch (Constraint[0]) {
1395   default:
1396     break;
1397   case 'k':
1398   // Registers k0-k7 (AVX512) size limit is 64 bit.
1399   case 'y':
1400     return Size <= 64;
1401   case 'f':
1402   case 't':
1403   case 'u':
1404     return Size <= 128;
1405   case 'Y':
1406     // 'Y' is the first character for several 2-character constraints.
1407     switch (Constraint[1]) {
1408     default:
1409       return false;
1410     case 'm':
1411       // 'Ym' is synonymous with 'y'.
1412     case 'k':
1413       return Size <= 64;
1414     case 'z':
1415       // XMM0/YMM/ZMM0
1416       if (hasFeatureEnabled(FeatureMap, "avx512f"))
1417         // ZMM0 can be used if target supports AVX512F.
1418         return Size <= 512U;
1419       else if (hasFeatureEnabled(FeatureMap, "avx"))
1420         // YMM0 can be used if target supports AVX.
1421         return Size <= 256U;
1422       else if (hasFeatureEnabled(FeatureMap, "sse"))
1423         return Size <= 128U;
1424       return false;
1425     case 'i':
1426     case 't':
1427     case '2':
1428       // 'Yi','Yt','Y2' are synonymous with 'x' when SSE2 is enabled.
1429       if (SSELevel < SSE2)
1430         return false;
1431       break;
1432     }
1433     break;
1434   case 'v':
1435   case 'x':
1436     if (hasFeatureEnabled(FeatureMap, "avx512f"))
1437       // 512-bit zmm registers can be used if target supports AVX512F.
1438       return Size <= 512U;
1439     else if (hasFeatureEnabled(FeatureMap, "avx"))
1440       // 256-bit ymm registers can be used if target supports AVX.
1441       return Size <= 256U;
1442     return Size <= 128U;
1443 
1444   }
1445 
1446   return true;
1447 }
1448 
convertConstraint(const char * & Constraint) const1449 std::string X86TargetInfo::convertConstraint(const char *&Constraint) const {
1450   switch (*Constraint) {
1451   case '@':
1452     if (auto Len = matchAsmCCConstraint(Constraint)) {
1453       std::string Converted = "{" + std::string(Constraint, Len) + "}";
1454       Constraint += Len - 1;
1455       return Converted;
1456     }
1457     return std::string(1, *Constraint);
1458   case 'a':
1459     return std::string("{ax}");
1460   case 'b':
1461     return std::string("{bx}");
1462   case 'c':
1463     return std::string("{cx}");
1464   case 'd':
1465     return std::string("{dx}");
1466   case 'S':
1467     return std::string("{si}");
1468   case 'D':
1469     return std::string("{di}");
1470   case 'p': // address
1471     return std::string("im");
1472   case 't': // top of floating point stack.
1473     return std::string("{st}");
1474   case 'u':                        // second from top of floating point stack.
1475     return std::string("{st(1)}"); // second from top of floating point stack.
1476   case 'Y':
1477     switch (Constraint[1]) {
1478     default:
1479       // Break from inner switch and fall through (copy single char),
1480       // continue parsing after copying the current constraint into
1481       // the return string.
1482       break;
1483     case 'k':
1484     case 'm':
1485     case 'i':
1486     case 't':
1487     case 'z':
1488     case '2':
1489       // "^" hints llvm that this is a 2 letter constraint.
1490       // "Constraint++" is used to promote the string iterator
1491       // to the next constraint.
1492       return std::string("^") + std::string(Constraint++, 2);
1493     }
1494     LLVM_FALLTHROUGH;
1495   default:
1496     return std::string(1, *Constraint);
1497   }
1498 }
1499 
fillValidCPUList(SmallVectorImpl<StringRef> & Values) const1500 void X86TargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
1501   bool Only64Bit = getTriple().getArch() != llvm::Triple::x86;
1502   llvm::X86::fillValidCPUArchList(Values, Only64Bit);
1503 }
1504 
fillValidTuneCPUList(SmallVectorImpl<StringRef> & Values) const1505 void X86TargetInfo::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values) const {
1506   llvm::X86::fillValidTuneCPUList(Values);
1507 }
1508 
getGCCRegNames() const1509 ArrayRef<const char *> X86TargetInfo::getGCCRegNames() const {
1510   return llvm::makeArrayRef(GCCRegNames);
1511 }
1512 
getGCCAddlRegNames() const1513 ArrayRef<TargetInfo::AddlRegName> X86TargetInfo::getGCCAddlRegNames() const {
1514   return llvm::makeArrayRef(AddlRegNames);
1515 }
1516 
getTargetBuiltins() const1517 ArrayRef<Builtin::Info> X86_32TargetInfo::getTargetBuiltins() const {
1518   return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin -
1519                                                 Builtin::FirstTSBuiltin + 1);
1520 }
1521 
getTargetBuiltins() const1522 ArrayRef<Builtin::Info> X86_64TargetInfo::getTargetBuiltins() const {
1523   return llvm::makeArrayRef(BuiltinInfoX86,
1524                             X86::LastTSBuiltin - Builtin::FirstTSBuiltin);
1525 }
1526