1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // REQUIRES: riscv-registered-target
3 // RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
4 
5 #include <riscv_vector.h>
6 
7 //
8 // CHECK-RV64-LABEL: @test_vfirst_m_b1(
9 // CHECK-RV64-NEXT:  entry:
10 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
11 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
12 //
test_vfirst_m_b1(vbool1_t op1,size_t vl)13 long test_vfirst_m_b1(vbool1_t op1, size_t vl) { return vfirst_m_b1(op1, vl); }
14 
15 //
16 // CHECK-RV64-LABEL: @test_vfirst_m_b2(
17 // CHECK-RV64-NEXT:  entry:
18 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
19 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
20 //
test_vfirst_m_b2(vbool2_t op1,size_t vl)21 long test_vfirst_m_b2(vbool2_t op1, size_t vl) { return vfirst_m_b2(op1, vl); }
22 
23 //
24 // CHECK-RV64-LABEL: @test_vfirst_m_b4(
25 // CHECK-RV64-NEXT:  entry:
26 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
27 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
28 //
test_vfirst_m_b4(vbool4_t op1,size_t vl)29 long test_vfirst_m_b4(vbool4_t op1, size_t vl) { return vfirst_m_b4(op1, vl); }
30 
31 //
32 // CHECK-RV64-LABEL: @test_vfirst_m_b8(
33 // CHECK-RV64-NEXT:  entry:
34 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
35 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
36 //
test_vfirst_m_b8(vbool8_t op1,size_t vl)37 long test_vfirst_m_b8(vbool8_t op1, size_t vl) { return vfirst_m_b8(op1, vl); }
38 
39 //
40 // CHECK-RV64-LABEL: @test_vfirst_m_b16(
41 // CHECK-RV64-NEXT:  entry:
42 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
43 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
44 //
test_vfirst_m_b16(vbool16_t op1,size_t vl)45 long test_vfirst_m_b16(vbool16_t op1, size_t vl) {
46   return vfirst_m_b16(op1, vl);
47 }
48 
49 //
50 // CHECK-RV64-LABEL: @test_vfirst_m_b32(
51 // CHECK-RV64-NEXT:  entry:
52 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
53 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
54 //
test_vfirst_m_b32(vbool32_t op1,size_t vl)55 long test_vfirst_m_b32(vbool32_t op1, size_t vl) {
56   return vfirst_m_b32(op1, vl);
57 }
58 
59 //
60 // CHECK-RV64-LABEL: @test_vfirst_m_b64(
61 // CHECK-RV64-NEXT:  entry:
62 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], i64 [[VL:%.*]])
63 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
64 //
test_vfirst_m_b64(vbool64_t op1,size_t vl)65 long test_vfirst_m_b64(vbool64_t op1, size_t vl) {
66   return vfirst_m_b64(op1, vl);
67 }
68 
69 //
70 // CHECK-RV64-LABEL: @test_vfirst_m_b1_m(
71 // CHECK-RV64-NEXT:  entry:
72 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.mask.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
73 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
74 //
test_vfirst_m_b1_m(vbool1_t mask,vbool1_t op1,size_t vl)75 long test_vfirst_m_b1_m(vbool1_t mask, vbool1_t op1, size_t vl) {
76   return vfirst_m_b1_m(mask, op1, vl);
77 }
78 
79 //
80 // CHECK-RV64-LABEL: @test_vfirst_m_b2_m(
81 // CHECK-RV64-NEXT:  entry:
82 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.mask.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
83 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
84 //
test_vfirst_m_b2_m(vbool2_t mask,vbool2_t op1,size_t vl)85 long test_vfirst_m_b2_m(vbool2_t mask, vbool2_t op1, size_t vl) {
86   return vfirst_m_b2_m(mask, op1, vl);
87 }
88 
89 //
90 // CHECK-RV64-LABEL: @test_vfirst_m_b4_m(
91 // CHECK-RV64-NEXT:  entry:
92 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.mask.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
93 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
94 //
test_vfirst_m_b4_m(vbool4_t mask,vbool4_t op1,size_t vl)95 long test_vfirst_m_b4_m(vbool4_t mask, vbool4_t op1, size_t vl) {
96   return vfirst_m_b4_m(mask, op1, vl);
97 }
98 
99 //
100 // CHECK-RV64-LABEL: @test_vfirst_m_b8_m(
101 // CHECK-RV64-NEXT:  entry:
102 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.mask.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
103 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
104 //
test_vfirst_m_b8_m(vbool8_t mask,vbool8_t op1,size_t vl)105 long test_vfirst_m_b8_m(vbool8_t mask, vbool8_t op1, size_t vl) {
106   return vfirst_m_b8_m(mask, op1, vl);
107 }
108 
109 //
110 // CHECK-RV64-LABEL: @test_vfirst_m_b16_m(
111 // CHECK-RV64-NEXT:  entry:
112 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.mask.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
113 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
114 //
test_vfirst_m_b16_m(vbool16_t mask,vbool16_t op1,size_t vl)115 long test_vfirst_m_b16_m(vbool16_t mask, vbool16_t op1, size_t vl) {
116   return vfirst_m_b16_m(mask, op1, vl);
117 }
118 
119 //
120 // CHECK-RV64-LABEL: @test_vfirst_m_b32_m(
121 // CHECK-RV64-NEXT:  entry:
122 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.mask.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
123 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
124 //
test_vfirst_m_b32_m(vbool32_t mask,vbool32_t op1,size_t vl)125 long test_vfirst_m_b32_m(vbool32_t mask, vbool32_t op1, size_t vl) {
126   return vfirst_m_b32_m(mask, op1, vl);
127 }
128 
129 //
130 // CHECK-RV64-LABEL: @test_vfirst_m_b64_m(
131 // CHECK-RV64-NEXT:  entry:
132 // CHECK-RV64-NEXT:    [[TMP0:%.*]] = call i64 @llvm.riscv.vfirst.mask.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]])
133 // CHECK-RV64-NEXT:    ret i64 [[TMP0]]
134 //
test_vfirst_m_b64_m(vbool64_t mask,vbool64_t op1,size_t vl)135 long test_vfirst_m_b64_m(vbool64_t mask, vbool64_t op1, size_t vl) {
136   return vfirst_m_b64_m(mask, op1, vl);
137 }
138