1 // RUN: %clang_cc1 -triple arm64-unknown-linux -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LINUX
2 // RUN: %clang_cc1 -triple aarch64-windows -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-WIN
3 // RUN: %clang_cc1 -triple arm64_32-apple-ios13 -disable-O0-optnone -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
4 #include <stdint.h>
5
f0(void * a,void * b)6 void f0(void *a, void *b) {
7 __clear_cache(a,b);
8 // CHECK: call {{.*}} @__clear_cache
9 }
10
tp(void)11 void *tp (void) {
12 return __builtin_thread_pointer ();
13 // CHECK-LINUX: call {{.*}} @llvm.thread.pointer()
14 }
15
16 // CHECK: call {{.*}} @llvm.bitreverse.i32(i32 %a)
rbit(unsigned a)17 unsigned rbit(unsigned a) {
18 return __builtin_arm_rbit(a);
19 }
20
21 // CHECK-WIN: [[A64:%[^ ]+]] = zext i32 %a to i64
22 // CHECK-WIN: call i64 @llvm.bitreverse.i64(i64 [[A64]])
23 // CHECK-LINUX: call i64 @llvm.bitreverse.i64(i64 %a)
rbitl(unsigned long a)24 unsigned long rbitl(unsigned long a) {
25 return __builtin_arm_rbit64(a);
26 }
27
28 // CHECK: call {{.*}} @llvm.bitreverse.i64(i64 %a)
rbit64(uint64_t a)29 uint64_t rbit64(uint64_t a) {
30 return __builtin_arm_rbit64(a);
31 }
32
hints()33 void hints() {
34 __builtin_arm_nop(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 0)
35 __builtin_arm_yield(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 1)
36 __builtin_arm_wfe(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 2)
37 __builtin_arm_wfi(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 3)
38 __builtin_arm_sev(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 4)
39 __builtin_arm_sevl(); //CHECK: call {{.*}} @llvm.aarch64.hint(i32 5)
40 }
41
barriers()42 void barriers() {
43 __builtin_arm_dmb(1); //CHECK: call {{.*}} @llvm.aarch64.dmb(i32 1)
44 __builtin_arm_dsb(2); //CHECK: call {{.*}} @llvm.aarch64.dsb(i32 2)
45 __builtin_arm_isb(3); //CHECK: call {{.*}} @llvm.aarch64.isb(i32 3)
46 }
47
prefetch()48 void prefetch() {
49 __builtin_arm_prefetch(0, 1, 2, 0, 1); // pstl3keep
50 // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* null, i32 1, i32 1, i32 1)
51
52 __builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1keep
53 // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* null, i32 0, i32 0, i32 1)
54
55 __builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1strm
56 // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* null, i32 0, i32 0, i32 1)
57
58 __builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep
59 // CHECK: call {{.*}} @llvm.prefetch.p0i8(i8* null, i32 0, i32 3, i32 0)
60 }
61
jcvt(double v)62 int32_t jcvt(double v) {
63 //CHECK-LABEL: @jcvt(
64 //CHECK: call i32 @llvm.aarch64.fjcvtzs
65 return __builtin_arm_jcvt(v);
66 }
67
68 __typeof__(__builtin_arm_rsr("1:2:3:4:5")) rsr(void);
69
rsr()70 uint32_t rsr() {
71 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])
72 // CHECK-NEXT: trunc i64 [[V0]] to i32
73 return __builtin_arm_rsr("1:2:3:4:5");
74 }
75
76 __typeof__(__builtin_arm_rsr64("1:2:3:4:5")) rsr64(void);
77
rsr64(void)78 uint64_t rsr64(void) {
79 // CHECK: call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])
80 return __builtin_arm_rsr64("1:2:3:4:5");
81 }
82
rsrp()83 void *rsrp() {
84 // CHECK: [[V0:[%A-Za-z0-9.]+]] = call i64 @llvm.read_volatile_register.i64(metadata ![[M0:[0-9]]])
85 // CHECK-NEXT: inttoptr i64 [[V0]] to i8*
86 return __builtin_arm_rsrp("1:2:3:4:5");
87 }
88
89 __typeof__(__builtin_arm_wsr("1:2:3:4:5", 0)) wsr(unsigned);
90
wsr(unsigned v)91 void wsr(unsigned v) {
92 // CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64
93 // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])
94 __builtin_arm_wsr("1:2:3:4:5", v);
95 }
96
97 __typeof__(__builtin_arm_wsr64("1:2:3:4:5", 0)) wsr64(uint64_t);
98
wsr64(uint64_t v)99 void wsr64(uint64_t v) {
100 // CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v)
101 __builtin_arm_wsr64("1:2:3:4:5", v);
102 }
103
wsrp(void * v)104 void wsrp(void *v) {
105 // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i64
106 // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])
107 __builtin_arm_wsrp("1:2:3:4:5", v);
108 }
109
cls(uint32_t v)110 unsigned int cls(uint32_t v) {
111 // CHECK: call i32 @llvm.aarch64.cls(i32 %v)
112 return __builtin_arm_cls(v);
113 }
114
clsl(unsigned long v)115 unsigned int clsl(unsigned long v) {
116 // CHECK-WIN: [[V64:%[^ ]+]] = zext i32 %v to i64
117 // CHECK-WIN: call i32 @llvm.aarch64.cls64(i64 [[V64]]
118 // CHECK-LINUX: call i32 @llvm.aarch64.cls64(i64 %v)
119 return __builtin_arm_cls64(v);
120 }
121
clsll(uint64_t v)122 unsigned int clsll(uint64_t v) {
123 // CHECK: call i32 @llvm.aarch64.cls64(i64 %v)
124 return __builtin_arm_cls64(v);
125 }
126
127 // CHECK-LABEL: @rndr(
128 // CHECK-NEXT: entry:
129 // CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndr()
130 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0
131 // CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
132 // CHECK-NEXT: store i64 [[TMP1]], i64* [[__ADDR:%.*]], align 8
133 // CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
134 // CHECK-NEXT: ret i32 [[TMP3]]
135 //
rndr(uint64_t * __addr)136 int rndr(uint64_t *__addr) {
137 return __builtin_arm_rndr(__addr);
138 }
139
140 // CHECK-LABEL: @rndrrs(
141 // CHECK-NEXT: entry:
142 // CHECK-NEXT: [[TMP0:%.*]] = call { i64, i1 } @llvm.aarch64.rndrrs()
143 // CHECK-NEXT: [[TMP1:%.*]] = extractvalue { i64, i1 } [[TMP0]], 0
144 // CHECK-NEXT: [[TMP2:%.*]] = extractvalue { i64, i1 } [[TMP0]], 1
145 // CHECK-NEXT: store i64 [[TMP1]], i64* [[__ADDR:%.*]], align 8
146 // CHECK-NEXT: [[TMP3:%.*]] = zext i1 [[TMP2]] to i32
147 // CHECK-NEXT: ret i32 [[TMP3]]
148 //
rndrrs(uint64_t * __addr)149 int rndrrs(uint64_t *__addr) {
150 return __builtin_arm_rndrrs(__addr);
151 }
152
153 // CHECK: ![[M0]] = !{!"1:2:3:4:5"}
154