1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
2 // RUN: %clang_cc1 -ffixed-point -triple x86_64-unknown-linux-gnu -S -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,SIGNED
3 // RUN: %clang_cc1 -ffixed-point -triple x86_64-unknown-linux-gnu -S -emit-llvm %s -o - -fpadding-on-unsigned-fixed-point | FileCheck %s --check-prefixes=CHECK,UNSIGNED
4
5 short _Accum sa;
6 _Accum a, a2;
7 long _Accum la;
8
9 unsigned short _Accum usa;
10 unsigned _Accum ua;
11 unsigned long _Accum ula;
12
13 short _Fract sf;
14 _Fract f;
15 long _Fract lf;
16 unsigned _Fract uf;
17
18 _Sat short _Accum sat_sa;
19 _Sat _Accum sat_a;
20 _Sat long _Accum sat_la;
21
22 _Sat unsigned short _Accum sat_usa;
23 _Sat unsigned _Accum sat_ua;
24 _Sat unsigned long _Accum sat_ula;
25
26 _Sat short _Fract sat_sf;
27 _Sat _Fract sat_f;
28 _Sat long _Fract sat_lf;
29 _Sat unsigned _Fract sat_uf;
30
31 short s;
32 int i;
33 unsigned int ui;
34
35 float fl;
36 double d;
37
38 // CHECK-LABEL: @fix_same1(
39 // CHECK-NEXT: entry:
40 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
41 // CHECK-NEXT: store i32 [[TMP0]], i32* @a2, align 4
42 // CHECK-NEXT: ret void
43 //
fix_same1()44 void fix_same1() {
45 a2 = a;
46 }
47
48 // CHECK-LABEL: @fix_same2(
49 // CHECK-NEXT: entry:
50 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
51 // CHECK-NEXT: store i32 [[TMP0]], i32* @a2, align 4
52 // CHECK-NEXT: ret void
53 //
fix_same2()54 void fix_same2() {
55 a2 = (_Accum)a;
56 }
57
58
59 // CHECK-LABEL: @fix_castdown1(
60 // CHECK-NEXT: entry:
61 // CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @la, align 8
62 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i64 [[TMP0]], 16
63 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i64 [[DOWNSCALE]] to i32
64 // CHECK-NEXT: store i32 [[RESIZE]], i32* @a, align 4
65 // CHECK-NEXT: ret void
66 //
fix_castdown1()67 void fix_castdown1() {
68 a = la;
69 }
70
71 // CHECK-LABEL: @fix_castdown2(
72 // CHECK-NEXT: entry:
73 // CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @la, align 8
74 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i64 [[TMP0]], 16
75 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i64 [[DOWNSCALE]] to i32
76 // CHECK-NEXT: store i32 [[RESIZE]], i32* @a, align 4
77 // CHECK-NEXT: ret void
78 //
fix_castdown2()79 void fix_castdown2() {
80 a = (_Accum)la;
81 }
82
83 // CHECK-LABEL: @fix_castdown3(
84 // CHECK-NEXT: entry:
85 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
86 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP0]], 8
87 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[DOWNSCALE]] to i16
88 // CHECK-NEXT: store i16 [[RESIZE]], i16* @sa, align 2
89 // CHECK-NEXT: ret void
90 //
fix_castdown3()91 void fix_castdown3() {
92 sa = a;
93 }
94
95 // CHECK-LABEL: @fix_castdown4(
96 // CHECK-NEXT: entry:
97 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
98 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP0]], 8
99 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[DOWNSCALE]] to i16
100 // CHECK-NEXT: store i16 [[RESIZE]], i16* @sa, align 2
101 // CHECK-NEXT: ret void
102 //
fix_castdown4()103 void fix_castdown4() {
104 sa = a;
105 }
106
107
108 // CHECK-LABEL: @fix_castup1(
109 // CHECK-NEXT: entry:
110 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @sa, align 2
111 // CHECK-NEXT: [[RESIZE:%.*]] = sext i16 [[TMP0]] to i32
112 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
113 // CHECK-NEXT: store i32 [[UPSCALE]], i32* @a, align 4
114 // CHECK-NEXT: ret void
115 //
fix_castup1()116 void fix_castup1() {
117 a = sa;
118 }
119
120 // CHECK-LABEL: @fix_castup2(
121 // CHECK-NEXT: entry:
122 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @sa, align 2
123 // CHECK-NEXT: [[RESIZE:%.*]] = sext i16 [[TMP0]] to i32
124 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
125 // CHECK-NEXT: store i32 [[UPSCALE]], i32* @a, align 4
126 // CHECK-NEXT: ret void
127 //
fix_castup2()128 void fix_castup2() {
129 a = (_Accum)sa;
130 }
131
132 // CHECK-LABEL: @fix_castup3(
133 // CHECK-NEXT: entry:
134 // CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @la, align 8
135 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i64 [[TMP0]], 16
136 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i64 [[DOWNSCALE]] to i32
137 // CHECK-NEXT: store i32 [[RESIZE]], i32* @a, align 4
138 // CHECK-NEXT: ret void
139 //
fix_castup3()140 void fix_castup3() {
141 a = la;
142 }
143
144 // CHECK-LABEL: @fix_castup4(
145 // CHECK-NEXT: entry:
146 // CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @la, align 8
147 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i64 [[TMP0]], 16
148 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i64 [[DOWNSCALE]] to i32
149 // CHECK-NEXT: store i32 [[RESIZE]], i32* @a, align 4
150 // CHECK-NEXT: ret void
151 //
fix_castup4()152 void fix_castup4() {
153 a = (long _Accum)la;
154 }
155
156
157 // SIGNED-LABEL: @fix_sign1(
158 // SIGNED-NEXT: entry:
159 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
160 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i32 [[TMP0]], 1
161 // SIGNED-NEXT: store i32 [[UPSCALE]], i32* @ua, align 4
162 // SIGNED-NEXT: ret void
163 //
164 // UNSIGNED-LABEL: @fix_sign1(
165 // UNSIGNED-NEXT: entry:
166 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
167 // UNSIGNED-NEXT: store i32 [[TMP0]], i32* @ua, align 4
168 // UNSIGNED-NEXT: ret void
169 //
fix_sign1()170 void fix_sign1() {
171 ua = a;
172 }
173
174 // SIGNED-LABEL: @fix_sign2(
175 // SIGNED-NEXT: entry:
176 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
177 // SIGNED-NEXT: [[DOWNSCALE:%.*]] = lshr i32 [[TMP0]], 1
178 // SIGNED-NEXT: store i32 [[DOWNSCALE]], i32* @a, align 4
179 // SIGNED-NEXT: ret void
180 //
181 // UNSIGNED-LABEL: @fix_sign2(
182 // UNSIGNED-NEXT: entry:
183 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
184 // UNSIGNED-NEXT: store i32 [[TMP0]], i32* @a, align 4
185 // UNSIGNED-NEXT: ret void
186 //
fix_sign2()187 void fix_sign2() {
188 a = ua;
189 }
190
191 // SIGNED-LABEL: @fix_sign3(
192 // SIGNED-NEXT: entry:
193 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
194 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i32 [[TMP0]], 1
195 // SIGNED-NEXT: store i32 [[UPSCALE]], i32* @ua, align 4
196 // SIGNED-NEXT: ret void
197 //
198 // UNSIGNED-LABEL: @fix_sign3(
199 // UNSIGNED-NEXT: entry:
200 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
201 // UNSIGNED-NEXT: store i32 [[TMP0]], i32* @ua, align 4
202 // UNSIGNED-NEXT: ret void
203 //
fix_sign3()204 void fix_sign3() {
205 ua = (unsigned _Accum)a;
206 }
207
208 // SIGNED-LABEL: @fix_sign4(
209 // SIGNED-NEXT: entry:
210 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
211 // SIGNED-NEXT: [[DOWNSCALE:%.*]] = lshr i32 [[TMP0]], 1
212 // SIGNED-NEXT: store i32 [[DOWNSCALE]], i32* @a, align 4
213 // SIGNED-NEXT: ret void
214 //
215 // UNSIGNED-LABEL: @fix_sign4(
216 // UNSIGNED-NEXT: entry:
217 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
218 // UNSIGNED-NEXT: store i32 [[TMP0]], i32* @a, align 4
219 // UNSIGNED-NEXT: ret void
220 //
fix_sign4()221 void fix_sign4() {
222 a = (_Accum)ua;
223 }
224
225 // SIGNED-LABEL: @fix_sign5(
226 // SIGNED-NEXT: entry:
227 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
228 // SIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP0]] to i64
229 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i64 [[RESIZE]], 17
230 // SIGNED-NEXT: store i64 [[UPSCALE]], i64* @ula, align 8
231 // SIGNED-NEXT: ret void
232 //
233 // UNSIGNED-LABEL: @fix_sign5(
234 // UNSIGNED-NEXT: entry:
235 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
236 // UNSIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP0]] to i64
237 // UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i64 [[RESIZE]], 16
238 // UNSIGNED-NEXT: store i64 [[UPSCALE]], i64* @ula, align 8
239 // UNSIGNED-NEXT: ret void
240 //
fix_sign5()241 void fix_sign5() {
242 ula = a;
243 }
244
245
246 // CHECK-LABEL: @fix_sat1(
247 // CHECK-NEXT: entry:
248 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @sat_a, align 4
249 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP0]], 8
250 // CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[DOWNSCALE]], 32767
251 // CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i32 32767, i32 [[DOWNSCALE]]
252 // CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[SATMAX]], -32768
253 // CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i32 -32768, i32 [[SATMAX]]
254 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[SATMIN]] to i16
255 // CHECK-NEXT: store i16 [[RESIZE]], i16* @sat_sa, align 2
256 // CHECK-NEXT: ret void
257 //
fix_sat1()258 void fix_sat1() {
259 // Casting down between types
260 sat_sa = sat_a;
261 }
262
263 // CHECK-LABEL: @fix_sat2(
264 // CHECK-NEXT: entry:
265 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @sat_a, align 4
266 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP0]], 8
267 // CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[DOWNSCALE]], 127
268 // CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i32 127, i32 [[DOWNSCALE]]
269 // CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[SATMAX]], -128
270 // CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i32 -128, i32 [[SATMAX]]
271 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[SATMIN]] to i8
272 // CHECK-NEXT: store i8 [[RESIZE]], i8* @sat_sf, align 1
273 // CHECK-NEXT: ret void
274 //
fix_sat2()275 void fix_sat2() {
276 // Accum to Fract, decreasing scale
277 sat_sf = sat_a;
278 }
279
280 // CHECK-LABEL: @fix_sat3(
281 // CHECK-NEXT: entry:
282 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
283 // CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[TMP0]], 32767
284 // CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i32 32767, i32 [[TMP0]]
285 // CHECK-NEXT: [[TMP2:%.*]] = icmp slt i32 [[SATMAX]], -32768
286 // CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i32 -32768, i32 [[SATMAX]]
287 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[SATMIN]] to i16
288 // CHECK-NEXT: store i16 [[RESIZE]], i16* @sat_f, align 2
289 // CHECK-NEXT: ret void
290 //
fix_sat3()291 void fix_sat3() {
292 // Accum to Fract, same scale
293 sat_f = a;
294 }
295
296 // CHECK-LABEL: @fix_sat4(
297 // CHECK-NEXT: entry:
298 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @sat_a, align 4
299 // CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP0]] to i48
300 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i48 [[RESIZE]], 16
301 // CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i48 [[UPSCALE]], 2147483647
302 // CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i48 2147483647, i48 [[UPSCALE]]
303 // CHECK-NEXT: [[TMP2:%.*]] = icmp slt i48 [[SATMAX]], -2147483648
304 // CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i48 -2147483648, i48 [[SATMAX]]
305 // CHECK-NEXT: [[RESIZE1:%.*]] = trunc i48 [[SATMIN]] to i32
306 // CHECK-NEXT: store i32 [[RESIZE1]], i32* @sat_lf, align 4
307 // CHECK-NEXT: ret void
308 //
fix_sat4()309 void fix_sat4() {
310 // Accum to Fract, increasing scale
311 sat_lf = sat_a;
312 }
313
314 // SIGNED-LABEL: @fix_sat5(
315 // SIGNED-NEXT: entry:
316 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @sat_a, align 4
317 // SIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP0]], 7
318 // SIGNED-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[DOWNSCALE]], 65535
319 // SIGNED-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i32 65535, i32 [[DOWNSCALE]]
320 // SIGNED-NEXT: [[TMP2:%.*]] = icmp slt i32 [[SATMAX]], 0
321 // SIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i32 0, i32 [[SATMAX]]
322 // SIGNED-NEXT: [[RESIZE:%.*]] = trunc i32 [[SATMIN]] to i16
323 // SIGNED-NEXT: store i16 [[RESIZE]], i16* @sat_usa, align 2
324 // SIGNED-NEXT: ret void
325 //
326 // UNSIGNED-LABEL: @fix_sat5(
327 // UNSIGNED-NEXT: entry:
328 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @sat_a, align 4
329 // UNSIGNED-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP0]], 8
330 // UNSIGNED-NEXT: [[TMP1:%.*]] = icmp sgt i32 [[DOWNSCALE]], 32767
331 // UNSIGNED-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i32 32767, i32 [[DOWNSCALE]]
332 // UNSIGNED-NEXT: [[TMP2:%.*]] = icmp slt i32 [[SATMAX]], 0
333 // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i32 0, i32 [[SATMAX]]
334 // UNSIGNED-NEXT: [[RESIZE:%.*]] = trunc i32 [[SATMIN]] to i16
335 // UNSIGNED-NEXT: store i16 [[RESIZE]], i16* @sat_usa, align 2
336 // UNSIGNED-NEXT: ret void
337 //
fix_sat5()338 void fix_sat5() {
339 // Signed to unsigned, decreasing scale
340 sat_usa = sat_a;
341 }
342
343 // SIGNED-LABEL: @fix_sat6(
344 // SIGNED-NEXT: entry:
345 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @sat_a, align 4
346 // SIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP0]] to i33
347 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i33 [[RESIZE]], 1
348 // SIGNED-NEXT: [[TMP1:%.*]] = icmp slt i33 [[UPSCALE]], 0
349 // SIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP1]], i33 0, i33 [[UPSCALE]]
350 // SIGNED-NEXT: [[RESIZE1:%.*]] = trunc i33 [[SATMIN]] to i32
351 // SIGNED-NEXT: store i32 [[RESIZE1]], i32* @sat_ua, align 4
352 // SIGNED-NEXT: ret void
353 //
354 // UNSIGNED-LABEL: @fix_sat6(
355 // UNSIGNED-NEXT: entry:
356 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @sat_a, align 4
357 // UNSIGNED-NEXT: [[TMP1:%.*]] = icmp slt i32 [[TMP0]], 0
358 // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP1]], i32 0, i32 [[TMP0]]
359 // UNSIGNED-NEXT: store i32 [[SATMIN]], i32* @sat_ua, align 4
360 // UNSIGNED-NEXT: ret void
361 //
fix_sat6()362 void fix_sat6() {
363 // Signed to unsigned, increasing scale
364 sat_ua = sat_a;
365 }
366
367 // CHECK-LABEL: @fix_sat7(
368 // CHECK-NEXT: entry:
369 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
370 // CHECK-NEXT: store i32 [[TMP0]], i32* @sat_a, align 4
371 // CHECK-NEXT: ret void
372 //
fix_sat7()373 void fix_sat7() {
374 // Nothing when saturating to the same type and size
375 sat_a = a;
376 }
377
378 // CHECK-LABEL: @fix_sat8(
379 // CHECK-NEXT: entry:
380 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @sat_a, align 4
381 // CHECK-NEXT: store i32 [[TMP0]], i32* @a, align 4
382 // CHECK-NEXT: ret void
383 //
fix_sat8()384 void fix_sat8() {
385 // Nothing when assigning back
386 a = sat_a;
387 }
388
389 // CHECK-LABEL: @fix_sat9(
390 // CHECK-NEXT: entry:
391 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @sat_f, align 2
392 // CHECK-NEXT: [[RESIZE:%.*]] = sext i16 [[TMP0]] to i32
393 // CHECK-NEXT: store i32 [[RESIZE]], i32* @sat_a, align 4
394 // CHECK-NEXT: ret void
395 //
fix_sat9()396 void fix_sat9() {
397 // No overflow when casting from fract to signed accum
398 sat_a = sat_f;
399 }
400
401 // SIGNED-LABEL: @fix_sat10(
402 // SIGNED-NEXT: entry:
403 // SIGNED-NEXT: [[TMP0:%.*]] = load i8, i8* @sat_sf, align 1
404 // SIGNED-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP0]] to i32
405 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 9
406 // SIGNED-NEXT: [[TMP1:%.*]] = icmp slt i32 [[UPSCALE]], 0
407 // SIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP1]], i32 0, i32 [[UPSCALE]]
408 // SIGNED-NEXT: store i32 [[SATMIN]], i32* @sat_ua, align 4
409 // SIGNED-NEXT: ret void
410 //
411 // UNSIGNED-LABEL: @fix_sat10(
412 // UNSIGNED-NEXT: entry:
413 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i8, i8* @sat_sf, align 1
414 // UNSIGNED-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP0]] to i32
415 // UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
416 // UNSIGNED-NEXT: [[TMP1:%.*]] = icmp slt i32 [[UPSCALE]], 0
417 // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP1]], i32 0, i32 [[UPSCALE]]
418 // UNSIGNED-NEXT: store i32 [[SATMIN]], i32* @sat_ua, align 4
419 // UNSIGNED-NEXT: ret void
420 //
fix_sat10()421 void fix_sat10() {
422 // Only get overflow checking if signed fract to unsigned accum
423 sat_ua = sat_sf;
424 }
425
426
427 // CHECK-LABEL: @fix_fract1(
428 // CHECK-NEXT: entry:
429 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
430 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i32 [[TMP0]], 8
431 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[DOWNSCALE]] to i8
432 // CHECK-NEXT: store i8 [[RESIZE]], i8* @sf, align 1
433 // CHECK-NEXT: ret void
434 //
fix_fract1()435 void fix_fract1() {
436 // To lower scale
437 sf = a;
438 }
439
440 // CHECK-LABEL: @fix_fract2(
441 // CHECK-NEXT: entry:
442 // CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @sf, align 1
443 // CHECK-NEXT: [[RESIZE:%.*]] = sext i8 [[TMP0]] to i32
444 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i32 [[RESIZE]], 8
445 // CHECK-NEXT: store i32 [[UPSCALE]], i32* @a, align 4
446 // CHECK-NEXT: ret void
447 //
fix_fract2()448 void fix_fract2() {
449 // To higher scale
450 a = sf;
451 }
452
453 // CHECK-LABEL: @fix_fract3(
454 // CHECK-NEXT: entry:
455 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
456 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP0]] to i16
457 // CHECK-NEXT: store i16 [[RESIZE]], i16* @f, align 2
458 // CHECK-NEXT: ret void
459 //
fix_fract3()460 void fix_fract3() {
461 // To same scale
462 f = a;
463 }
464
465 // CHECK-LABEL: @fix_fract4(
466 // CHECK-NEXT: entry:
467 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @f, align 2
468 // CHECK-NEXT: [[RESIZE:%.*]] = sext i16 [[TMP0]] to i32
469 // CHECK-NEXT: store i32 [[RESIZE]], i32* @a, align 4
470 // CHECK-NEXT: ret void
471 //
fix_fract4()472 void fix_fract4() {
473 a = f;
474 }
475
476 // CHECK-LABEL: @fix_fract5(
477 // CHECK-NEXT: entry:
478 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @uf, align 2
479 // CHECK-NEXT: [[RESIZE:%.*]] = zext i16 [[TMP0]] to i32
480 // CHECK-NEXT: store i32 [[RESIZE]], i32* @ua, align 4
481 // CHECK-NEXT: ret void
482 //
fix_fract5()483 void fix_fract5() {
484 // To unsigned
485 ua = uf;
486 }
487
488 // CHECK-LABEL: @fix_fract6(
489 // CHECK-NEXT: entry:
490 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
491 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP0]] to i16
492 // CHECK-NEXT: store i16 [[RESIZE]], i16* @uf, align 2
493 // CHECK-NEXT: ret void
494 //
fix_fract6()495 void fix_fract6() {
496 uf = ua;
497 }
498
499
500 // CHECK-LABEL: @fix_int1(
501 // CHECK-NEXT: entry:
502 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @sa, align 2
503 // CHECK-NEXT: [[TMP1:%.*]] = icmp slt i16 [[TMP0]], 0
504 // CHECK-NEXT: [[TMP2:%.*]] = add i16 [[TMP0]], 127
505 // CHECK-NEXT: [[TMP3:%.*]] = select i1 [[TMP1]], i16 [[TMP2]], i16 [[TMP0]]
506 // CHECK-NEXT: [[DOWNSCALE:%.*]] = ashr i16 [[TMP3]], 7
507 // CHECK-NEXT: [[RESIZE:%.*]] = sext i16 [[DOWNSCALE]] to i32
508 // CHECK-NEXT: store i32 [[RESIZE]], i32* @i, align 4
509 // CHECK-NEXT: ret void
510 //
fix_int1()511 void fix_int1() {
512 // Will need to check for negative values
513 i = sa;
514 }
515
516 // SIGNED-LABEL: @fix_int2(
517 // SIGNED-NEXT: entry:
518 // SIGNED-NEXT: [[TMP0:%.*]] = load i16, i16* @usa, align 2
519 // SIGNED-NEXT: [[DOWNSCALE:%.*]] = lshr i16 [[TMP0]], 8
520 // SIGNED-NEXT: [[RESIZE:%.*]] = zext i16 [[DOWNSCALE]] to i32
521 // SIGNED-NEXT: store i32 [[RESIZE]], i32* @i, align 4
522 // SIGNED-NEXT: ret void
523 //
524 // UNSIGNED-LABEL: @fix_int2(
525 // UNSIGNED-NEXT: entry:
526 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, i16* @usa, align 2
527 // UNSIGNED-NEXT: [[DOWNSCALE:%.*]] = lshr i16 [[TMP0]], 7
528 // UNSIGNED-NEXT: [[RESIZE:%.*]] = zext i16 [[DOWNSCALE]] to i32
529 // UNSIGNED-NEXT: store i32 [[RESIZE]], i32* @i, align 4
530 // UNSIGNED-NEXT: ret void
531 //
fix_int2()532 void fix_int2() {
533 // No check needed for unsigned fixed points. Can just right shift.
534 i = usa;
535 }
536
537
538 // CHECK-LABEL: @int_fix1(
539 // CHECK-NEXT: entry:
540 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @i, align 4
541 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP0]] to i16
542 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i16 [[RESIZE]], 7
543 // CHECK-NEXT: store i16 [[UPSCALE]], i16* @sa, align 2
544 // CHECK-NEXT: ret void
545 //
int_fix1()546 void int_fix1() {
547 sa = i;
548 }
549
550 // CHECK-LABEL: @int_fix2(
551 // CHECK-NEXT: entry:
552 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ui, align 4
553 // CHECK-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP0]] to i16
554 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i16 [[RESIZE]], 7
555 // CHECK-NEXT: store i16 [[UPSCALE]], i16* @sa, align 2
556 // CHECK-NEXT: ret void
557 //
int_fix2()558 void int_fix2() {
559 sa = ui;
560 }
561
562 // SIGNED-LABEL: @int_fix3(
563 // SIGNED-NEXT: entry:
564 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @i, align 4
565 // SIGNED-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP0]] to i16
566 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i16 [[RESIZE]], 8
567 // SIGNED-NEXT: store i16 [[UPSCALE]], i16* @usa, align 2
568 // SIGNED-NEXT: ret void
569 //
570 // UNSIGNED-LABEL: @int_fix3(
571 // UNSIGNED-NEXT: entry:
572 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @i, align 4
573 // UNSIGNED-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP0]] to i16
574 // UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i16 [[RESIZE]], 7
575 // UNSIGNED-NEXT: store i16 [[UPSCALE]], i16* @usa, align 2
576 // UNSIGNED-NEXT: ret void
577 //
int_fix3()578 void int_fix3() {
579 usa = i;
580 }
581
582 // SIGNED-LABEL: @int_fix4(
583 // SIGNED-NEXT: entry:
584 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ui, align 4
585 // SIGNED-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP0]] to i16
586 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i16 [[RESIZE]], 8
587 // SIGNED-NEXT: store i16 [[UPSCALE]], i16* @usa, align 2
588 // SIGNED-NEXT: ret void
589 //
590 // UNSIGNED-LABEL: @int_fix4(
591 // UNSIGNED-NEXT: entry:
592 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ui, align 4
593 // UNSIGNED-NEXT: [[RESIZE:%.*]] = trunc i32 [[TMP0]] to i16
594 // UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i16 [[RESIZE]], 7
595 // UNSIGNED-NEXT: store i16 [[UPSCALE]], i16* @usa, align 2
596 // UNSIGNED-NEXT: ret void
597 //
int_fix4()598 void int_fix4() {
599 usa = ui;
600 }
601
602 // CHECK-LABEL: @int_fix5(
603 // CHECK-NEXT: entry:
604 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @s, align 2
605 // CHECK-NEXT: [[RESIZE:%.*]] = sext i16 [[TMP0]] to i64
606 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i64 [[RESIZE]], 31
607 // CHECK-NEXT: store i64 [[UPSCALE]], i64* @la, align 8
608 // CHECK-NEXT: ret void
609 //
int_fix5()610 void int_fix5() {
611 la = s;
612 }
613
614
615 // CHECK-LABEL: @int_sat1(
616 // CHECK-NEXT: entry:
617 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @i, align 4
618 // CHECK-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP0]] to i39
619 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i39 [[RESIZE]], 7
620 // CHECK-NEXT: [[TMP1:%.*]] = icmp sgt i39 [[UPSCALE]], 32767
621 // CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i39 32767, i39 [[UPSCALE]]
622 // CHECK-NEXT: [[TMP2:%.*]] = icmp slt i39 [[SATMAX]], -32768
623 // CHECK-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i39 -32768, i39 [[SATMAX]]
624 // CHECK-NEXT: [[RESIZE1:%.*]] = trunc i39 [[SATMIN]] to i16
625 // CHECK-NEXT: store i16 [[RESIZE1]], i16* @sat_sa, align 2
626 // CHECK-NEXT: ret void
627 //
int_sat1()628 void int_sat1() {
629 sat_sa = i;
630 }
631
632 // CHECK-LABEL: @int_sat2(
633 // CHECK-NEXT: entry:
634 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @ui, align 4
635 // CHECK-NEXT: [[RESIZE:%.*]] = zext i32 [[TMP0]] to i39
636 // CHECK-NEXT: [[UPSCALE:%.*]] = shl i39 [[RESIZE]], 7
637 // CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i39 [[UPSCALE]], 32767
638 // CHECK-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i39 32767, i39 [[UPSCALE]]
639 // CHECK-NEXT: [[RESIZE1:%.*]] = trunc i39 [[SATMAX]] to i16
640 // CHECK-NEXT: store i16 [[RESIZE1]], i16* @sat_sa, align 2
641 // CHECK-NEXT: ret void
642 //
int_sat2()643 void int_sat2() {
644 sat_sa = ui;
645 }
646
647 // SIGNED-LABEL: @int_sat3(
648 // SIGNED-NEXT: entry:
649 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @i, align 4
650 // SIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP0]] to i40
651 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i40 [[RESIZE]], 8
652 // SIGNED-NEXT: [[TMP1:%.*]] = icmp sgt i40 [[UPSCALE]], 65535
653 // SIGNED-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i40 65535, i40 [[UPSCALE]]
654 // SIGNED-NEXT: [[TMP2:%.*]] = icmp slt i40 [[SATMAX]], 0
655 // SIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i40 0, i40 [[SATMAX]]
656 // SIGNED-NEXT: [[RESIZE1:%.*]] = trunc i40 [[SATMIN]] to i16
657 // SIGNED-NEXT: store i16 [[RESIZE1]], i16* @sat_usa, align 2
658 // SIGNED-NEXT: ret void
659 //
660 // UNSIGNED-LABEL: @int_sat3(
661 // UNSIGNED-NEXT: entry:
662 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @i, align 4
663 // UNSIGNED-NEXT: [[RESIZE:%.*]] = sext i32 [[TMP0]] to i39
664 // UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i39 [[RESIZE]], 7
665 // UNSIGNED-NEXT: [[TMP1:%.*]] = icmp sgt i39 [[UPSCALE]], 32767
666 // UNSIGNED-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i39 32767, i39 [[UPSCALE]]
667 // UNSIGNED-NEXT: [[TMP2:%.*]] = icmp slt i39 [[SATMAX]], 0
668 // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP2]], i39 0, i39 [[SATMAX]]
669 // UNSIGNED-NEXT: [[RESIZE1:%.*]] = trunc i39 [[SATMIN]] to i16
670 // UNSIGNED-NEXT: store i16 [[RESIZE1]], i16* @sat_usa, align 2
671 // UNSIGNED-NEXT: ret void
672 //
int_sat3()673 void int_sat3() {
674 sat_usa = i;
675 }
676
677 // SIGNED-LABEL: @int_sat4(
678 // SIGNED-NEXT: entry:
679 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ui, align 4
680 // SIGNED-NEXT: [[RESIZE:%.*]] = zext i32 [[TMP0]] to i40
681 // SIGNED-NEXT: [[UPSCALE:%.*]] = shl i40 [[RESIZE]], 8
682 // SIGNED-NEXT: [[TMP1:%.*]] = icmp ugt i40 [[UPSCALE]], 65535
683 // SIGNED-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i40 65535, i40 [[UPSCALE]]
684 // SIGNED-NEXT: [[RESIZE1:%.*]] = trunc i40 [[SATMAX]] to i16
685 // SIGNED-NEXT: store i16 [[RESIZE1]], i16* @sat_usa, align 2
686 // SIGNED-NEXT: ret void
687 //
688 // UNSIGNED-LABEL: @int_sat4(
689 // UNSIGNED-NEXT: entry:
690 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ui, align 4
691 // UNSIGNED-NEXT: [[RESIZE:%.*]] = zext i32 [[TMP0]] to i39
692 // UNSIGNED-NEXT: [[UPSCALE:%.*]] = shl i39 [[RESIZE]], 7
693 // UNSIGNED-NEXT: [[TMP1:%.*]] = icmp ugt i39 [[UPSCALE]], 32767
694 // UNSIGNED-NEXT: [[SATMAX:%.*]] = select i1 [[TMP1]], i39 32767, i39 [[UPSCALE]]
695 // UNSIGNED-NEXT: [[RESIZE1:%.*]] = trunc i39 [[SATMAX]] to i16
696 // UNSIGNED-NEXT: store i16 [[RESIZE1]], i16* @sat_usa, align 2
697 // UNSIGNED-NEXT: ret void
698 //
int_sat4()699 void int_sat4() {
700 sat_usa = ui;
701 }
702
703
704 // CHECK-LABEL: @float_fix1(
705 // CHECK-NEXT: entry:
706 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
707 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 1.280000e+02
708 // CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i16
709 // CHECK-NEXT: store i16 [[TMP2]], i16* @sa, align 2
710 // CHECK-NEXT: ret void
711 //
float_fix1()712 void float_fix1() {
713 sa = fl;
714 }
715
716 // CHECK-LABEL: @float_fix2(
717 // CHECK-NEXT: entry:
718 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
719 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 3.276800e+04
720 // CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i32
721 // CHECK-NEXT: store i32 [[TMP2]], i32* @a, align 4
722 // CHECK-NEXT: ret void
723 //
float_fix2()724 void float_fix2() {
725 a = fl;
726 }
727
728 // CHECK-LABEL: @float_fix3(
729 // CHECK-NEXT: entry:
730 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
731 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 0x41E0000000000000
732 // CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i64
733 // CHECK-NEXT: store i64 [[TMP2]], i64* @la, align 8
734 // CHECK-NEXT: ret void
735 //
float_fix3()736 void float_fix3() {
737 la = fl;
738 }
739
740 // CHECK-LABEL: @float_fix4(
741 // CHECK-NEXT: entry:
742 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
743 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 1.280000e+02
744 // CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i8
745 // CHECK-NEXT: store i8 [[TMP2]], i8* @sf, align 1
746 // CHECK-NEXT: ret void
747 //
float_fix4()748 void float_fix4() {
749 sf = fl;
750 }
751
752 // CHECK-LABEL: @float_fix5(
753 // CHECK-NEXT: entry:
754 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
755 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 0x41E0000000000000
756 // CHECK-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i32
757 // CHECK-NEXT: store i32 [[TMP2]], i32* @lf, align 4
758 // CHECK-NEXT: ret void
759 //
float_fix5()760 void float_fix5() {
761 lf = fl;
762 }
763
764 // SIGNED-LABEL: @float_fix6(
765 // SIGNED-NEXT: entry:
766 // SIGNED-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
767 // SIGNED-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 6.553600e+04
768 // SIGNED-NEXT: [[TMP2:%.*]] = fptoui float [[TMP1]] to i32
769 // SIGNED-NEXT: store i32 [[TMP2]], i32* @ua, align 4
770 // SIGNED-NEXT: ret void
771 //
772 // UNSIGNED-LABEL: @float_fix6(
773 // UNSIGNED-NEXT: entry:
774 // UNSIGNED-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
775 // UNSIGNED-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 3.276800e+04
776 // UNSIGNED-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i32
777 // UNSIGNED-NEXT: store i32 [[TMP2]], i32* @ua, align 4
778 // UNSIGNED-NEXT: ret void
779 //
float_fix6()780 void float_fix6() {
781 ua = fl;
782 }
783
784 // SIGNED-LABEL: @float_fix7(
785 // SIGNED-NEXT: entry:
786 // SIGNED-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
787 // SIGNED-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 6.553600e+04
788 // SIGNED-NEXT: [[TMP2:%.*]] = fptoui float [[TMP1]] to i16
789 // SIGNED-NEXT: store i16 [[TMP2]], i16* @uf, align 2
790 // SIGNED-NEXT: ret void
791 //
792 // UNSIGNED-LABEL: @float_fix7(
793 // UNSIGNED-NEXT: entry:
794 // UNSIGNED-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
795 // UNSIGNED-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 3.276800e+04
796 // UNSIGNED-NEXT: [[TMP2:%.*]] = fptosi float [[TMP1]] to i16
797 // UNSIGNED-NEXT: store i16 [[TMP2]], i16* @uf, align 2
798 // UNSIGNED-NEXT: ret void
799 //
float_fix7()800 void float_fix7() {
801 uf = fl;
802 }
803
804
805 // CHECK-LABEL: @fix_float1(
806 // CHECK-NEXT: entry:
807 // CHECK-NEXT: [[TMP0:%.*]] = load i16, i16* @sa, align 2
808 // CHECK-NEXT: [[TMP1:%.*]] = sitofp i16 [[TMP0]] to float
809 // CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 7.812500e-03
810 // CHECK-NEXT: store float [[TMP2]], float* @fl, align 4
811 // CHECK-NEXT: ret void
812 //
fix_float1()813 void fix_float1() {
814 fl = sa;
815 }
816
817 // CHECK-LABEL: @fix_float2(
818 // CHECK-NEXT: entry:
819 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @a, align 4
820 // CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float
821 // CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000
822 // CHECK-NEXT: store float [[TMP2]], float* @fl, align 4
823 // CHECK-NEXT: ret void
824 //
fix_float2()825 void fix_float2() {
826 fl = a;
827 }
828
829 // CHECK-LABEL: @fix_float3(
830 // CHECK-NEXT: entry:
831 // CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* @la, align 8
832 // CHECK-NEXT: [[TMP1:%.*]] = sitofp i64 [[TMP0]] to float
833 // CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000
834 // CHECK-NEXT: store float [[TMP2]], float* @fl, align 4
835 // CHECK-NEXT: ret void
836 //
fix_float3()837 void fix_float3() {
838 fl = la;
839 }
840
841 // CHECK-LABEL: @fix_float4(
842 // CHECK-NEXT: entry:
843 // CHECK-NEXT: [[TMP0:%.*]] = load i8, i8* @sf, align 1
844 // CHECK-NEXT: [[TMP1:%.*]] = sitofp i8 [[TMP0]] to float
845 // CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 7.812500e-03
846 // CHECK-NEXT: store float [[TMP2]], float* @fl, align 4
847 // CHECK-NEXT: ret void
848 //
fix_float4()849 void fix_float4() {
850 fl = sf;
851 }
852
853 // CHECK-LABEL: @fix_float5(
854 // CHECK-NEXT: entry:
855 // CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* @lf, align 4
856 // CHECK-NEXT: [[TMP1:%.*]] = sitofp i32 [[TMP0]] to float
857 // CHECK-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3E00000000000000
858 // CHECK-NEXT: store float [[TMP2]], float* @fl, align 4
859 // CHECK-NEXT: ret void
860 //
fix_float5()861 void fix_float5() {
862 fl = lf;
863 }
864
865 // SIGNED-LABEL: @fix_float6(
866 // SIGNED-NEXT: entry:
867 // SIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
868 // SIGNED-NEXT: [[TMP1:%.*]] = uitofp i32 [[TMP0]] to float
869 // SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3EF0000000000000
870 // SIGNED-NEXT: store float [[TMP2]], float* @fl, align 4
871 // SIGNED-NEXT: ret void
872 //
873 // UNSIGNED-LABEL: @fix_float6(
874 // UNSIGNED-NEXT: entry:
875 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i32, i32* @ua, align 4
876 // UNSIGNED-NEXT: [[TMP1:%.*]] = uitofp i32 [[TMP0]] to float
877 // UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000
878 // UNSIGNED-NEXT: store float [[TMP2]], float* @fl, align 4
879 // UNSIGNED-NEXT: ret void
880 //
fix_float6()881 void fix_float6() {
882 fl = ua;
883 }
884
885 // SIGNED-LABEL: @fix_float7(
886 // SIGNED-NEXT: entry:
887 // SIGNED-NEXT: [[TMP0:%.*]] = load i16, i16* @uf, align 2
888 // SIGNED-NEXT: [[TMP1:%.*]] = uitofp i16 [[TMP0]] to float
889 // SIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3EF0000000000000
890 // SIGNED-NEXT: store float [[TMP2]], float* @fl, align 4
891 // SIGNED-NEXT: ret void
892 //
893 // UNSIGNED-LABEL: @fix_float7(
894 // UNSIGNED-NEXT: entry:
895 // UNSIGNED-NEXT: [[TMP0:%.*]] = load i16, i16* @uf, align 2
896 // UNSIGNED-NEXT: [[TMP1:%.*]] = uitofp i16 [[TMP0]] to float
897 // UNSIGNED-NEXT: [[TMP2:%.*]] = fmul float [[TMP1]], 0x3F00000000000000
898 // UNSIGNED-NEXT: store float [[TMP2]], float* @fl, align 4
899 // UNSIGNED-NEXT: ret void
900 //
fix_float7()901 void fix_float7() {
902 fl = uf;
903 }
904
905
906 // CHECK-LABEL: @float_sat1(
907 // CHECK-NEXT: entry:
908 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
909 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 1.280000e+02
910 // CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.fptosi.sat.i16.f32(float [[TMP1]])
911 // CHECK-NEXT: store i16 [[TMP2]], i16* @sat_sa, align 2
912 // CHECK-NEXT: ret void
913 //
float_sat1()914 void float_sat1() {
915 sat_sa = fl;
916 }
917
918 // CHECK-LABEL: @float_sat2(
919 // CHECK-NEXT: entry:
920 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
921 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 3.276800e+04
922 // CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.fptosi.sat.i32.f32(float [[TMP1]])
923 // CHECK-NEXT: store i32 [[TMP2]], i32* @sat_a, align 4
924 // CHECK-NEXT: ret void
925 //
float_sat2()926 void float_sat2() {
927 sat_a = fl;
928 }
929
930 // CHECK-LABEL: @float_sat3(
931 // CHECK-NEXT: entry:
932 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
933 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 0x41E0000000000000
934 // CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.fptosi.sat.i64.f32(float [[TMP1]])
935 // CHECK-NEXT: store i64 [[TMP2]], i64* @sat_la, align 8
936 // CHECK-NEXT: ret void
937 //
float_sat3()938 void float_sat3() {
939 sat_la = fl;
940 }
941
942 // CHECK-LABEL: @float_sat4(
943 // CHECK-NEXT: entry:
944 // CHECK-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
945 // CHECK-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 1.280000e+02
946 // CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.fptosi.sat.i8.f32(float [[TMP1]])
947 // CHECK-NEXT: store i8 [[TMP2]], i8* @sat_sf, align 1
948 // CHECK-NEXT: ret void
949 //
float_sat4()950 void float_sat4() {
951 sat_sf = fl;
952 }
953
954 // SIGNED-LABEL: @float_sat5(
955 // SIGNED-NEXT: entry:
956 // SIGNED-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
957 // SIGNED-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 6.553600e+04
958 // SIGNED-NEXT: [[TMP2:%.*]] = call i32 @llvm.fptoui.sat.i32.f32(float [[TMP1]])
959 // SIGNED-NEXT: store i32 [[TMP2]], i32* @sat_ua, align 4
960 // SIGNED-NEXT: ret void
961 //
962 // UNSIGNED-LABEL: @float_sat5(
963 // UNSIGNED-NEXT: entry:
964 // UNSIGNED-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
965 // UNSIGNED-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 3.276800e+04
966 // UNSIGNED-NEXT: [[TMP2:%.*]] = call i32 @llvm.fptosi.sat.i32.f32(float [[TMP1]])
967 // UNSIGNED-NEXT: [[TMP3:%.*]] = icmp slt i32 [[TMP2]], 0
968 // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
969 // UNSIGNED-NEXT: store i32 [[SATMIN]], i32* @sat_ua, align 4
970 // UNSIGNED-NEXT: ret void
971 //
float_sat5()972 void float_sat5() {
973 sat_ua = fl;
974 }
975
976 // SIGNED-LABEL: @float_sat6(
977 // SIGNED-NEXT: entry:
978 // SIGNED-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
979 // SIGNED-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 6.553600e+04
980 // SIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.fptoui.sat.i16.f32(float [[TMP1]])
981 // SIGNED-NEXT: store i16 [[TMP2]], i16* @sat_uf, align 2
982 // SIGNED-NEXT: ret void
983 //
984 // UNSIGNED-LABEL: @float_sat6(
985 // UNSIGNED-NEXT: entry:
986 // UNSIGNED-NEXT: [[TMP0:%.*]] = load float, float* @fl, align 4
987 // UNSIGNED-NEXT: [[TMP1:%.*]] = fmul float [[TMP0]], 3.276800e+04
988 // UNSIGNED-NEXT: [[TMP2:%.*]] = call i16 @llvm.fptosi.sat.i16.f32(float [[TMP1]])
989 // UNSIGNED-NEXT: [[TMP3:%.*]] = icmp slt i16 [[TMP2]], 0
990 // UNSIGNED-NEXT: [[SATMIN:%.*]] = select i1 [[TMP3]], i16 0, i16 [[TMP2]]
991 // UNSIGNED-NEXT: store i16 [[SATMIN]], i16* @sat_uf, align 2
992 // UNSIGNED-NEXT: ret void
993 //
float_sat6()994 void float_sat6() {
995 sat_uf = fl;
996 }
997