1//===- Mips16InstrFormats.td - Mips Instruction Formats ----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Describe MIPS instructions format
11//
12//  CPU INSTRUCTION FORMATS
13//
14//  funct or f      Function field
15//
16//  immediate       4-,5-,8- or 11-bit immediate, branch displacement, or
17//  or imm          address displacement
18//
19//  op              5-bit major operation code
20//
21//  rx              3-bit source or destination register
22//
23//  ry              3-bit source or destination register
24//
25//  rz              3-bit source or destination register
26//
27//  sa              3- or 5-bit shift amount
28//
29//===----------------------------------------------------------------------===//
30
31
32// Base class for Mips 16 Format
33// This class does not depend on the instruction size
34//
35class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
36                      InstrItinClass itin>: Instruction
37{
38
39  let Namespace = "Mips";
40
41  let OutOperandList = outs;
42  let InOperandList  = ins;
43
44  let AsmString   = asmstr;
45  let Pattern     = pattern;
46  let Itinerary   = itin;
47
48  let Predicates = [InMips16Mode];
49}
50
51//
52// Generic Mips 16 Format
53//
54class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
55                 InstrItinClass itin>:
56  MipsInst16_Base<outs, ins, asmstr, pattern, itin>
57{
58  field bits<16> Inst;
59  bits<5> Opcode = 0;
60
61  // Top 5 bits are the 'opcode' field
62  let Inst{15-11} = Opcode;
63
64  let Size=2;
65  field bits<16> SoftFail = 0;
66}
67
68//
69// For 32 bit extended instruction forms.
70//
71class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
72                    InstrItinClass itin>:
73  MipsInst16_Base<outs, ins, asmstr, pattern, itin>
74{
75  field bits<32> Inst;
76
77  let Size=4;
78  field bits<32> SoftFail = 0;
79}
80
81class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
82                        InstrItinClass itin>:
83  MipsInst16_32<outs, ins, asmstr, pattern, itin>
84{
85  let Inst{31-27} = 0b11110;
86}
87
88
89
90// Mips Pseudo Instructions Format
91class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
92  MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
93  let isCodeGenOnly = 1;
94  let isPseudo = 1;
95}
96
97
98//===----------------------------------------------------------------------===//
99// Format I instruction class in Mips : <|opcode|imm11|>
100//===----------------------------------------------------------------------===//
101
102class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
103           InstrItinClass itin>:
104  MipsInst16<outs, ins, asmstr, pattern, itin>
105{
106  bits<11> imm11;
107
108  let Opcode = op;
109
110  let Inst{10-0}  = imm11;
111}
112
113//===----------------------------------------------------------------------===//
114// Format RI instruction class in Mips : <|opcode|rx|imm8|>
115//===----------------------------------------------------------------------===//
116
117class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
118            list<dag> pattern, InstrItinClass itin>:
119  MipsInst16<outs, ins, asmstr, pattern, itin>
120{
121  bits<3>  rx;
122  bits<8>   imm8;
123
124  let Opcode = op;
125
126  let Inst{10-8} = rx;
127  let Inst{7-0} = imm8;
128}
129
130//===----------------------------------------------------------------------===//
131// Format RR instruction class in Mips : <|opcode|rx|ry|funct|>
132//===----------------------------------------------------------------------===//
133
134class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
135            list<dag> pattern, InstrItinClass itin>:
136  MipsInst16<outs, ins, asmstr, pattern, itin>
137{
138  bits<3>  rx;
139  bits<3>  ry;
140  bits<5>  funct;
141
142  let Opcode = 0b11101;
143  let funct  = _funct;
144
145  let Inst{10-8} = rx;
146  let Inst{7-5} = ry;
147  let Inst{4-0}   = funct;
148}
149
150class FRRBreak16<dag outs, dag ins, string asmstr,
151                 list<dag> pattern, InstrItinClass itin>:
152  MipsInst16<outs, ins, asmstr, pattern, itin>
153{
154  bits<6>  Code;
155  bits<5>  funct;
156
157  let Opcode = 0b11101;
158  let funct  = 0b00101;
159
160  let Inst{10-5} = Code;
161  let Inst{4-0}   = funct;
162}
163
164//
165// For conversion functions.
166//
167class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
168               string asmstr, list<dag> pattern, InstrItinClass itin>:
169  MipsInst16<outs, ins, asmstr, pattern, itin>
170{
171  bits<3>  rx;
172  bits<3>  subfunct;
173  bits<5>  funct;
174
175  let Opcode = 0b11101; // RR
176  let funct  = _funct;
177  let subfunct = _subfunct;
178
179  let Inst{10-8} = rx;
180  let Inst{7-5} = subfunct;
181  let Inst{4-0}   = funct;
182}
183
184//
185// just used for breakpoint (hardware and software) instructions.
186//
187class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
188           list<dag> pattern, InstrItinClass itin>:
189  MipsInst16<outs, ins, asmstr, pattern, itin>
190{
191  bits<6>  _code;  // code is a keyword in tablegen
192  bits<5>  funct;
193
194  let Opcode = 0b11101; // RR
195  let funct  = _funct;
196
197  let Inst{10-5} = _code;
198  let Inst{4-0}   = funct;
199}
200
201//
202// J(AL)R(C) subformat
203//
204class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
205                  dag outs, dag ins, string asmstr,
206                  list<dag> pattern, InstrItinClass itin>:
207  MipsInst16<outs, ins, asmstr, pattern, itin>
208{
209  bits<3>  rx;
210  bits<1>  nd;
211  bits<1>  l;
212  bits<1>  ra;
213
214  let nd = _nd;
215  let l = _l;
216  let ra = r_a;
217
218  let Opcode = 0b11101;
219
220  let Inst{10-8} = rx;
221  let Inst{7} = nd;
222  let Inst{6} = l;
223  let Inst{5} = ra;
224  let Inst{4-0} = 0;
225}
226
227//===----------------------------------------------------------------------===//
228// Format RRI instruction class in Mips : <|opcode|rx|ry|imm5|>
229//===----------------------------------------------------------------------===//
230
231class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
232             list<dag> pattern, InstrItinClass itin>:
233  MipsInst16<outs, ins, asmstr, pattern, itin>
234{
235  bits<3>  rx;
236  bits<3>  ry;
237  bits<5>  imm5;
238
239  let Opcode = op;
240
241
242  let Inst{10-8} = rx;
243  let Inst{7-5} = ry;
244  let Inst{4-0}   = imm5;
245}
246
247//===----------------------------------------------------------------------===//
248// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
249//===----------------------------------------------------------------------===//
250
251class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
252             list<dag> pattern, InstrItinClass itin>:
253  MipsInst16<outs, ins, asmstr, pattern, itin>
254{
255  bits<3>  rx;
256  bits<3>  ry;
257  bits<3>  rz;
258  bits<2>  f;
259
260  let Opcode = 0b11100;
261  let f  = _f;
262
263  let Inst{10-8} = rx;
264  let Inst{7-5} = ry;
265  let Inst{4-2} = rz;
266  let Inst{1-0}   = f;
267}
268
269//===----------------------------------------------------------------------===//
270// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
271//===----------------------------------------------------------------------===//
272
273class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
274               list<dag> pattern, InstrItinClass itin>:
275  MipsInst16<outs, ins, asmstr, pattern, itin>
276{
277  bits<3>  rx;
278  bits<3>  ry;
279  bits<1>  f;
280  bits<4>  imm4;
281
282  let Opcode = 0b01000;
283  let  f = _f;
284
285  let Inst{10-8} = rx;
286  let Inst{7-5} = ry;
287  let Inst{4} = f;
288  let Inst{3-0}   = imm4;
289}
290
291//===----------------------------------------------------------------------===//
292// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
293//===----------------------------------------------------------------------===//
294
295class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
296               list<dag> pattern, InstrItinClass itin>:
297  MipsInst16<outs, ins, asmstr, pattern, itin>
298{
299  bits<3>  rx;
300  bits<3>  ry;
301  bits<3>  sa;
302  bits<2>  f;
303
304  let Opcode = 0b00110;
305  let f  = _f;
306
307  let Inst{10-8} = rx;
308  let Inst{7-5} = ry;
309  let Inst{4-2} = sa;
310  let Inst{1-0}   = f;
311}
312
313//===----------------------------------------------------------------------===//
314// Format i8 instruction class in Mips : <|opcode|funct|imm8>
315//===----------------------------------------------------------------------===//
316
317class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
318            list<dag> pattern, InstrItinClass itin>:
319  MipsInst16<outs, ins, asmstr, pattern, itin>
320{
321  bits<3>  func;
322  bits<8>   imm8;
323
324  let Opcode = 0b01100;
325  let func  = _func;
326
327  let Inst{10-8} = func;
328  let Inst{7-0} = imm8;
329}
330
331//===----------------------------------------------------------------------===//
332// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
333//===----------------------------------------------------------------------===//
334
335class FI8_MOVR3216<dag outs, dag ins, string asmstr,
336                   list<dag> pattern, InstrItinClass itin>:
337  MipsInst16<outs, ins, asmstr, pattern, itin>
338{
339
340  bits<4> ry;
341  bits<4> r32;
342
343  let Opcode = 0b01100;
344
345  let Inst{10-8} = 0b111;
346  let Inst{7-4} = ry;
347  let Inst{3-0} = r32;
348
349}
350
351
352
353//===----------------------------------------------------------------------===//
354// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>
355//===----------------------------------------------------------------------===//
356
357class FI8_MOV32R16<dag outs, dag ins, string asmstr,
358                   list<dag> pattern, InstrItinClass itin>:
359  MipsInst16<outs, ins, asmstr, pattern, itin>
360{
361
362  bits<3>  func;
363  bits<5> r32;
364  bits<3> rz;
365
366
367  let Opcode = 0b01100;
368
369  let Inst{10-8} = 0b101;
370  let Inst{7-5} = r32{2-0};
371  let Inst{4-3} = r32{4-3};
372  let Inst{2-0} = rz;
373
374}
375
376//===----------------------------------------------------------------------===//
377// Format i8_SVRS instruction class in Mips :
378//    <|opcode|svrs|s|ra|s0|s1|framesize>
379//===----------------------------------------------------------------------===//
380
381class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
382                 list<dag> pattern, InstrItinClass itin>:
383  MipsInst16<outs, ins, asmstr, pattern, itin>
384{
385  bits<1> s;
386  bits<1> ra = 0;
387  bits<1> s0 = 0;
388  bits<1> s1 = 0;
389  bits<4> framesize = 0;
390
391  let s =_s;
392  let Opcode = 0b01100;
393
394  let Inst{10-8} = 0b100;
395  let Inst{7} = s;
396  let Inst{6} = ra;
397  let Inst{5} = s0;
398  let Inst{4} = s1;
399  let Inst{3-0} = framesize;
400
401}
402
403//===----------------------------------------------------------------------===//
404// Format JAL instruction class in Mips16 :
405//    <|opcode|svrs|s|ra|s0|s1|framesize>
406//===----------------------------------------------------------------------===//
407
408class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
409             list<dag> pattern, InstrItinClass itin>:
410  MipsInst16_32<outs, ins, asmstr, pattern, itin>
411{
412  bits<1> X;
413  bits<26> imm26;
414
415
416  let X = _X;
417
418  let Inst{31-27} = 0b00011;
419  let Inst{26} = X;
420  let Inst{25-21} = imm26{20-16};
421  let Inst{20-16} = imm26{25-21};
422  let Inst{15-0}  = imm26{15-0};
423
424}
425
426//===----------------------------------------------------------------------===//
427// Format EXT-I instruction class in Mips16 :
428//     <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
429//===----------------------------------------------------------------------===//
430
431class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
432               list<dag> pattern, InstrItinClass itin>:
433  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
434{
435  bits<16> imm16;
436  bits<5> eop;
437
438  let eop = _eop;
439
440  let Inst{26-21} = imm16{10-5};
441  let Inst{20-16} = imm16{15-11};
442  let Inst{15-11} = eop;
443  let Inst{10-5} = 0;
444  let Inst{4-0} = imm16{4-0};
445
446}
447
448//===----------------------------------------------------------------------===//
449// Format ASMACRO instruction class in Mips16 :
450//    <EXTEND|select|p4|p3|RRR|p2|p1|p0>
451//===----------------------------------------------------------------------===//
452
453class FASMACRO16<dag outs, dag ins, string asmstr,
454                 list<dag> pattern, InstrItinClass itin>:
455  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
456{
457  bits<3> select;
458  bits<3> p4;
459  bits<5> p3;
460  bits<5> RRR = 0b11100;
461  bits<3> p2;
462  bits<3> p1;
463  bits<5> p0;
464
465
466  let Inst{26-24} = select;
467  let Inst{23-21} = p4;
468  let Inst{20-16} = p3;
469  let Inst{15-11} = RRR;
470  let Inst{10-8} = p2;
471  let Inst{7-5} = p1;
472  let Inst{4-0} = p0;
473
474}
475
476
477//===----------------------------------------------------------------------===//
478// Format EXT-RI instruction class in Mips16 :
479//    <|EXTEND|imm10:5|imm15:11|op|rx|0|0|0|imm4:0>
480//===----------------------------------------------------------------------===//
481
482class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
483                list<dag> pattern, InstrItinClass itin>:
484  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
485{
486  bits<16> imm16;
487  bits<5> op;
488  bits<3> rx;
489
490  let op = _op;
491
492  let Inst{26-21} = imm16{10-5};
493  let Inst{20-16} = imm16{15-11};
494  let Inst{15-11} = op;
495  let Inst{10-8} = rx;
496  let Inst{7-5} = 0;
497  let Inst{4-0} = imm16{4-0};
498
499}
500
501//===----------------------------------------------------------------------===//
502// Format EXT-RRI instruction class in Mips16 :
503//     <|EXTEND|imm10:5|imm15:11|op|rx|ry|imm4:0>
504//===----------------------------------------------------------------------===//
505
506class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
507                 list<dag> pattern, InstrItinClass itin>:
508  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
509{
510  bits<5> op;
511  bits<16> imm16;
512  bits<3> rx;
513  bits<3> ry;
514
515  let op=_op;
516
517  let Inst{26-21} = imm16{10-5};
518  let Inst{20-16} = imm16{15-11};
519  let Inst{15-11} = op;
520  let Inst{10-8} = rx;
521  let Inst{7-5} = ry;
522  let Inst{4-0} = imm16{4-0};
523
524}
525
526//===----------------------------------------------------------------------===//
527// Format EXT-RRI-A instruction class in Mips16 :
528//    <|EXTEND|imm10:4|imm14:11|RRI-A|rx|ry|f|imm3:0>
529//===----------------------------------------------------------------------===//
530
531class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
532                   list<dag> pattern, InstrItinClass itin>:
533  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
534{
535  bits<15> imm15;
536  bits<3> rx;
537  bits<3> ry;
538  bits<1> f;
539
540  let f = _f;
541
542  let Inst{26-20} = imm15{10-4};
543  let Inst{19-16} = imm15{14-11};
544  let Inst{15-11} = 0b01000;
545  let Inst{10-8} = rx;
546  let Inst{7-5} = ry;
547  let Inst{4} = f;
548  let Inst{3-0} = imm15{3-0};
549
550}
551
552//===----------------------------------------------------------------------===//
553// Format EXT-SHIFT instruction class in Mips16 :
554//    <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
555//===----------------------------------------------------------------------===//
556
557class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
558                   list<dag> pattern, InstrItinClass itin>:
559  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
560{
561  bits<6> sa6;
562  bits<3> rx;
563  bits<3> ry;
564  bits<2> f;
565
566  let f = _f;
567
568  let Inst{26-22} = sa6{4-0};
569  let Inst{21} = sa6{5};
570  let Inst{20-16} = 0;
571  let Inst{15-11} = 0b00110;
572  let Inst{10-8} = rx;
573  let Inst{7-5} = ry;
574  let Inst{4-2} = 0;
575  let Inst{1-0} = f;
576
577}
578
579//===----------------------------------------------------------------------===//
580// Format EXT-I8 instruction class in Mips16 :
581//    <|EXTEND|imm10:5|imm15:11|I8|funct|0|imm4:0>
582//===----------------------------------------------------------------------===//
583
584class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
585                list<dag> pattern, InstrItinClass itin>:
586  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
587{
588  bits<16> imm16;
589  bits<5> I8;
590  bits<3> funct;
591
592  let funct = _funct;
593  let I8 = 0b00110;
594
595  let Inst{26-21} = imm16{10-5};
596  let Inst{20-16} = imm16{15-11};
597  let Inst{15-11} = I8;
598  let Inst{10-8} = funct;
599  let Inst{7-5} = 0;
600  let Inst{4-0} = imm16{4-0};
601
602}
603
604//===----------------------------------------------------------------------===//
605// Format EXT-I8_SVRS instruction class in Mips16 :
606//    <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
607//===----------------------------------------------------------------------===//
608
609class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
610                     list<dag> pattern, InstrItinClass itin>:
611  MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin>
612{
613  bits<3> xsregs =0;
614  bits<8> framesize =0;
615  bits<3> aregs =0;
616  bits<5> I8 = 0b01100;
617  bits<3> SVRS = 0b100;
618  bits<1> s;
619  bits<1> ra = 0;
620  bits<1> s0 = 0;
621  bits<1> s1 = 0;
622
623  let s= s_;
624
625  let Inst{26-24} = xsregs;
626  let Inst{23-20} = framesize{7-4};
627  let Inst{19} = 0;
628  let Inst{18-16} = aregs;
629  let Inst{15-11} = I8;
630  let Inst{10-8} = SVRS;
631  let Inst{7} = s;
632  let Inst{6} = ra;
633  let Inst{5} = s0;
634  let Inst{4} = s1;
635  let Inst{3-0} = framesize{3-0};
636
637
638}
639
640