1//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9//===----------------------------------------------------------------------===//
10//  Declarations that describe the MIPS register file
11//===----------------------------------------------------------------------===//
12let Namespace = "Mips" in {
13def sub_32     : SubRegIndex<32>;
14def sub_64     : SubRegIndex<64>;
15def sub_lo     : SubRegIndex<32>;
16def sub_hi     : SubRegIndex<32, 32>;
17def sub_dsp16_19 : SubRegIndex<4, 16>;
18def sub_dsp20    : SubRegIndex<1, 20>;
19def sub_dsp21    : SubRegIndex<1, 21>;
20def sub_dsp22    : SubRegIndex<1, 22>;
21def sub_dsp23    : SubRegIndex<1, 23>;
22}
23
24class Unallocatable {
25  bit isAllocatable = 0;
26}
27
28// We have banks of 32 registers each.
29class MipsReg<bits<16> Enc, string n> : Register<n> {
30  let HWEncoding = Enc;
31  let Namespace = "Mips";
32}
33
34class MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs>
35  : RegisterWithSubRegs<n, subregs> {
36  let HWEncoding = Enc;
37  let Namespace = "Mips";
38}
39
40// Mips CPU Registers.
41class MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>;
42
43// Mips 64-bit CPU Registers
44class Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs>
45  : MipsRegWithSubRegs<Enc, n, subregs> {
46  let SubRegIndices = [sub_32];
47}
48
49// Mips 32-bit FPU Registers
50class FPR<bits<16> Enc, string n> : MipsReg<Enc, n>;
51
52// Mips 64-bit (aliased) FPU Registers
53class AFPR<bits<16> Enc, string n, list<Register> subregs>
54  : MipsRegWithSubRegs<Enc, n, subregs> {
55  let SubRegIndices = [sub_lo, sub_hi];
56  let CoveredBySubRegs = 1;
57}
58
59class AFPR64<bits<16> Enc, string n, list<Register> subregs>
60  : MipsRegWithSubRegs<Enc, n, subregs> {
61  let SubRegIndices = [sub_lo, sub_hi];
62  let CoveredBySubRegs = 1;
63}
64
65// Mips 128-bit (aliased) MSA Registers
66class AFPR128<bits<16> Enc, string n, list<Register> subregs>
67  : MipsRegWithSubRegs<Enc, n, subregs> {
68  let SubRegIndices = [sub_64];
69}
70
71// Accumulator Registers
72class ACCReg<bits<16> Enc, string n, list<Register> subregs>
73  : MipsRegWithSubRegs<Enc, n, subregs> {
74  let SubRegIndices = [sub_lo, sub_hi];
75  let CoveredBySubRegs = 1;
76}
77
78// Mips Hardware Registers
79class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
80
81//===----------------------------------------------------------------------===//
82//  Registers
83//===----------------------------------------------------------------------===//
84
85let Namespace = "Mips" in {
86  // General Purpose Registers
87  def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
88  def AT   : MipsGPRReg< 1, "1">,    DwarfRegNum<[1]>;
89  def V0   : MipsGPRReg< 2, "2">,    DwarfRegNum<[2]>;
90  def V1   : MipsGPRReg< 3, "3">,    DwarfRegNum<[3]>;
91  def A0   : MipsGPRReg< 4, "4">,    DwarfRegNum<[4]>;
92  def A1   : MipsGPRReg< 5, "5">,    DwarfRegNum<[5]>;
93  def A2   : MipsGPRReg< 6, "6">,    DwarfRegNum<[6]>;
94  def A3   : MipsGPRReg< 7, "7">,    DwarfRegNum<[7]>;
95  def T0   : MipsGPRReg< 8, "8">,    DwarfRegNum<[8]>;
96  def T1   : MipsGPRReg< 9, "9">,    DwarfRegNum<[9]>;
97  def T2   : MipsGPRReg< 10, "10">,  DwarfRegNum<[10]>;
98  def T3   : MipsGPRReg< 11, "11">,  DwarfRegNum<[11]>;
99  def T4   : MipsGPRReg< 12, "12">,  DwarfRegNum<[12]>;
100  def T5   : MipsGPRReg< 13, "13">,  DwarfRegNum<[13]>;
101  def T6   : MipsGPRReg< 14, "14">,  DwarfRegNum<[14]>;
102  def T7   : MipsGPRReg< 15, "15">,  DwarfRegNum<[15]>;
103  def S0   : MipsGPRReg< 16, "16">,  DwarfRegNum<[16]>;
104  def S1   : MipsGPRReg< 17, "17">,  DwarfRegNum<[17]>;
105  def S2   : MipsGPRReg< 18, "18">,  DwarfRegNum<[18]>;
106  def S3   : MipsGPRReg< 19, "19">,  DwarfRegNum<[19]>;
107  def S4   : MipsGPRReg< 20, "20">,  DwarfRegNum<[20]>;
108  def S5   : MipsGPRReg< 21, "21">,  DwarfRegNum<[21]>;
109  def S6   : MipsGPRReg< 22, "22">,  DwarfRegNum<[22]>;
110  def S7   : MipsGPRReg< 23, "23">,  DwarfRegNum<[23]>;
111  def T8   : MipsGPRReg< 24, "24">,  DwarfRegNum<[24]>;
112  def T9   : MipsGPRReg< 25, "25">,  DwarfRegNum<[25]>;
113  def K0   : MipsGPRReg< 26, "26">,  DwarfRegNum<[26]>;
114  def K1   : MipsGPRReg< 27, "27">,  DwarfRegNum<[27]>;
115  def GP   : MipsGPRReg< 28, "gp">,  DwarfRegNum<[28]>;
116  def SP   : MipsGPRReg< 29, "sp">,  DwarfRegNum<[29]>;
117  def FP   : MipsGPRReg< 30, "fp">,  DwarfRegNum<[30]>;
118  def RA   : MipsGPRReg< 31, "ra">,  DwarfRegNum<[31]>;
119
120  // General Purpose 64-bit Registers
121  def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
122  def AT_64   : Mips64GPRReg< 1, "1",    [AT]>, DwarfRegNum<[1]>;
123  def V0_64   : Mips64GPRReg< 2, "2",    [V0]>, DwarfRegNum<[2]>;
124  def V1_64   : Mips64GPRReg< 3, "3",    [V1]>, DwarfRegNum<[3]>;
125  def A0_64   : Mips64GPRReg< 4, "4",    [A0]>, DwarfRegNum<[4]>;
126  def A1_64   : Mips64GPRReg< 5, "5",    [A1]>, DwarfRegNum<[5]>;
127  def A2_64   : Mips64GPRReg< 6, "6",    [A2]>, DwarfRegNum<[6]>;
128  def A3_64   : Mips64GPRReg< 7, "7",    [A3]>, DwarfRegNum<[7]>;
129  def T0_64   : Mips64GPRReg< 8, "8",    [T0]>, DwarfRegNum<[8]>;
130  def T1_64   : Mips64GPRReg< 9, "9",    [T1]>, DwarfRegNum<[9]>;
131  def T2_64   : Mips64GPRReg< 10, "10",  [T2]>, DwarfRegNum<[10]>;
132  def T3_64   : Mips64GPRReg< 11, "11",  [T3]>, DwarfRegNum<[11]>;
133  def T4_64   : Mips64GPRReg< 12, "12",  [T4]>, DwarfRegNum<[12]>;
134  def T5_64   : Mips64GPRReg< 13, "13",  [T5]>, DwarfRegNum<[13]>;
135  def T6_64   : Mips64GPRReg< 14, "14",  [T6]>, DwarfRegNum<[14]>;
136  def T7_64   : Mips64GPRReg< 15, "15",  [T7]>, DwarfRegNum<[15]>;
137  def S0_64   : Mips64GPRReg< 16, "16",  [S0]>, DwarfRegNum<[16]>;
138  def S1_64   : Mips64GPRReg< 17, "17",  [S1]>, DwarfRegNum<[17]>;
139  def S2_64   : Mips64GPRReg< 18, "18",  [S2]>, DwarfRegNum<[18]>;
140  def S3_64   : Mips64GPRReg< 19, "19",  [S3]>, DwarfRegNum<[19]>;
141  def S4_64   : Mips64GPRReg< 20, "20",  [S4]>, DwarfRegNum<[20]>;
142  def S5_64   : Mips64GPRReg< 21, "21",  [S5]>, DwarfRegNum<[21]>;
143  def S6_64   : Mips64GPRReg< 22, "22",  [S6]>, DwarfRegNum<[22]>;
144  def S7_64   : Mips64GPRReg< 23, "23",  [S7]>, DwarfRegNum<[23]>;
145  def T8_64   : Mips64GPRReg< 24, "24",  [T8]>, DwarfRegNum<[24]>;
146  def T9_64   : Mips64GPRReg< 25, "25",  [T9]>, DwarfRegNum<[25]>;
147  def K0_64   : Mips64GPRReg< 26, "26",  [K0]>, DwarfRegNum<[26]>;
148  def K1_64   : Mips64GPRReg< 27, "27",  [K1]>, DwarfRegNum<[27]>;
149  def GP_64   : Mips64GPRReg< 28, "gp",  [GP]>, DwarfRegNum<[28]>;
150  def SP_64   : Mips64GPRReg< 29, "sp",  [SP]>, DwarfRegNum<[29]>;
151  def FP_64   : Mips64GPRReg< 30, "fp",  [FP]>, DwarfRegNum<[30]>;
152  def RA_64   : Mips64GPRReg< 31, "ra",  [RA]>, DwarfRegNum<[31]>;
153
154  /// Mips Single point precision FPU Registers
155  foreach I = 0-31 in
156  def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
157
158  // Higher half of 64-bit FP registers.
159  foreach I = 0-31 in
160  def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>;
161
162  /// Mips Double point precision FPU Registers (aliased
163  /// with the single precision to hold 64 bit values)
164  foreach I = 0-15 in
165  def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1),
166                 [!cast<FPR>("F"#!shl(I, 1)),
167                  !cast<FPR>("F"#!add(!shl(I, 1), 1))]>;
168
169  /// Mips Double point precision FPU Registers in MFP64 mode.
170  foreach I = 0-31 in
171  def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>,
172                DwarfRegNum<[!add(I, 32)]>;
173
174  /// Mips MSA registers
175  /// MSA and FPU cannot both be present unless the FPU has 64-bit registers
176  foreach I = 0-31 in
177  def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>,
178            DwarfRegNum<[!add(I, 32)]>;
179
180  // Hi/Lo registers
181  def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>;
182  def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>;
183  def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>;
184  def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>;
185  def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>;
186  def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>;
187  def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>;
188  def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>;
189
190  let SubRegIndices = [sub_32] in {
191  def HI0_64  : RegisterWithSubRegs<"hi", [HI0]>;
192  def LO0_64  : RegisterWithSubRegs<"lo", [LO0]>;
193  }
194
195  // FP control registers.
196  foreach I = 0-31 in
197  def FCR#I : MipsReg<I, ""#I>;
198
199  // FP condition code registers.
200  foreach I = 0-7 in
201  def FCC#I : MipsReg<I, "fcc"#I>;
202
203  // COP0 registers.
204  foreach I = 0-31 in
205  def COP0#I : MipsReg<I, ""#I>;
206
207  // COP2 registers.
208  foreach I = 0-31 in
209  def COP2#I : MipsReg<I, ""#I>;
210
211  // COP3 registers.
212  foreach I = 0-31 in
213  def COP3#I : MipsReg<I, ""#I>;
214
215  // PC register
216  def PC : Register<"pc">;
217
218  // Hardware registers
219  def HWR0 : MipsReg<0, "hwr_cpunum">;
220  def HWR1 : MipsReg<1, "hwr_synci_step">;
221  def HWR2 : MipsReg<2, "hwr_cc">;
222  def HWR3 : MipsReg<3, "hwr_ccres">;
223
224  foreach I = 4-31 in
225  def HWR#I : MipsReg<I, ""#I>;
226
227  // Accum registers
228  foreach I = 0-3 in
229  def AC#I : ACCReg<I, "ac"#I,
230                    [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>;
231
232  def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>;
233
234  // DSP-ASE control register fields.
235  def DSPPos : Register<"">;
236  def DSPSCount : Register<"">;
237  def DSPCarry : Register<"">;
238  def DSPEFI : Register<"">;
239  def DSPOutFlag16_19 : Register<"">;
240  def DSPOutFlag20 : Register<"">;
241  def DSPOutFlag21 : Register<"">;
242  def DSPOutFlag22 : Register<"">;
243  def DSPOutFlag23 : Register<"">;
244  def DSPCCond : Register<"">;
245
246  let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22,
247                       sub_dsp23] in
248  def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20,
249                                            DSPOutFlag21, DSPOutFlag22,
250                                            DSPOutFlag23]>;
251
252  // MSA-ASE control registers.
253  def MSAIR      : MipsReg<0, "0">;
254  def MSACSR     : MipsReg<1, "1">;
255  def MSAAccess  : MipsReg<2, "2">;
256  def MSASave    : MipsReg<3, "3">;
257  def MSAModify  : MipsReg<4, "4">;
258  def MSARequest : MipsReg<5, "5">;
259  def MSAMap     : MipsReg<6, "6">;
260  def MSAUnmap   : MipsReg<7, "7">;
261  // MSA-ASE fake control registers.
262  // These registers do not exist, but instructions like `cfcmsa`
263  // and `ctcmsa` allows to specify them.
264  foreach I = 8-31 in
265  def MSA#I : MipsReg<I, ""#I>;
266
267  // Octeon multiplier and product registers
268  def MPL0 : MipsReg<0, "mpl0">;
269  def MPL1 : MipsReg<1, "mpl1">;
270  def MPL2 : MipsReg<2, "mpl2">;
271  def P0 : MipsReg<0, "p0">;
272  def P1 : MipsReg<1, "p1">;
273  def P2 : MipsReg<2, "p2">;
274
275}
276
277//===----------------------------------------------------------------------===//
278// Register Classes
279//===----------------------------------------------------------------------===//
280
281class GPR32Class<list<ValueType> regTypes> :
282  RegisterClass<"Mips", regTypes, 32, (add
283  // Reserved
284  ZERO, AT,
285  // Return Values and Arguments
286  V0, V1, A0, A1, A2, A3,
287  // Not preserved across procedure calls
288  T0, T1, T2, T3, T4, T5, T6, T7,
289  // Callee save
290  S0, S1, S2, S3, S4, S5, S6, S7,
291  // Not preserved across procedure calls
292  T8, T9,
293  // Reserved
294  K0, K1, GP, SP, FP, RA)>;
295
296def GPR32 : GPR32Class<[i32]>;
297
298def GPR32ZERO : RegisterClass<"Mips", [i32], 32, (add
299  // Reserved
300  ZERO)>;
301
302def GPR32NONZERO : RegisterClass<"Mips", [i32], 32, (add
303  // Reserved
304  AT,
305  // Return Values and Arguments
306  V0, V1, A0, A1, A2, A3,
307  // Not preserved across procedure calls
308  T0, T1, T2, T3, T4, T5, T6, T7,
309  // Callee save
310  S0, S1, S2, S3, S4, S5, S6, S7,
311  // Not preserved across procedure calls
312  T8, T9,
313  // Reserved
314  K0, K1, GP, SP, FP, RA)>;
315
316def DSPR  : GPR32Class<[v4i8, v2i16]>;
317
318def GPRMM16 : RegisterClass<"Mips", [i32], 32, (add
319  // Callee save
320  S0, S1,
321  // Return Values and Arguments
322  V0, V1, A0, A1, A2, A3)>;
323
324def GPRMM16Zero : RegisterClass<"Mips", [i32], 32, (add
325  // Reserved
326  ZERO,
327  // Callee save
328  S1,
329  // Return Values and Arguments
330  V0, V1, A0, A1, A2, A3)>;
331
332def GPRMM16MoveP : RegisterClass<"Mips", [i32], 32, (add
333  // Reserved
334  ZERO,
335  // Callee save
336  S1,
337  // Return Values and Arguments
338  V0, V1,
339  // Callee save
340  S0, S2, S3, S4)>;
341
342def GPRMM16MovePPairFirst : RegisterClass<"Mips", [i32], 32, (add
343  // Arguments
344  A0, A1, A2)>;
345
346def GPRMM16MovePPairSecond : RegisterClass<"Mips", [i32], 32, (add
347  // Arguments
348  A1, A2, A3,
349  // Callee save
350  S5, S6)>;
351
352def GPR64 : RegisterClass<"Mips", [i64], 64, (add
353  // Reserved
354  ZERO_64, AT_64,
355  // Return Values and Arguments
356  V0_64, V1_64, A0_64, A1_64, A2_64, A3_64,
357  // Not preserved across procedure calls
358  T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64,
359  // Callee save
360  S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64,
361  // Not preserved across procedure calls
362  T8_64, T9_64,
363  // Reserved
364  K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>;
365
366def CPU16Regs : RegisterClass<"Mips", [i32], 32, (add
367  // Return Values and Arguments
368  V0, V1, A0, A1, A2, A3,
369  // Callee save
370  S0, S1)>;
371
372def CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add
373  // Return Values and Arguments
374  V0, V1, A0, A1, A2, A3,
375  // Callee save
376  S0, S1,
377  SP)>;
378
379def CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable;
380
381def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
382
383// 64bit fp:
384// * FGR64  - 32 64-bit registers
385// * AFGR64 - 16 32-bit even registers (32-bit FP Mode)
386//
387// 32bit fp:
388// * FGR32 - 16 32-bit even registers
389// * FGR32 - 32 32-bit registers (single float only mode)
390def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)> {
391  // Do not allocate odd registers when given -mattr=+nooddspreg.
392  let AltOrders = [(decimate FGR32, 2)];
393  let AltOrderSelect = [{
394    const auto & S = MF.getSubtarget<MipsSubtarget>();
395    return S.isABI_O32() && !S.useOddSPReg();
396  }];
397}
398
399def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
400  // Return Values and Arguments
401  D0, D1,
402  // Not preserved across procedure calls
403  D2, D3, D4, D5,
404  // Return Values and Arguments
405  D6, D7,
406  // Not preserved across procedure calls
407  D8, D9,
408  // Callee save
409  D10, D11, D12, D13, D14, D15)>;
410
411def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)> {
412  // Do not allocate odd registers when given -mattr=+nooddspreg.
413  let AltOrders = [(decimate FGR64, 2)];
414  let AltOrderSelect = [{
415    const auto & S = MF.getSubtarget<MipsSubtarget>();
416    return S.isABI_O32() && !S.useOddSPReg();
417  }];
418}
419
420// FP control registers.
421def CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>,
422          Unallocatable;
423
424// FP condition code registers.
425def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>,
426          Unallocatable;
427
428// MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers.
429// This class allows us to represent this in codegen patterns.
430def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>;
431
432def MSA128F16 : RegisterClass<"Mips", [f16], 128, (sequence "W%u", 0, 31)>;
433
434def MSA128B: RegisterClass<"Mips", [v16i8], 128,
435                           (sequence "W%u", 0, 31)>;
436def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128,
437                           (sequence "W%u", 0, 31)>;
438def MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128,
439                           (sequence "W%u", 0, 31)>;
440def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
441                           (sequence "W%u", 0, 31)>;
442def MSA128WEvens: RegisterClass<"Mips", [v4i32, v4f32], 128,
443                                (decimate (sequence "W%u", 0, 31), 2)>;
444
445def MSACtrl: RegisterClass<"Mips", [i32], 32, (add
446  MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap,
447  (sequence "MSA%u", 8, 31))>, Unallocatable;
448
449// Hi/Lo Registers
450def LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>;
451def HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>;
452def LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>;
453def HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>;
454def LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>;
455def HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>;
456
457// Hardware registers
458def HWRegs : RegisterClass<"Mips", [i32], 32, (sequence "HWR%u", 0, 31)>,
459             Unallocatable;
460
461// Accumulator Registers
462def ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> {
463  let Size = 64;
464}
465
466def ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> {
467  let Size = 128;
468}
469
470def ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> {
471  let Size = 64;
472}
473
474def DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>;
475
476// Coprocessor 0 registers.
477def COP0 : RegisterClass<"Mips", [i32], 32, (sequence "COP0%u", 0, 31)>,
478           Unallocatable;
479
480// Coprocessor 2 registers.
481def COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>,
482           Unallocatable;
483
484// Coprocessor 3 registers.
485def COP3 : RegisterClass<"Mips", [i32], 32, (sequence "COP3%u", 0, 31)>,
486           Unallocatable;
487
488// Stack pointer and global pointer classes for instructions that are limited
489// to a single register such as lwgp/lwsp in microMIPS.
490def SP32 : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
491def SP64 : RegisterClass<"Mips", [i64], 64, (add SP_64)>, Unallocatable;
492def GP32 : RegisterClass<"Mips", [i32], 32, (add GP)>, Unallocatable;
493def GP64 : RegisterClass<"Mips", [i64], 64, (add GP_64)>, Unallocatable;
494
495// Octeon multiplier and product registers
496def OCTEON_MPL : RegisterClass<"Mips", [i64], 64, (add MPL0, MPL1, MPL2)>,
497                 Unallocatable;
498def OCTEON_P : RegisterClass<"Mips", [i64], 64, (add P0, P1, P2)>,
499               Unallocatable;
500
501// Register Operands.
502
503class MipsAsmRegOperand : AsmOperandClass {
504  let ParserMethod = "parseAnyRegister";
505}
506
507def GPR64AsmOperand : MipsAsmRegOperand {
508  let Name = "GPR64AsmReg";
509  let PredicateMethod = "isGPRAsmReg";
510}
511
512def GPR32ZeroAsmOperand : MipsAsmRegOperand {
513  let Name = "GPR32ZeroAsmReg";
514  let PredicateMethod = "isGPRZeroAsmReg";
515}
516
517def GPR32NonZeroAsmOperand : MipsAsmRegOperand {
518  let Name = "GPR32NonZeroAsmReg";
519  let PredicateMethod = "isGPRNonZeroAsmReg";
520}
521
522def GPR32AsmOperand : MipsAsmRegOperand {
523  let Name = "GPR32AsmReg";
524  let PredicateMethod = "isGPRAsmReg";
525}
526
527def GPRMM16AsmOperand : MipsAsmRegOperand {
528  let Name = "GPRMM16AsmReg";
529  let PredicateMethod = "isMM16AsmReg";
530}
531
532def GPRMM16AsmOperandZero : MipsAsmRegOperand {
533  let Name = "GPRMM16AsmRegZero";
534  let PredicateMethod = "isMM16AsmRegZero";
535}
536
537def GPRMM16AsmOperandMoveP : MipsAsmRegOperand {
538  let Name = "GPRMM16AsmRegMoveP";
539  let PredicateMethod = "isMM16AsmRegMoveP";
540}
541
542def GPRMM16AsmOperandMovePPairFirst : MipsAsmRegOperand {
543  let Name = "GPRMM16AsmRegMovePPairFirst";
544  let PredicateMethod = "isMM16AsmRegMovePPairFirst";
545}
546
547def GPRMM16AsmOperandMovePPairSecond : MipsAsmRegOperand {
548  let Name = "GPRMM16AsmRegMovePPairSecond";
549  let PredicateMethod = "isMM16AsmRegMovePPairSecond";
550}
551
552def ACC64DSPAsmOperand : MipsAsmRegOperand {
553  let Name = "ACC64DSPAsmReg";
554  let PredicateMethod = "isACCAsmReg";
555}
556
557def HI32DSPAsmOperand : MipsAsmRegOperand {
558  let Name = "HI32DSPAsmReg";
559  let PredicateMethod = "isACCAsmReg";
560}
561
562def LO32DSPAsmOperand : MipsAsmRegOperand {
563  let Name = "LO32DSPAsmReg";
564  let PredicateMethod = "isACCAsmReg";
565}
566
567def CCRAsmOperand : MipsAsmRegOperand {
568  let Name = "CCRAsmReg";
569}
570
571def AFGR64AsmOperand : MipsAsmRegOperand {
572  let Name = "AFGR64AsmReg";
573  let PredicateMethod = "isFGRAsmReg";
574}
575
576def StrictlyAFGR64AsmOperand : MipsAsmRegOperand {
577  let Name = "StrictlyAFGR64AsmReg";
578  let PredicateMethod = "isStrictlyFGRAsmReg";
579}
580
581def FGR64AsmOperand : MipsAsmRegOperand {
582  let Name = "FGR64AsmReg";
583  let PredicateMethod = "isFGRAsmReg";
584}
585
586def StrictlyFGR64AsmOperand : MipsAsmRegOperand {
587  let Name = "StrictlyFGR64AsmReg";
588  let PredicateMethod = "isStrictlyFGRAsmReg";
589}
590
591def FGR32AsmOperand : MipsAsmRegOperand {
592  let Name = "FGR32AsmReg";
593  let PredicateMethod = "isFGRAsmReg";
594}
595
596def StrictlyFGR32AsmOperand : MipsAsmRegOperand {
597  let Name = "StrictlyFGR32AsmReg";
598  let PredicateMethod = "isStrictlyFGRAsmReg";
599}
600
601def FCCRegsAsmOperand : MipsAsmRegOperand {
602  let Name = "FCCAsmReg";
603}
604
605def MSA128AsmOperand : MipsAsmRegOperand {
606  let Name = "MSA128AsmReg";
607}
608
609def MSACtrlAsmOperand : MipsAsmRegOperand {
610  let Name = "MSACtrlAsmReg";
611}
612
613def GPR32ZeroOpnd : RegisterOperand<GPR32ZERO> {
614  let ParserMatchClass = GPR32ZeroAsmOperand;
615}
616
617def GPR32NonZeroOpnd : RegisterOperand<GPR32NONZERO> {
618  let ParserMatchClass = GPR32NonZeroAsmOperand;
619}
620
621def GPR32Opnd : RegisterOperand<GPR32> {
622  let ParserMatchClass = GPR32AsmOperand;
623}
624
625def GPRMM16Opnd : RegisterOperand<GPRMM16> {
626  let ParserMatchClass = GPRMM16AsmOperand;
627}
628
629def GPRMM16OpndZero : RegisterOperand<GPRMM16Zero> {
630  let ParserMatchClass = GPRMM16AsmOperandZero;
631}
632
633def GPRMM16OpndMoveP : RegisterOperand<GPRMM16MoveP> {
634  let ParserMatchClass = GPRMM16AsmOperandMoveP;
635  let EncoderMethod = "getMovePRegSingleOpValue";
636}
637
638def GPRMM16OpndMovePPairFirst : RegisterOperand<GPRMM16MovePPairFirst> {
639  let ParserMatchClass = GPRMM16AsmOperandMovePPairFirst;
640}
641
642def GPRMM16OpndMovePPairSecond : RegisterOperand<GPRMM16MovePPairSecond> {
643  let ParserMatchClass = GPRMM16AsmOperandMovePPairSecond;
644}
645
646def GPR64Opnd : RegisterOperand<GPR64> {
647  let ParserMatchClass = GPR64AsmOperand;
648}
649
650def DSPROpnd : RegisterOperand<DSPR> {
651  let ParserMatchClass = GPR32AsmOperand;
652}
653
654def CCROpnd : RegisterOperand<CCR> {
655  let ParserMatchClass = CCRAsmOperand;
656}
657
658def HWRegsAsmOperand : MipsAsmRegOperand {
659  let Name = "HWRegsAsmReg";
660}
661
662def COP0AsmOperand : MipsAsmRegOperand {
663  let Name = "COP0AsmReg";
664}
665
666def COP2AsmOperand : MipsAsmRegOperand {
667  let Name = "COP2AsmReg";
668}
669
670def COP3AsmOperand : MipsAsmRegOperand {
671  let Name = "COP3AsmReg";
672}
673
674def HWRegsOpnd : RegisterOperand<HWRegs> {
675  let ParserMatchClass = HWRegsAsmOperand;
676}
677
678def AFGR64Opnd : RegisterOperand<AFGR64> {
679  let ParserMatchClass = AFGR64AsmOperand;
680}
681
682def StrictlyAFGR64Opnd : RegisterOperand<AFGR64> {
683  let ParserMatchClass = StrictlyAFGR64AsmOperand;
684}
685
686def FGR64Opnd : RegisterOperand<FGR64> {
687  let ParserMatchClass = FGR64AsmOperand;
688}
689
690def StrictlyFGR64Opnd : RegisterOperand<FGR64> {
691  let ParserMatchClass = StrictlyFGR64AsmOperand;
692}
693
694def FGR32Opnd : RegisterOperand<FGR32> {
695  let ParserMatchClass = FGR32AsmOperand;
696}
697
698def StrictlyFGR32Opnd : RegisterOperand<FGR32> {
699  let ParserMatchClass = StrictlyFGR32AsmOperand;
700}
701
702def FGRCCOpnd : RegisterOperand<FGRCC> {
703  // The assembler doesn't use register classes so we can re-use
704  // FGR32AsmOperand.
705  let ParserMatchClass = FGR32AsmOperand;
706}
707
708def FCCRegsOpnd : RegisterOperand<FCC> {
709  let ParserMatchClass = FCCRegsAsmOperand;
710}
711
712def LO32DSPOpnd : RegisterOperand<LO32DSP> {
713  let ParserMatchClass = LO32DSPAsmOperand;
714}
715
716def HI32DSPOpnd : RegisterOperand<HI32DSP> {
717  let ParserMatchClass = HI32DSPAsmOperand;
718}
719
720def ACC64DSPOpnd : RegisterOperand<ACC64DSP> {
721  let ParserMatchClass = ACC64DSPAsmOperand;
722}
723
724def COP0Opnd : RegisterOperand<COP0> {
725  let ParserMatchClass = COP0AsmOperand;
726}
727
728def COP2Opnd : RegisterOperand<COP2> {
729  let ParserMatchClass = COP2AsmOperand;
730}
731
732def COP3Opnd : RegisterOperand<COP3> {
733  let ParserMatchClass = COP3AsmOperand;
734}
735
736def MSA128F16Opnd : RegisterOperand<MSA128F16> {
737  let ParserMatchClass = MSA128AsmOperand;
738}
739
740def MSA128BOpnd : RegisterOperand<MSA128B> {
741  let ParserMatchClass = MSA128AsmOperand;
742}
743
744def MSA128HOpnd : RegisterOperand<MSA128H> {
745  let ParserMatchClass = MSA128AsmOperand;
746}
747
748def MSA128WOpnd : RegisterOperand<MSA128W> {
749  let ParserMatchClass = MSA128AsmOperand;
750}
751
752def MSA128DOpnd : RegisterOperand<MSA128D> {
753  let ParserMatchClass = MSA128AsmOperand;
754}
755
756def MSA128CROpnd : RegisterOperand<MSACtrl> {
757  let ParserMatchClass = MSACtrlAsmOperand;
758}
759