1 //===- SparcDisassembler.cpp - Disassembler for Sparc -----------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file is part of the Sparc Disassembler.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #include "MCTargetDesc/SparcMCTargetDesc.h"
14 #include "TargetInfo/SparcTargetInfo.h"
15 #include "llvm/MC/MCAsmInfo.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/Support/TargetRegistry.h"
21
22 using namespace llvm;
23
24 #define DEBUG_TYPE "sparc-disassembler"
25
26 typedef MCDisassembler::DecodeStatus DecodeStatus;
27
28 namespace {
29
30 /// A disassembler class for Sparc.
31 class SparcDisassembler : public MCDisassembler {
32 public:
SparcDisassembler(const MCSubtargetInfo & STI,MCContext & Ctx)33 SparcDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
34 : MCDisassembler(STI, Ctx) {}
~SparcDisassembler()35 virtual ~SparcDisassembler() {}
36
37 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
38 ArrayRef<uint8_t> Bytes, uint64_t Address,
39 raw_ostream &CStream) const override;
40 };
41 }
42
createSparcDisassembler(const Target & T,const MCSubtargetInfo & STI,MCContext & Ctx)43 static MCDisassembler *createSparcDisassembler(const Target &T,
44 const MCSubtargetInfo &STI,
45 MCContext &Ctx) {
46 return new SparcDisassembler(STI, Ctx);
47 }
48
49
LLVMInitializeSparcDisassembler()50 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSparcDisassembler() {
51 // Register the disassembler.
52 TargetRegistry::RegisterMCDisassembler(getTheSparcTarget(),
53 createSparcDisassembler);
54 TargetRegistry::RegisterMCDisassembler(getTheSparcV9Target(),
55 createSparcDisassembler);
56 TargetRegistry::RegisterMCDisassembler(getTheSparcelTarget(),
57 createSparcDisassembler);
58 }
59
60 static const unsigned IntRegDecoderTable[] = {
61 SP::G0, SP::G1, SP::G2, SP::G3,
62 SP::G4, SP::G5, SP::G6, SP::G7,
63 SP::O0, SP::O1, SP::O2, SP::O3,
64 SP::O4, SP::O5, SP::O6, SP::O7,
65 SP::L0, SP::L1, SP::L2, SP::L3,
66 SP::L4, SP::L5, SP::L6, SP::L7,
67 SP::I0, SP::I1, SP::I2, SP::I3,
68 SP::I4, SP::I5, SP::I6, SP::I7 };
69
70 static const unsigned FPRegDecoderTable[] = {
71 SP::F0, SP::F1, SP::F2, SP::F3,
72 SP::F4, SP::F5, SP::F6, SP::F7,
73 SP::F8, SP::F9, SP::F10, SP::F11,
74 SP::F12, SP::F13, SP::F14, SP::F15,
75 SP::F16, SP::F17, SP::F18, SP::F19,
76 SP::F20, SP::F21, SP::F22, SP::F23,
77 SP::F24, SP::F25, SP::F26, SP::F27,
78 SP::F28, SP::F29, SP::F30, SP::F31 };
79
80 static const unsigned DFPRegDecoderTable[] = {
81 SP::D0, SP::D16, SP::D1, SP::D17,
82 SP::D2, SP::D18, SP::D3, SP::D19,
83 SP::D4, SP::D20, SP::D5, SP::D21,
84 SP::D6, SP::D22, SP::D7, SP::D23,
85 SP::D8, SP::D24, SP::D9, SP::D25,
86 SP::D10, SP::D26, SP::D11, SP::D27,
87 SP::D12, SP::D28, SP::D13, SP::D29,
88 SP::D14, SP::D30, SP::D15, SP::D31 };
89
90 static const unsigned QFPRegDecoderTable[] = {
91 SP::Q0, SP::Q8, ~0U, ~0U,
92 SP::Q1, SP::Q9, ~0U, ~0U,
93 SP::Q2, SP::Q10, ~0U, ~0U,
94 SP::Q3, SP::Q11, ~0U, ~0U,
95 SP::Q4, SP::Q12, ~0U, ~0U,
96 SP::Q5, SP::Q13, ~0U, ~0U,
97 SP::Q6, SP::Q14, ~0U, ~0U,
98 SP::Q7, SP::Q15, ~0U, ~0U } ;
99
100 static const unsigned FCCRegDecoderTable[] = {
101 SP::FCC0, SP::FCC1, SP::FCC2, SP::FCC3 };
102
103 static const unsigned ASRRegDecoderTable[] = {
104 SP::Y, SP::ASR1, SP::ASR2, SP::ASR3,
105 SP::ASR4, SP::ASR5, SP::ASR6, SP::ASR7,
106 SP::ASR8, SP::ASR9, SP::ASR10, SP::ASR11,
107 SP::ASR12, SP::ASR13, SP::ASR14, SP::ASR15,
108 SP::ASR16, SP::ASR17, SP::ASR18, SP::ASR19,
109 SP::ASR20, SP::ASR21, SP::ASR22, SP::ASR23,
110 SP::ASR24, SP::ASR25, SP::ASR26, SP::ASR27,
111 SP::ASR28, SP::ASR29, SP::ASR30, SP::ASR31};
112
113 static const unsigned PRRegDecoderTable[] = {
114 SP::TPC, SP::TNPC, SP::TSTATE, SP::TT, SP::TICK, SP::TBA, SP::PSTATE,
115 SP::TL, SP::PIL, SP::CWP, SP::CANSAVE, SP::CANRESTORE, SP::CLEANWIN,
116 SP::OTHERWIN, SP::WSTATE, SP::PC
117 };
118
119 static const uint16_t IntPairDecoderTable[] = {
120 SP::G0_G1, SP::G2_G3, SP::G4_G5, SP::G6_G7,
121 SP::O0_O1, SP::O2_O3, SP::O4_O5, SP::O6_O7,
122 SP::L0_L1, SP::L2_L3, SP::L4_L5, SP::L6_L7,
123 SP::I0_I1, SP::I2_I3, SP::I4_I5, SP::I6_I7,
124 };
125
126 static const unsigned CPRegDecoderTable[] = {
127 SP::C0, SP::C1, SP::C2, SP::C3,
128 SP::C4, SP::C5, SP::C6, SP::C7,
129 SP::C8, SP::C9, SP::C10, SP::C11,
130 SP::C12, SP::C13, SP::C14, SP::C15,
131 SP::C16, SP::C17, SP::C18, SP::C19,
132 SP::C20, SP::C21, SP::C22, SP::C23,
133 SP::C24, SP::C25, SP::C26, SP::C27,
134 SP::C28, SP::C29, SP::C30, SP::C31
135 };
136
137
138 static const uint16_t CPPairDecoderTable[] = {
139 SP::C0_C1, SP::C2_C3, SP::C4_C5, SP::C6_C7,
140 SP::C8_C9, SP::C10_C11, SP::C12_C13, SP::C14_C15,
141 SP::C16_C17, SP::C18_C19, SP::C20_C21, SP::C22_C23,
142 SP::C24_C25, SP::C26_C27, SP::C28_C29, SP::C30_C31
143 };
144
DecodeIntRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)145 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst,
146 unsigned RegNo,
147 uint64_t Address,
148 const void *Decoder) {
149 if (RegNo > 31)
150 return MCDisassembler::Fail;
151 unsigned Reg = IntRegDecoderTable[RegNo];
152 Inst.addOperand(MCOperand::createReg(Reg));
153 return MCDisassembler::Success;
154 }
155
DecodeI64RegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)156 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst,
157 unsigned RegNo,
158 uint64_t Address,
159 const void *Decoder) {
160 if (RegNo > 31)
161 return MCDisassembler::Fail;
162 unsigned Reg = IntRegDecoderTable[RegNo];
163 Inst.addOperand(MCOperand::createReg(Reg));
164 return MCDisassembler::Success;
165 }
166
167
DecodeFPRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)168 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst,
169 unsigned RegNo,
170 uint64_t Address,
171 const void *Decoder) {
172 if (RegNo > 31)
173 return MCDisassembler::Fail;
174 unsigned Reg = FPRegDecoderTable[RegNo];
175 Inst.addOperand(MCOperand::createReg(Reg));
176 return MCDisassembler::Success;
177 }
178
179
DecodeDFPRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)180 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst,
181 unsigned RegNo,
182 uint64_t Address,
183 const void *Decoder) {
184 if (RegNo > 31)
185 return MCDisassembler::Fail;
186 unsigned Reg = DFPRegDecoderTable[RegNo];
187 Inst.addOperand(MCOperand::createReg(Reg));
188 return MCDisassembler::Success;
189 }
190
191
DecodeQFPRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)192 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst,
193 unsigned RegNo,
194 uint64_t Address,
195 const void *Decoder) {
196 if (RegNo > 31)
197 return MCDisassembler::Fail;
198
199 unsigned Reg = QFPRegDecoderTable[RegNo];
200 if (Reg == ~0U)
201 return MCDisassembler::Fail;
202 Inst.addOperand(MCOperand::createReg(Reg));
203 return MCDisassembler::Success;
204 }
205
DecodeCPRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)206 static DecodeStatus DecodeCPRegsRegisterClass(MCInst &Inst,
207 unsigned RegNo,
208 uint64_t Address,
209 const void *Decoder) {
210 if (RegNo > 31)
211 return MCDisassembler::Fail;
212 unsigned Reg = CPRegDecoderTable[RegNo];
213 Inst.addOperand(MCOperand::createReg(Reg));
214 return MCDisassembler::Success;
215 }
216
DecodeFCCRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)217 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo,
218 uint64_t Address,
219 const void *Decoder) {
220 if (RegNo > 3)
221 return MCDisassembler::Fail;
222 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo]));
223 return MCDisassembler::Success;
224 }
225
DecodeASRRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)226 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
227 uint64_t Address,
228 const void *Decoder) {
229 if (RegNo > 31)
230 return MCDisassembler::Fail;
231 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo]));
232 return MCDisassembler::Success;
233 }
234
DecodePRRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)235 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo,
236 uint64_t Address,
237 const void *Decoder) {
238 if (RegNo >= array_lengthof(PRRegDecoderTable))
239 return MCDisassembler::Fail;
240 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo]));
241 return MCDisassembler::Success;
242 }
243
DecodeIntPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)244 static DecodeStatus DecodeIntPairRegisterClass(MCInst &Inst, unsigned RegNo,
245 uint64_t Address, const void *Decoder) {
246 DecodeStatus S = MCDisassembler::Success;
247
248 if (RegNo > 31)
249 return MCDisassembler::Fail;
250
251 if ((RegNo & 1))
252 S = MCDisassembler::SoftFail;
253
254 unsigned RegisterPair = IntPairDecoderTable[RegNo/2];
255 Inst.addOperand(MCOperand::createReg(RegisterPair));
256 return S;
257 }
258
DecodeCPPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder)259 static DecodeStatus DecodeCPPairRegisterClass(MCInst &Inst, unsigned RegNo,
260 uint64_t Address, const void *Decoder) {
261 if (RegNo > 31)
262 return MCDisassembler::Fail;
263
264 unsigned RegisterPair = CPPairDecoderTable[RegNo/2];
265 Inst.addOperand(MCOperand::createReg(RegisterPair));
266 return MCDisassembler::Success;
267 }
268
269 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
270 const void *Decoder);
271 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
272 const void *Decoder);
273 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
274 const void *Decoder);
275 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
276 const void *Decoder);
277 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
278 const void *Decoder);
279 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
280 const void *Decoder);
281 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
282 const void *Decoder);
283 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeCall(MCInst &Inst, unsigned insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeSIMM13(MCInst &Inst, unsigned insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeJMPL(MCInst &Inst, unsigned insn, uint64_t Address,
302 const void *Decoder);
303 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
304 const void *Decoder);
305 static DecodeStatus DecodeSWAP(MCInst &Inst, unsigned insn, uint64_t Address,
306 const void *Decoder);
307 static DecodeStatus DecodeTRAP(MCInst &Inst, unsigned insn, uint64_t Address,
308 const void *Decoder);
309
310 #include "SparcGenDisassemblerTables.inc"
311
312 /// Read four bytes from the ArrayRef and return 32 bit word.
readInstruction32(ArrayRef<uint8_t> Bytes,uint64_t Address,uint64_t & Size,uint32_t & Insn,bool IsLittleEndian)313 static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
314 uint64_t &Size, uint32_t &Insn,
315 bool IsLittleEndian) {
316 // We want to read exactly 4 Bytes of data.
317 if (Bytes.size() < 4) {
318 Size = 0;
319 return MCDisassembler::Fail;
320 }
321
322 Insn = IsLittleEndian
323 ? (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
324 (Bytes[3] << 24)
325 : (Bytes[3] << 0) | (Bytes[2] << 8) | (Bytes[1] << 16) |
326 (Bytes[0] << 24);
327
328 return MCDisassembler::Success;
329 }
330
getInstruction(MCInst & Instr,uint64_t & Size,ArrayRef<uint8_t> Bytes,uint64_t Address,raw_ostream & CStream) const331 DecodeStatus SparcDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
332 ArrayRef<uint8_t> Bytes,
333 uint64_t Address,
334 raw_ostream &CStream) const {
335 uint32_t Insn;
336 bool isLittleEndian = getContext().getAsmInfo()->isLittleEndian();
337 DecodeStatus Result =
338 readInstruction32(Bytes, Address, Size, Insn, isLittleEndian);
339 if (Result == MCDisassembler::Fail)
340 return MCDisassembler::Fail;
341
342 // Calling the auto-generated decoder function.
343
344 if (STI.getFeatureBits()[Sparc::FeatureV9])
345 {
346 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
347 }
348 else
349 {
350 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
351 }
352 if (Result != MCDisassembler::Fail)
353 return Result;
354
355 Result =
356 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
357
358 if (Result != MCDisassembler::Fail) {
359 Size = 4;
360 return Result;
361 }
362
363 return MCDisassembler::Fail;
364 }
365
366
367 typedef DecodeStatus (*DecodeFunc)(MCInst &MI, unsigned insn, uint64_t Address,
368 const void *Decoder);
369
DecodeMem(MCInst & MI,unsigned insn,uint64_t Address,const void * Decoder,bool isLoad,DecodeFunc DecodeRD)370 static DecodeStatus DecodeMem(MCInst &MI, unsigned insn, uint64_t Address,
371 const void *Decoder,
372 bool isLoad, DecodeFunc DecodeRD) {
373 unsigned rd = fieldFromInstruction(insn, 25, 5);
374 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
375 bool isImm = fieldFromInstruction(insn, 13, 1);
376 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
377 unsigned asi = fieldFromInstruction(insn, 5, 8);
378 unsigned rs2 = 0;
379 unsigned simm13 = 0;
380 if (isImm)
381 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
382 else
383 rs2 = fieldFromInstruction(insn, 0, 5);
384
385 DecodeStatus status;
386 if (isLoad) {
387 status = DecodeRD(MI, rd, Address, Decoder);
388 if (status != MCDisassembler::Success)
389 return status;
390 }
391
392 // Decode rs1.
393 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
394 if (status != MCDisassembler::Success)
395 return status;
396
397 // Decode imm|rs2.
398 if (isImm)
399 MI.addOperand(MCOperand::createImm(simm13));
400 else {
401 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
402 if (status != MCDisassembler::Success)
403 return status;
404 }
405
406 if (hasAsi)
407 MI.addOperand(MCOperand::createImm(asi));
408
409 if (!isLoad) {
410 status = DecodeRD(MI, rd, Address, Decoder);
411 if (status != MCDisassembler::Success)
412 return status;
413 }
414 return MCDisassembler::Success;
415 }
416
DecodeLoadInt(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)417 static DecodeStatus DecodeLoadInt(MCInst &Inst, unsigned insn, uint64_t Address,
418 const void *Decoder) {
419 return DecodeMem(Inst, insn, Address, Decoder, true,
420 DecodeIntRegsRegisterClass);
421 }
422
DecodeLoadIntPair(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)423 static DecodeStatus DecodeLoadIntPair(MCInst &Inst, unsigned insn, uint64_t Address,
424 const void *Decoder) {
425 return DecodeMem(Inst, insn, Address, Decoder, true,
426 DecodeIntPairRegisterClass);
427 }
428
DecodeLoadFP(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)429 static DecodeStatus DecodeLoadFP(MCInst &Inst, unsigned insn, uint64_t Address,
430 const void *Decoder) {
431 return DecodeMem(Inst, insn, Address, Decoder, true,
432 DecodeFPRegsRegisterClass);
433 }
434
DecodeLoadDFP(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)435 static DecodeStatus DecodeLoadDFP(MCInst &Inst, unsigned insn, uint64_t Address,
436 const void *Decoder) {
437 return DecodeMem(Inst, insn, Address, Decoder, true,
438 DecodeDFPRegsRegisterClass);
439 }
440
DecodeLoadQFP(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)441 static DecodeStatus DecodeLoadQFP(MCInst &Inst, unsigned insn, uint64_t Address,
442 const void *Decoder) {
443 return DecodeMem(Inst, insn, Address, Decoder, true,
444 DecodeQFPRegsRegisterClass);
445 }
446
DecodeLoadCP(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)447 static DecodeStatus DecodeLoadCP(MCInst &Inst, unsigned insn, uint64_t Address,
448 const void *Decoder) {
449 return DecodeMem(Inst, insn, Address, Decoder, true,
450 DecodeCPRegsRegisterClass);
451 }
452
DecodeLoadCPPair(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)453 static DecodeStatus DecodeLoadCPPair(MCInst &Inst, unsigned insn, uint64_t Address,
454 const void *Decoder) {
455 return DecodeMem(Inst, insn, Address, Decoder, true,
456 DecodeCPPairRegisterClass);
457 }
458
DecodeStoreInt(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)459 static DecodeStatus DecodeStoreInt(MCInst &Inst, unsigned insn,
460 uint64_t Address, const void *Decoder) {
461 return DecodeMem(Inst, insn, Address, Decoder, false,
462 DecodeIntRegsRegisterClass);
463 }
464
DecodeStoreIntPair(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)465 static DecodeStatus DecodeStoreIntPair(MCInst &Inst, unsigned insn,
466 uint64_t Address, const void *Decoder) {
467 return DecodeMem(Inst, insn, Address, Decoder, false,
468 DecodeIntPairRegisterClass);
469 }
470
DecodeStoreFP(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)471 static DecodeStatus DecodeStoreFP(MCInst &Inst, unsigned insn, uint64_t Address,
472 const void *Decoder) {
473 return DecodeMem(Inst, insn, Address, Decoder, false,
474 DecodeFPRegsRegisterClass);
475 }
476
DecodeStoreDFP(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)477 static DecodeStatus DecodeStoreDFP(MCInst &Inst, unsigned insn,
478 uint64_t Address, const void *Decoder) {
479 return DecodeMem(Inst, insn, Address, Decoder, false,
480 DecodeDFPRegsRegisterClass);
481 }
482
DecodeStoreQFP(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)483 static DecodeStatus DecodeStoreQFP(MCInst &Inst, unsigned insn,
484 uint64_t Address, const void *Decoder) {
485 return DecodeMem(Inst, insn, Address, Decoder, false,
486 DecodeQFPRegsRegisterClass);
487 }
488
DecodeStoreCP(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)489 static DecodeStatus DecodeStoreCP(MCInst &Inst, unsigned insn,
490 uint64_t Address, const void *Decoder) {
491 return DecodeMem(Inst, insn, Address, Decoder, false,
492 DecodeCPRegsRegisterClass);
493 }
494
DecodeStoreCPPair(MCInst & Inst,unsigned insn,uint64_t Address,const void * Decoder)495 static DecodeStatus DecodeStoreCPPair(MCInst &Inst, unsigned insn,
496 uint64_t Address, const void *Decoder) {
497 return DecodeMem(Inst, insn, Address, Decoder, false,
498 DecodeCPPairRegisterClass);
499 }
500
tryAddingSymbolicOperand(int64_t Value,bool isBranch,uint64_t Address,uint64_t Offset,uint64_t Width,MCInst & MI,const void * Decoder)501 static bool tryAddingSymbolicOperand(int64_t Value, bool isBranch,
502 uint64_t Address, uint64_t Offset,
503 uint64_t Width, MCInst &MI,
504 const void *Decoder) {
505 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
506 return Dis->tryAddingSymbolicOperand(MI, Value, Address, isBranch,
507 Offset, Width);
508 }
509
DecodeCall(MCInst & MI,unsigned insn,uint64_t Address,const void * Decoder)510 static DecodeStatus DecodeCall(MCInst &MI, unsigned insn,
511 uint64_t Address, const void *Decoder) {
512 unsigned tgt = fieldFromInstruction(insn, 0, 30);
513 tgt <<= 2;
514 if (!tryAddingSymbolicOperand(tgt+Address, false, Address,
515 0, 30, MI, Decoder))
516 MI.addOperand(MCOperand::createImm(tgt));
517 return MCDisassembler::Success;
518 }
519
DecodeSIMM13(MCInst & MI,unsigned insn,uint64_t Address,const void * Decoder)520 static DecodeStatus DecodeSIMM13(MCInst &MI, unsigned insn,
521 uint64_t Address, const void *Decoder) {
522 unsigned tgt = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
523 MI.addOperand(MCOperand::createImm(tgt));
524 return MCDisassembler::Success;
525 }
526
DecodeJMPL(MCInst & MI,unsigned insn,uint64_t Address,const void * Decoder)527 static DecodeStatus DecodeJMPL(MCInst &MI, unsigned insn, uint64_t Address,
528 const void *Decoder) {
529
530 unsigned rd = fieldFromInstruction(insn, 25, 5);
531 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
532 unsigned isImm = fieldFromInstruction(insn, 13, 1);
533 unsigned rs2 = 0;
534 unsigned simm13 = 0;
535 if (isImm)
536 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
537 else
538 rs2 = fieldFromInstruction(insn, 0, 5);
539
540 // Decode RD.
541 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
542 if (status != MCDisassembler::Success)
543 return status;
544
545 // Decode RS1.
546 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
547 if (status != MCDisassembler::Success)
548 return status;
549
550 // Decode RS1 | SIMM13.
551 if (isImm)
552 MI.addOperand(MCOperand::createImm(simm13));
553 else {
554 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
555 if (status != MCDisassembler::Success)
556 return status;
557 }
558 return MCDisassembler::Success;
559 }
560
DecodeReturn(MCInst & MI,unsigned insn,uint64_t Address,const void * Decoder)561 static DecodeStatus DecodeReturn(MCInst &MI, unsigned insn, uint64_t Address,
562 const void *Decoder) {
563
564 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
565 unsigned isImm = fieldFromInstruction(insn, 13, 1);
566 unsigned rs2 = 0;
567 unsigned simm13 = 0;
568 if (isImm)
569 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
570 else
571 rs2 = fieldFromInstruction(insn, 0, 5);
572
573 // Decode RS1.
574 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
575 if (status != MCDisassembler::Success)
576 return status;
577
578 // Decode RS2 | SIMM13.
579 if (isImm)
580 MI.addOperand(MCOperand::createImm(simm13));
581 else {
582 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
583 if (status != MCDisassembler::Success)
584 return status;
585 }
586 return MCDisassembler::Success;
587 }
588
DecodeSWAP(MCInst & MI,unsigned insn,uint64_t Address,const void * Decoder)589 static DecodeStatus DecodeSWAP(MCInst &MI, unsigned insn, uint64_t Address,
590 const void *Decoder) {
591
592 unsigned rd = fieldFromInstruction(insn, 25, 5);
593 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
594 unsigned isImm = fieldFromInstruction(insn, 13, 1);
595 bool hasAsi = fieldFromInstruction(insn, 23, 1); // (in op3 field)
596 unsigned asi = fieldFromInstruction(insn, 5, 8);
597 unsigned rs2 = 0;
598 unsigned simm13 = 0;
599 if (isImm)
600 simm13 = SignExtend32<13>(fieldFromInstruction(insn, 0, 13));
601 else
602 rs2 = fieldFromInstruction(insn, 0, 5);
603
604 // Decode RD.
605 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rd, Address, Decoder);
606 if (status != MCDisassembler::Success)
607 return status;
608
609 // Decode RS1.
610 status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
611 if (status != MCDisassembler::Success)
612 return status;
613
614 // Decode RS1 | SIMM13.
615 if (isImm)
616 MI.addOperand(MCOperand::createImm(simm13));
617 else {
618 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
619 if (status != MCDisassembler::Success)
620 return status;
621 }
622
623 if (hasAsi)
624 MI.addOperand(MCOperand::createImm(asi));
625
626 return MCDisassembler::Success;
627 }
628
DecodeTRAP(MCInst & MI,unsigned insn,uint64_t Address,const void * Decoder)629 static DecodeStatus DecodeTRAP(MCInst &MI, unsigned insn, uint64_t Address,
630 const void *Decoder) {
631
632 unsigned rs1 = fieldFromInstruction(insn, 14, 5);
633 unsigned isImm = fieldFromInstruction(insn, 13, 1);
634 unsigned cc =fieldFromInstruction(insn, 25, 4);
635 unsigned rs2 = 0;
636 unsigned imm7 = 0;
637 if (isImm)
638 imm7 = fieldFromInstruction(insn, 0, 7);
639 else
640 rs2 = fieldFromInstruction(insn, 0, 5);
641
642 // Decode RS1.
643 DecodeStatus status = DecodeIntRegsRegisterClass(MI, rs1, Address, Decoder);
644 if (status != MCDisassembler::Success)
645 return status;
646
647 // Decode RS1 | IMM7.
648 if (isImm)
649 MI.addOperand(MCOperand::createImm(imm7));
650 else {
651 status = DecodeIntRegsRegisterClass(MI, rs2, Address, Decoder);
652 if (status != MCDisassembler::Success)
653 return status;
654 }
655
656 // Decode CC
657 MI.addOperand(MCOperand::createImm(cc));
658
659 return MCDisassembler::Success;
660 }
661