1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1030 < %s | FileCheck --check-prefix=GCN %s 3 4; -------------------------------------------------------------------------------- 5; amdgcn atomic csub 6; -------------------------------------------------------------------------------- 7 8define amdgpu_ps float @global_csub_saddr_i32_rtn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 9; GCN-LABEL: global_csub_saddr_i32_rtn: 10; GCN: ; %bb.0: 11; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] glc 12; GCN-NEXT: s_waitcnt vmcnt(0) 13; GCN-NEXT: ; return to shader part epilog 14 %zext.offset = zext i32 %voffset to i64 15 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 16 %cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)* 17 %rtn = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %cast.gep0, i32 %data) 18 %cast.rtn = bitcast i32 %rtn to float 19 ret float %cast.rtn 20} 21 22define amdgpu_ps float @global_csub_saddr_i32_rtn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 23; GCN-LABEL: global_csub_saddr_i32_rtn_neg128: 24; GCN: ; %bb.0: 25; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:-128 glc 26; GCN-NEXT: s_waitcnt vmcnt(0) 27; GCN-NEXT: ; return to shader part epilog 28 %zext.offset = zext i32 %voffset to i64 29 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 30 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 31 %cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)* 32 %rtn = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %cast.gep1, i32 %data) 33 %cast.rtn = bitcast i32 %rtn to float 34 ret float %cast.rtn 35} 36 37define amdgpu_ps void @global_csub_saddr_i32_nortn(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 38; GCN-LABEL: global_csub_saddr_i32_nortn: 39; GCN: ; %bb.0: 40; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] glc 41; GCN-NEXT: s_endpgm 42 %zext.offset = zext i32 %voffset to i64 43 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 44 %cast.gep0 = bitcast i8 addrspace(1)* %gep0 to i32 addrspace(1)* 45 %unused = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %cast.gep0, i32 %data) 46 ret void 47} 48 49define amdgpu_ps void @global_csub_saddr_i32_nortn_neg128(i8 addrspace(1)* inreg %sbase, i32 %voffset, i32 %data) { 50; GCN-LABEL: global_csub_saddr_i32_nortn_neg128: 51; GCN: ; %bb.0: 52; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:-128 glc 53; GCN-NEXT: s_endpgm 54 %zext.offset = zext i32 %voffset to i64 55 %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset 56 %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -128 57 %cast.gep1 = bitcast i8 addrspace(1)* %gep1 to i32 addrspace(1)* 58 %unused = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %cast.gep1, i32 %data) 59 ret void 60} 61 62declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0 63 64attributes #0 = { argmemonly nounwind willreturn } 65