1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s 3; RUN: llc -march=amdgcn -mcpu=gfx600 -amdgpu-bypass-slow-div=0 -amdgpu-codegenprepare-expand-div64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN-IR %s 4 5define amdgpu_kernel void @s_test_udiv_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 6; GCN-LABEL: s_test_udiv_i64: 7; GCN: ; %bb.0: 8; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd 9; GCN-NEXT: v_mov_b32_e32 v2, 0 10; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 11; GCN-NEXT: s_mov_b32 s7, 0xf000 12; GCN-NEXT: s_mov_b32 s6, -1 13; GCN-NEXT: s_waitcnt lgkmcnt(0) 14; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 15; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 16; GCN-NEXT: s_sub_u32 s4, 0, s2 17; GCN-NEXT: s_subb_u32 s5, 0, s3 18; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 19; GCN-NEXT: v_rcp_f32_e32 v0, v0 20; GCN-NEXT: v_mov_b32_e32 v1, 0 21; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 22; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 23; GCN-NEXT: v_trunc_f32_e32 v3, v3 24; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 25; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 26; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 27; GCN-NEXT: v_mul_hi_u32 v5, s4, v0 28; GCN-NEXT: v_mul_lo_u32 v4, s4, v3 29; GCN-NEXT: v_mul_lo_u32 v7, s5, v0 30; GCN-NEXT: v_mul_lo_u32 v6, s4, v0 31; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 32; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 33; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 34; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 35; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 36; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 37; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 38; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 39; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc 40; GCN-NEXT: v_mul_hi_u32 v9, v3, v4 41; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 42; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v8 43; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v6, vcc 44; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v1, vcc 45; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 46; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 47; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc 48; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] 49; GCN-NEXT: v_mul_lo_u32 v6, s4, v4 50; GCN-NEXT: v_mul_hi_u32 v7, s4, v0 51; GCN-NEXT: v_mul_lo_u32 v8, s5, v0 52; GCN-NEXT: s_mov_b32 s5, s9 53; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 54; GCN-NEXT: v_mul_lo_u32 v7, s4, v0 55; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 56; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 57; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 58; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 59; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 60; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 61; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 62; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 63; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc 64; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 65; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 66; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc 67; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v1, vcc 68; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 69; GCN-NEXT: v_addc_u32_e32 v6, vcc, v2, v6, vcc 70; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 71; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[0:1] 72; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 73; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 74; GCN-NEXT: v_mul_lo_u32 v4, s10, v3 75; GCN-NEXT: v_mul_hi_u32 v5, s10, v0 76; GCN-NEXT: v_mul_hi_u32 v6, s10, v3 77; GCN-NEXT: v_mul_hi_u32 v7, s11, v3 78; GCN-NEXT: v_mul_lo_u32 v3, s11, v3 79; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 80; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc 81; GCN-NEXT: v_mul_lo_u32 v6, s11, v0 82; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 83; GCN-NEXT: s_mov_b32 s4, s8 84; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 85; GCN-NEXT: v_addc_u32_e32 v0, vcc, v5, v0, vcc 86; GCN-NEXT: v_addc_u32_e32 v1, vcc, v7, v1, vcc 87; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 88; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc 89; GCN-NEXT: v_mul_lo_u32 v2, s2, v1 90; GCN-NEXT: v_mul_hi_u32 v3, s2, v0 91; GCN-NEXT: v_mul_lo_u32 v4, s3, v0 92; GCN-NEXT: v_mov_b32_e32 v5, s3 93; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 94; GCN-NEXT: v_mul_lo_u32 v3, s2, v0 95; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 96; GCN-NEXT: v_sub_i32_e32 v4, vcc, s11, v2 97; GCN-NEXT: v_sub_i32_e32 v3, vcc, s10, v3 98; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc 99; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s2, v3 100; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] 101; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s3, v4 102; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] 103; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s2, v5 104; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] 105; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s3, v4 106; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] 107; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 108; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v1, s[0:1] 109; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 110; GCN-NEXT: v_addc_u32_e64 v8, s[0:1], 0, v1, s[0:1] 111; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 112; GCN-NEXT: v_cndmask_b32_e64 v4, v8, v6, s[0:1] 113; GCN-NEXT: v_mov_b32_e32 v6, s11 114; GCN-NEXT: v_subb_u32_e32 v2, vcc, v6, v2, vcc 115; GCN-NEXT: v_cmp_le_u32_e32 vcc, s3, v2 116; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc 117; GCN-NEXT: v_cmp_le_u32_e32 vcc, s2, v3 118; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc 119; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s3, v2 120; GCN-NEXT: v_cndmask_b32_e32 v2, v6, v3, vcc 121; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 122; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] 123; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc 124; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 125; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 126; GCN-NEXT: s_endpgm 127; 128; GCN-IR-LABEL: s_test_udiv_i64: 129; GCN-IR: ; %bb.0: ; %_udiv-special-cases 130; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 131; GCN-IR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0xd 132; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 133; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 134; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 135; GCN-IR-NEXT: s_add_i32 s10, s10, 32 136; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 137; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 138; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 139; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 140; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 141; GCN-IR-NEXT: s_add_i32 s10, s10, 32 142; GCN-IR-NEXT: s_flbit_i32_b32 s11, s7 143; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 144; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 145; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 146; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 147; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc 148; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 149; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 150; GCN-IR-NEXT: v_subb_u32_e64 v1, s[10:11], 0, 0, vcc 151; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] 152; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] 153; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc 154; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] 155; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1 156; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc 157; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] 158; GCN-IR-NEXT: s_cbranch_vccz BB0_4 159; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 160; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 161; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc 162; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] 163; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 164; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 165; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1] 166; GCN-IR-NEXT: s_cbranch_vccz BB0_5 167; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 168; GCN-IR-NEXT: v_not_b32_e32 v2, v2 169; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 170; GCN-IR-NEXT: s_add_u32 s6, s2, -1 171; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 172; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 173; GCN-IR-NEXT: s_addc_u32 s7, s3, -1 174; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc 175; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 176; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 177; GCN-IR-NEXT: BB0_3: ; %udiv-do-while 178; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 179; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 180; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 181; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 182; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 183; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 184; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 185; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6 186; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc 187; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 188; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 189; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 190; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 191; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 192; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 193; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc 194; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] 195; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 196; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 197; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 198; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 199; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] 200; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc 201; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 202; GCN-IR-NEXT: s_cbranch_vccz BB0_3 203; GCN-IR-NEXT: s_branch BB0_6 204; GCN-IR-NEXT: BB0_4: 205; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 206; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] 207; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 208; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] 209; GCN-IR-NEXT: s_branch BB0_7 210; GCN-IR-NEXT: BB0_5: 211; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 212; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 213; GCN-IR-NEXT: BB0_6: ; %Flow6 214; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 215; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 216; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 217; GCN-IR-NEXT: BB0_7: ; %udiv-end 218; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 219; GCN-IR-NEXT: s_mov_b32 s6, -1 220; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 221; GCN-IR-NEXT: s_endpgm 222 %result = udiv i64 %x, %y 223 store i64 %result, i64 addrspace(1)* %out 224 ret void 225} 226 227define i64 @v_test_udiv_i64(i64 %x, i64 %y) { 228; GCN-LABEL: v_test_udiv_i64: 229; GCN: ; %bb.0: 230; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 231; GCN-NEXT: v_cvt_f32_u32_e32 v4, v2 232; GCN-NEXT: v_cvt_f32_u32_e32 v5, v3 233; GCN-NEXT: v_sub_i32_e32 v6, vcc, 0, v2 234; GCN-NEXT: v_subb_u32_e32 v7, vcc, 0, v3, vcc 235; GCN-NEXT: v_mov_b32_e32 v14, 0 236; GCN-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5 237; GCN-NEXT: v_rcp_f32_e32 v4, v4 238; GCN-NEXT: v_mov_b32_e32 v13, 0 239; GCN-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 240; GCN-NEXT: v_mul_f32_e32 v5, 0x2f800000, v4 241; GCN-NEXT: v_trunc_f32_e32 v5, v5 242; GCN-NEXT: v_mac_f32_e32 v4, 0xcf800000, v5 243; GCN-NEXT: v_cvt_u32_f32_e32 v4, v4 244; GCN-NEXT: v_cvt_u32_f32_e32 v5, v5 245; GCN-NEXT: v_mul_hi_u32 v8, v6, v4 246; GCN-NEXT: v_mul_lo_u32 v9, v6, v5 247; GCN-NEXT: v_mul_lo_u32 v10, v7, v4 248; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v9 249; GCN-NEXT: v_mul_lo_u32 v9, v6, v4 250; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 251; GCN-NEXT: v_mul_lo_u32 v11, v4, v8 252; GCN-NEXT: v_mul_hi_u32 v10, v4, v8 253; GCN-NEXT: v_mul_hi_u32 v12, v4, v9 254; GCN-NEXT: v_mul_hi_u32 v15, v5, v8 255; GCN-NEXT: v_mul_lo_u32 v8, v5, v8 256; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 257; GCN-NEXT: v_mul_lo_u32 v12, v5, v9 258; GCN-NEXT: v_mul_hi_u32 v9, v5, v9 259; GCN-NEXT: v_addc_u32_e32 v10, vcc, v14, v10, vcc 260; GCN-NEXT: v_add_i32_e32 v11, vcc, v11, v12 261; GCN-NEXT: v_addc_u32_e32 v9, vcc, v10, v9, vcc 262; GCN-NEXT: v_addc_u32_e32 v10, vcc, v15, v13, vcc 263; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 264; GCN-NEXT: v_add_i32_e64 v4, s[4:5], v4, v8 265; GCN-NEXT: v_addc_u32_e32 v9, vcc, v14, v10, vcc 266; GCN-NEXT: v_addc_u32_e64 v8, vcc, v5, v9, s[4:5] 267; GCN-NEXT: v_mul_lo_u32 v10, v6, v8 268; GCN-NEXT: v_mul_hi_u32 v11, v6, v4 269; GCN-NEXT: v_mul_lo_u32 v7, v7, v4 270; GCN-NEXT: v_mul_lo_u32 v6, v6, v4 271; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 272; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 273; GCN-NEXT: v_mul_lo_u32 v12, v4, v7 274; GCN-NEXT: v_mul_hi_u32 v15, v4, v6 275; GCN-NEXT: v_mul_hi_u32 v16, v4, v7 276; GCN-NEXT: v_mul_hi_u32 v11, v8, v6 277; GCN-NEXT: v_mul_lo_u32 v6, v8, v6 278; GCN-NEXT: v_add_i32_e32 v12, vcc, v15, v12 279; GCN-NEXT: v_mul_hi_u32 v10, v8, v7 280; GCN-NEXT: v_addc_u32_e32 v15, vcc, v14, v16, vcc 281; GCN-NEXT: v_mul_lo_u32 v7, v8, v7 282; GCN-NEXT: v_add_i32_e32 v6, vcc, v12, v6 283; GCN-NEXT: v_addc_u32_e32 v6, vcc, v15, v11, vcc 284; GCN-NEXT: v_addc_u32_e32 v8, vcc, v10, v13, vcc 285; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 286; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc 287; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v9 288; GCN-NEXT: v_addc_u32_e64 v5, vcc, v5, v7, s[4:5] 289; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 290; GCN-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc 291; GCN-NEXT: v_mul_lo_u32 v6, v0, v5 292; GCN-NEXT: v_mul_hi_u32 v7, v0, v4 293; GCN-NEXT: v_mul_hi_u32 v8, v0, v5 294; GCN-NEXT: v_mul_hi_u32 v9, v1, v5 295; GCN-NEXT: v_mul_lo_u32 v5, v1, v5 296; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 297; GCN-NEXT: v_addc_u32_e32 v7, vcc, v14, v8, vcc 298; GCN-NEXT: v_mul_lo_u32 v8, v1, v4 299; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 300; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 301; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v4, vcc 302; GCN-NEXT: v_addc_u32_e32 v6, vcc, v9, v13, vcc 303; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 304; GCN-NEXT: v_addc_u32_e32 v5, vcc, v14, v6, vcc 305; GCN-NEXT: v_mul_lo_u32 v6, v2, v5 306; GCN-NEXT: v_mul_hi_u32 v7, v2, v4 307; GCN-NEXT: v_mul_lo_u32 v8, v3, v4 308; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 309; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 310; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 311; GCN-NEXT: v_sub_i32_e32 v8, vcc, v1, v6 312; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v7 313; GCN-NEXT: v_subb_u32_e64 v7, s[4:5], v8, v3, vcc 314; GCN-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v2 315; GCN-NEXT: v_subbrev_u32_e64 v7, s[4:5], 0, v7, s[4:5] 316; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v7, v3 317; GCN-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] 318; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v8, v2 319; GCN-NEXT: v_cndmask_b32_e64 v8, 0, -1, s[4:5] 320; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v7, v3 321; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v6, vcc 322; GCN-NEXT: v_cndmask_b32_e64 v7, v9, v8, s[4:5] 323; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 2, v4 324; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v5, s[4:5] 325; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 326; GCN-NEXT: v_add_i32_e64 v10, s[4:5], 1, v4 327; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc 328; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 329; GCN-NEXT: v_addc_u32_e64 v11, s[4:5], 0, v5, s[4:5] 330; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc 331; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3 332; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v7 333; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc 334; GCN-NEXT: v_cndmask_b32_e64 v7, v10, v8, s[4:5] 335; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 336; GCN-NEXT: v_cndmask_b32_e64 v1, v11, v9, s[4:5] 337; GCN-NEXT: v_cndmask_b32_e32 v0, v4, v7, vcc 338; GCN-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc 339; GCN-NEXT: s_setpc_b64 s[30:31] 340; 341; GCN-IR-LABEL: v_test_udiv_i64: 342; GCN-IR: ; %bb.0: ; %_udiv-special-cases 343; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 344; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3] 345; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] 346; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v2 347; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] 348; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 349; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v3 350; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 351; GCN-IR-NEXT: v_cndmask_b32_e32 v8, v5, v4, vcc 352; GCN-IR-NEXT: v_ffbh_u32_e32 v4, v0 353; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 32, v4 354; GCN-IR-NEXT: v_ffbh_u32_e32 v5, v1 355; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 356; GCN-IR-NEXT: v_cndmask_b32_e32 v10, v5, v4, vcc 357; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v8, v10 358; GCN-IR-NEXT: v_subb_u32_e64 v7, s[6:7], 0, 0, vcc 359; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[6:7] 360; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 361; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc 362; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[6:7] 363; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 364; GCN-IR-NEXT: v_mov_b32_e32 v11, v9 365; GCN-IR-NEXT: v_cndmask_b32_e64 v4, v1, 0, s[4:5] 366; GCN-IR-NEXT: v_cndmask_b32_e64 v5, v0, 0, s[4:5] 367; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc 368; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] 369; GCN-IR-NEXT: s_cbranch_execz BB1_6 370; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 371; GCN-IR-NEXT: v_add_i32_e32 v12, vcc, 1, v6 372; GCN-IR-NEXT: v_addc_u32_e32 v13, vcc, 0, v7, vcc 373; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 63, v6 374; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[12:13], v[6:7] 375; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 376; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[0:1], v4 377; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 378; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 379; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc 380; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] 381; GCN-IR-NEXT: s_cbranch_execz BB1_5 382; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 383; GCN-IR-NEXT: v_lshr_b64 v[12:13], v[0:1], v12 384; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, -1, v2 385; GCN-IR-NEXT: v_addc_u32_e32 v1, vcc, -1, v3, vcc 386; GCN-IR-NEXT: v_not_b32_e32 v6, v8 387; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 388; GCN-IR-NEXT: v_not_b32_e32 v7, v9 389; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, v6, v10 390; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 391; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, v7, v11, vcc 392; GCN-IR-NEXT: BB1_3: ; %udiv-do-while 393; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 394; GCN-IR-NEXT: v_lshl_b64 v[10:11], v[12:13], 1 395; GCN-IR-NEXT: v_lshrrev_b32_e32 v6, 31, v5 396; GCN-IR-NEXT: v_or_b32_e32 v10, v10, v6 397; GCN-IR-NEXT: v_lshl_b64 v[4:5], v[4:5], 1 398; GCN-IR-NEXT: v_sub_i32_e32 v6, vcc, v0, v10 399; GCN-IR-NEXT: v_subb_u32_e32 v6, vcc, v1, v11, vcc 400; GCN-IR-NEXT: v_or_b32_e32 v4, v14, v4 401; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v8 402; GCN-IR-NEXT: v_ashrrev_i32_e32 v12, 31, v6 403; GCN-IR-NEXT: v_or_b32_e32 v5, v15, v5 404; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v9, vcc 405; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[8:9] 406; GCN-IR-NEXT: v_mov_b32_e32 v8, v14 407; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 408; GCN-IR-NEXT: v_and_b32_e32 v6, 1, v12 409; GCN-IR-NEXT: v_and_b32_e32 v13, v12, v3 410; GCN-IR-NEXT: v_and_b32_e32 v12, v12, v2 411; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v10, v12 412; GCN-IR-NEXT: v_mov_b32_e32 v9, v15 413; GCN-IR-NEXT: v_mov_b32_e32 v15, v7 414; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v11, v13, s[4:5] 415; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] 416; GCN-IR-NEXT: v_mov_b32_e32 v14, v6 417; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] 418; GCN-IR-NEXT: s_cbranch_execnz BB1_3 419; GCN-IR-NEXT: ; %bb.4: ; %Flow 420; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] 421; GCN-IR-NEXT: BB1_5: ; %Flow3 422; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] 423; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[4:5], 1 424; GCN-IR-NEXT: v_or_b32_e32 v4, v7, v1 425; GCN-IR-NEXT: v_or_b32_e32 v5, v6, v0 426; GCN-IR-NEXT: BB1_6: ; %Flow4 427; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] 428; GCN-IR-NEXT: v_mov_b32_e32 v0, v5 429; GCN-IR-NEXT: v_mov_b32_e32 v1, v4 430; GCN-IR-NEXT: s_setpc_b64 s[30:31] 431 %result = udiv i64 %x, %y 432 ret i64 %result 433} 434 435define amdgpu_kernel void @s_test_udiv24_64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 436; GCN-LABEL: s_test_udiv24_64: 437; GCN: ; %bb.0: 438; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 439; GCN-NEXT: s_load_dword s0, s[0:1], 0xe 440; GCN-NEXT: s_mov_b32 s3, 0xf000 441; GCN-NEXT: s_mov_b32 s2, -1 442; GCN-NEXT: s_waitcnt lgkmcnt(0) 443; GCN-NEXT: s_mov_b32 s1, s5 444; GCN-NEXT: s_lshr_b32 s0, s0, 8 445; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 446; GCN-NEXT: s_lshr_b32 s0, s7, 8 447; GCN-NEXT: v_cvt_f32_u32_e32 v1, s0 448; GCN-NEXT: s_mov_b32 s0, s4 449; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 450; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 451; GCN-NEXT: v_trunc_f32_e32 v2, v2 452; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 453; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 454; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 455; GCN-NEXT: v_mov_b32_e32 v1, 0 456; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 457; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 458; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 459; GCN-NEXT: s_endpgm 460; 461; GCN-IR-LABEL: s_test_udiv24_64: 462; GCN-IR: ; %bb.0: 463; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 464; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe 465; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 466; GCN-IR-NEXT: s_mov_b32 s2, -1 467; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 468; GCN-IR-NEXT: s_mov_b32 s1, s5 469; GCN-IR-NEXT: s_lshr_b32 s0, s0, 8 470; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 471; GCN-IR-NEXT: s_lshr_b32 s0, s7, 8 472; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s0 473; GCN-IR-NEXT: s_mov_b32 s0, s4 474; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 475; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 476; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 477; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 478; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 479; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 480; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 481; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 482; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 483; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 484; GCN-IR-NEXT: s_endpgm 485 %1 = lshr i64 %x, 40 486 %2 = lshr i64 %y, 40 487 %result = udiv i64 %1, %2 488 store i64 %result, i64 addrspace(1)* %out 489 ret void 490} 491 492define i64 @v_test_udiv24_i64(i64 %x, i64 %y) { 493; GCN-LABEL: v_test_udiv24_i64: 494; GCN: ; %bb.0: 495; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 496; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3 497; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0 498; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1 499; GCN-NEXT: v_cvt_f32_u32_e32 v1, v1 500; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 501; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 502; GCN-NEXT: v_trunc_f32_e32 v2, v2 503; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 504; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 505; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 506; GCN-NEXT: v_mov_b32_e32 v1, 0 507; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 508; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 509; GCN-NEXT: s_setpc_b64 s[30:31] 510; 511; GCN-IR-LABEL: v_test_udiv24_i64: 512; GCN-IR: ; %bb.0: 513; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 514; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3 515; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0 516; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1 517; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, v1 518; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 519; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 520; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 521; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 522; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 523; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 524; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 525; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 526; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 527; GCN-IR-NEXT: s_setpc_b64 s[30:31] 528 %1 = lshr i64 %x, 40 529 %2 = lshr i64 %y, 40 530 %result = udiv i64 %1, %2 531 ret i64 %result 532} 533 534define amdgpu_kernel void @s_test_udiv32_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 535; GCN-LABEL: s_test_udiv32_i64: 536; GCN: ; %bb.0: 537; GCN-NEXT: s_load_dword s2, s[0:1], 0xe 538; GCN-NEXT: s_mov_b32 s7, 0xf000 539; GCN-NEXT: s_mov_b32 s6, -1 540; GCN-NEXT: s_waitcnt lgkmcnt(0) 541; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 542; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 543; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 544; GCN-NEXT: s_waitcnt lgkmcnt(0) 545; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 546; GCN-NEXT: s_mov_b32 s4, s0 547; GCN-NEXT: s_mov_b32 s5, s1 548; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 549; GCN-NEXT: v_trunc_f32_e32 v2, v2 550; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 551; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 552; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 553; GCN-NEXT: v_mov_b32_e32 v1, 0 554; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 555; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 556; GCN-NEXT: s_endpgm 557; 558; GCN-IR-LABEL: s_test_udiv32_i64: 559; GCN-IR: ; %bb.0: 560; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe 561; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 562; GCN-IR-NEXT: s_mov_b32 s6, -1 563; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 564; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 565; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 566; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 567; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 568; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s3 569; GCN-IR-NEXT: s_mov_b32 s4, s0 570; GCN-IR-NEXT: s_mov_b32 s5, s1 571; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 572; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 573; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 574; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 575; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 576; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 577; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 578; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 579; GCN-IR-NEXT: s_endpgm 580 %1 = lshr i64 %x, 32 581 %2 = lshr i64 %y, 32 582 %result = udiv i64 %1, %2 583 store i64 %result, i64 addrspace(1)* %out 584 ret void 585} 586 587define amdgpu_kernel void @s_test_udiv31_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 588; GCN-LABEL: s_test_udiv31_i64: 589; GCN: ; %bb.0: 590; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 591; GCN-NEXT: s_load_dword s0, s[0:1], 0xe 592; GCN-NEXT: s_mov_b32 s3, 0xf000 593; GCN-NEXT: s_mov_b32 s2, -1 594; GCN-NEXT: s_waitcnt lgkmcnt(0) 595; GCN-NEXT: s_mov_b32 s1, s5 596; GCN-NEXT: s_lshr_b32 s0, s0, 1 597; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 598; GCN-NEXT: s_lshr_b32 s0, s7, 1 599; GCN-NEXT: v_cvt_f32_u32_e32 v1, s0 600; GCN-NEXT: s_mov_b32 s0, s4 601; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 602; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 603; GCN-NEXT: v_trunc_f32_e32 v2, v2 604; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 605; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 606; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 607; GCN-NEXT: v_mov_b32_e32 v1, 0 608; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 609; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 610; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 611; GCN-NEXT: s_endpgm 612; 613; GCN-IR-LABEL: s_test_udiv31_i64: 614; GCN-IR: ; %bb.0: 615; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 616; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe 617; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 618; GCN-IR-NEXT: s_mov_b32 s2, -1 619; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 620; GCN-IR-NEXT: s_mov_b32 s1, s5 621; GCN-IR-NEXT: s_lshr_b32 s0, s0, 1 622; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 623; GCN-IR-NEXT: s_lshr_b32 s0, s7, 1 624; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s0 625; GCN-IR-NEXT: s_mov_b32 s0, s4 626; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 627; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 628; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 629; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 630; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 631; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 632; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 633; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 634; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 635; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 636; GCN-IR-NEXT: s_endpgm 637 %1 = lshr i64 %x, 33 638 %2 = lshr i64 %y, 33 639 %result = udiv i64 %1, %2 640 store i64 %result, i64 addrspace(1)* %out 641 ret void 642} 643 644define amdgpu_kernel void @s_test_udiv23_i64(i64 addrspace(1)* %out, i64 %x, i64 %y) { 645; GCN-LABEL: s_test_udiv23_i64: 646; GCN: ; %bb.0: 647; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 648; GCN-NEXT: s_load_dword s0, s[0:1], 0xe 649; GCN-NEXT: s_mov_b32 s3, 0xf000 650; GCN-NEXT: s_mov_b32 s2, -1 651; GCN-NEXT: s_waitcnt lgkmcnt(0) 652; GCN-NEXT: s_mov_b32 s1, s5 653; GCN-NEXT: s_lshr_b32 s0, s0, 9 654; GCN-NEXT: v_cvt_f32_u32_e32 v0, s0 655; GCN-NEXT: s_lshr_b32 s0, s7, 9 656; GCN-NEXT: v_cvt_f32_u32_e32 v1, s0 657; GCN-NEXT: s_mov_b32 s0, s4 658; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 659; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 660; GCN-NEXT: v_trunc_f32_e32 v2, v2 661; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 662; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 663; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 664; GCN-NEXT: v_mov_b32_e32 v1, 0 665; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 666; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0 667; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 668; GCN-NEXT: s_endpgm 669; 670; GCN-IR-LABEL: s_test_udiv23_i64: 671; GCN-IR: ; %bb.0: 672; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 673; GCN-IR-NEXT: s_load_dword s0, s[0:1], 0xe 674; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 675; GCN-IR-NEXT: s_mov_b32 s2, -1 676; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 677; GCN-IR-NEXT: s_mov_b32 s1, s5 678; GCN-IR-NEXT: s_lshr_b32 s0, s0, 9 679; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s0 680; GCN-IR-NEXT: s_lshr_b32 s0, s7, 9 681; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s0 682; GCN-IR-NEXT: s_mov_b32 s0, s4 683; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 684; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 685; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 686; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 687; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 688; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 689; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 690; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc 691; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffff, v0 692; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 693; GCN-IR-NEXT: s_endpgm 694 %1 = lshr i64 %x, 41 695 %2 = lshr i64 %y, 41 696 %result = udiv i64 %1, %2 697 store i64 %result, i64 addrspace(1)* %out 698 ret void 699} 700 701define amdgpu_kernel void @s_test_udiv24_i48(i48 addrspace(1)* %out, i48 %x, i48 %y) { 702; GCN-LABEL: s_test_udiv24_i48: 703; GCN: ; %bb.0: 704; GCN-NEXT: s_load_dword s2, s[0:1], 0xd 705; GCN-NEXT: s_load_dword s3, s[0:1], 0xe 706; GCN-NEXT: s_mov_b32 s5, 0xff000000 707; GCN-NEXT: s_mov_b32 s4, 0xffff 708; GCN-NEXT: v_cvt_f32_ubyte3_e32 v2, s4 709; GCN-NEXT: s_waitcnt lgkmcnt(0) 710; GCN-NEXT: s_and_b32 s2, s2, s5 711; GCN-NEXT: s_and_b32 s3, s3, s4 712; GCN-NEXT: v_mov_b32_e32 v0, s2 713; GCN-NEXT: v_alignbit_b32 v0, s3, v0, 24 714; GCN-NEXT: v_cvt_f32_u32_e32 v1, v0 715; GCN-NEXT: s_load_dword s6, s[0:1], 0xb 716; GCN-NEXT: s_load_dword s7, s[0:1], 0xc 717; GCN-NEXT: s_lshr_b64 s[2:3], s[2:3], 24 718; GCN-NEXT: v_mov_b32_e32 v9, 0 719; GCN-NEXT: v_mac_f32_e32 v1, 0x4f800000, v2 720; GCN-NEXT: v_rcp_f32_e32 v1, v1 721; GCN-NEXT: s_waitcnt lgkmcnt(0) 722; GCN-NEXT: s_and_b32 s7, s7, s4 723; GCN-NEXT: s_and_b32 s6, s6, s5 724; GCN-NEXT: s_sub_u32 s8, 0, s2 725; GCN-NEXT: v_mul_f32_e32 v1, 0x5f7ffffc, v1 726; GCN-NEXT: v_mul_f32_e32 v2, 0x2f800000, v1 727; GCN-NEXT: v_trunc_f32_e32 v2, v2 728; GCN-NEXT: v_mac_f32_e32 v1, 0xcf800000, v2 729; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 730; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 731; GCN-NEXT: s_subb_u32 s9, 0, s3 732; GCN-NEXT: v_mov_b32_e32 v8, 0 733; GCN-NEXT: v_mul_lo_u32 v3, s8, v2 734; GCN-NEXT: v_mul_hi_u32 v4, s8, v1 735; GCN-NEXT: v_mul_lo_u32 v5, s9, v1 736; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 737; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 738; GCN-NEXT: v_mul_lo_u32 v4, s8, v1 739; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 740; GCN-NEXT: v_mul_lo_u32 v6, v1, v3 741; GCN-NEXT: v_mul_hi_u32 v5, v1, v3 742; GCN-NEXT: v_mul_hi_u32 v7, v1, v4 743; GCN-NEXT: v_mul_hi_u32 v10, v2, v3 744; GCN-NEXT: v_mul_lo_u32 v3, v2, v3 745; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 746; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 747; GCN-NEXT: v_mul_hi_u32 v4, v2, v4 748; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc 749; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 750; GCN-NEXT: v_addc_u32_e32 v4, vcc, v5, v4, vcc 751; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v8, vcc 752; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 753; GCN-NEXT: v_add_i32_e64 v1, s[2:3], v1, v3 754; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v5, vcc 755; GCN-NEXT: v_addc_u32_e64 v3, vcc, v2, v4, s[2:3] 756; GCN-NEXT: v_mul_lo_u32 v5, s8, v3 757; GCN-NEXT: v_mul_hi_u32 v6, s8, v1 758; GCN-NEXT: v_mul_lo_u32 v7, s9, v1 759; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 760; GCN-NEXT: v_mul_lo_u32 v6, s8, v1 761; GCN-NEXT: v_add_i32_e32 v5, vcc, v7, v5 762; GCN-NEXT: v_mul_lo_u32 v11, v1, v5 763; GCN-NEXT: v_mul_hi_u32 v13, v1, v5 764; GCN-NEXT: v_mul_hi_u32 v12, v1, v6 765; GCN-NEXT: v_mul_hi_u32 v10, v3, v6 766; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 767; GCN-NEXT: v_mul_hi_u32 v7, v3, v5 768; GCN-NEXT: v_add_i32_e32 v11, vcc, v12, v11 769; GCN-NEXT: v_addc_u32_e32 v12, vcc, v9, v13, vcc 770; GCN-NEXT: v_mul_lo_u32 v3, v3, v5 771; GCN-NEXT: v_add_i32_e32 v6, vcc, v11, v6 772; GCN-NEXT: v_addc_u32_e32 v6, vcc, v12, v10, vcc 773; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc 774; GCN-NEXT: v_add_i32_e32 v3, vcc, v6, v3 775; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v5, vcc 776; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 777; GCN-NEXT: v_addc_u32_e64 v2, vcc, v2, v5, s[2:3] 778; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 779; GCN-NEXT: v_mov_b32_e32 v3, s6 780; GCN-NEXT: v_alignbit_b32 v3, s7, v3, 24 781; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc 782; GCN-NEXT: v_mul_hi_u32 v5, v3, v1 783; GCN-NEXT: v_mul_lo_u32 v4, v3, v2 784; GCN-NEXT: v_mul_hi_u32 v6, v3, v2 785; GCN-NEXT: v_mul_hi_u32 v1, 0, v1 786; GCN-NEXT: v_mul_hi_u32 v2, 0, v2 787; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 788; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc 789; GCN-NEXT: v_add_i32_e32 v4, vcc, 0, v4 790; GCN-NEXT: v_addc_u32_e32 v1, vcc, v5, v1, vcc 791; GCN-NEXT: v_addc_u32_e32 v2, vcc, v2, v8, vcc 792; GCN-NEXT: v_add_i32_e32 v1, vcc, 0, v1 793; GCN-NEXT: v_addc_u32_e32 v2, vcc, v9, v2, vcc 794; GCN-NEXT: v_mul_lo_u32 v4, v0, v2 795; GCN-NEXT: v_mul_hi_u32 v5, v0, v1 796; GCN-NEXT: v_mul_lo_u32 v6, v0, v1 797; GCN-NEXT: s_mov_b32 s7, 0xf000 798; GCN-NEXT: s_mov_b32 s6, -1 799; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 800; GCN-NEXT: v_sub_i32_e32 v3, vcc, v3, v6 801; GCN-NEXT: v_subb_u32_e32 v4, vcc, 0, v4, vcc 802; GCN-NEXT: v_sub_i32_e32 v5, vcc, v3, v0 803; GCN-NEXT: v_subbrev_u32_e32 v6, vcc, 0, v4, vcc 804; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v5, v0 805; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc 806; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v6 807; GCN-NEXT: v_cndmask_b32_e32 v5, -1, v5, vcc 808; GCN-NEXT: v_add_i32_e32 v6, vcc, 2, v1 809; GCN-NEXT: v_addc_u32_e32 v7, vcc, 0, v2, vcc 810; GCN-NEXT: v_add_i32_e32 v8, vcc, 1, v1 811; GCN-NEXT: v_cmp_ge_u32_e64 s[0:1], v3, v0 812; GCN-NEXT: v_addc_u32_e32 v9, vcc, 0, v2, vcc 813; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[0:1] 814; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v4 815; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 816; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[0:1] 817; GCN-NEXT: v_cndmask_b32_e32 v5, v8, v6, vcc 818; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v0 819; GCN-NEXT: v_cndmask_b32_e64 v0, v1, v5, s[0:1] 820; GCN-NEXT: v_cndmask_b32_e32 v1, v9, v7, vcc 821; GCN-NEXT: v_cndmask_b32_e64 v1, v2, v1, s[0:1] 822; GCN-NEXT: s_waitcnt lgkmcnt(0) 823; GCN-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 824; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 825; GCN-NEXT: s_endpgm 826; 827; GCN-IR-LABEL: s_test_udiv24_i48: 828; GCN-IR: ; %bb.0: ; %_udiv-special-cases 829; GCN-IR-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 830; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xb 831; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xc 832; GCN-IR-NEXT: s_load_dword s6, s[0:1], 0xd 833; GCN-IR-NEXT: s_load_dword s7, s[0:1], 0xe 834; GCN-IR-NEXT: s_mov_b32 s8, 0xffff 835; GCN-IR-NEXT: s_mov_b32 s9, 0xff000000 836; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 837; GCN-IR-NEXT: s_and_b32 s1, s3, s8 838; GCN-IR-NEXT: s_and_b32 s0, s2, s9 839; GCN-IR-NEXT: s_and_b32 s3, s7, s8 840; GCN-IR-NEXT: s_and_b32 s2, s6, s9 841; GCN-IR-NEXT: s_lshr_b64 s[2:3], s[2:3], 24 842; GCN-IR-NEXT: s_flbit_i32_b32 s10, s2 843; GCN-IR-NEXT: s_lshr_b64 s[6:7], s[0:1], 24 844; GCN-IR-NEXT: s_add_i32 s10, s10, 32 845; GCN-IR-NEXT: s_flbit_i32_b32 s11, s3 846; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 847; GCN-IR-NEXT: s_flbit_i32_b32 s10, s6 848; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 849; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s3, 0 850; GCN-IR-NEXT: s_add_i32 s10, s10, 32 851; GCN-IR-NEXT: s_flbit_i32_b32 s11, s7 852; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 853; GCN-IR-NEXT: v_mov_b32_e32 v0, s11 854; GCN-IR-NEXT: v_mov_b32_e32 v1, s10 855; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 856; GCN-IR-NEXT: v_cndmask_b32_e32 v3, v0, v1, vcc 857; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, v2, v3 858; GCN-IR-NEXT: v_subb_u32_e64 v1, s[10:11], 0, 0, vcc 859; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[2:3], 0 860; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[8:9], s[6:7], 0 861; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] 862; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9] 863; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc 864; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] 865; GCN-IR-NEXT: s_xor_b64 s[8:9], s[0:1], -1 866; GCN-IR-NEXT: s_and_b64 s[8:9], s[8:9], vcc 867; GCN-IR-NEXT: s_and_b64 vcc, exec, s[8:9] 868; GCN-IR-NEXT: s_cbranch_vccz BB7_4 869; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 870; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v0 871; GCN-IR-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc 872; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[4:5], v[0:1] 873; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 874; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 875; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1] 876; GCN-IR-NEXT: s_cbranch_vccz BB7_5 877; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 878; GCN-IR-NEXT: v_not_b32_e32 v2, v2 879; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v4 880; GCN-IR-NEXT: s_add_u32 s6, s2, -1 881; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, v2, v3 882; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 883; GCN-IR-NEXT: s_addc_u32 s7, s3, -1 884; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], -1, 0, vcc 885; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 886; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 887; GCN-IR-NEXT: BB7_3: ; %udiv-do-while 888; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 889; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 890; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 891; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 892; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 893; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 894; GCN-IR-NEXT: v_mov_b32_e32 v2, s7 895; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s6, v6 896; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc 897; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 898; GCN-IR-NEXT: v_and_b32_e32 v10, s2, v8 899; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 900; GCN-IR-NEXT: v_and_b32_e32 v11, s3, v8 901; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 902; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 903; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc 904; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] 905; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 906; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 907; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 908; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 909; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] 910; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc 911; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 912; GCN-IR-NEXT: s_cbranch_vccz BB7_3 913; GCN-IR-NEXT: s_branch BB7_6 914; GCN-IR-NEXT: BB7_4: 915; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 916; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] 917; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 918; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] 919; GCN-IR-NEXT: s_branch BB7_7 920; GCN-IR-NEXT: BB7_5: 921; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 922; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 923; GCN-IR-NEXT: BB7_6: ; %Flow3 924; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 925; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 926; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 927; GCN-IR-NEXT: BB7_7: ; %udiv-end 928; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 929; GCN-IR-NEXT: s_mov_b32 s6, -1 930; GCN-IR-NEXT: buffer_store_short v1, off, s[4:7], 0 offset:4 931; GCN-IR-NEXT: buffer_store_dword v0, off, s[4:7], 0 932; GCN-IR-NEXT: s_endpgm 933 %1 = lshr i48 %x, 24 934 %2 = lshr i48 %y, 24 935 %result = udiv i48 %1, %2 936 store i48 %result, i48 addrspace(1)* %out 937 ret void 938} 939 940define amdgpu_kernel void @s_test_udiv_k_num_i64(i64 addrspace(1)* %out, i64 %x) { 941; GCN-LABEL: s_test_udiv_k_num_i64: 942; GCN: ; %bb.0: 943; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 944; GCN-NEXT: v_mov_b32_e32 v2, 0 945; GCN-NEXT: s_mov_b32 s11, 0xf000 946; GCN-NEXT: s_mov_b32 s10, -1 947; GCN-NEXT: s_waitcnt lgkmcnt(0) 948; GCN-NEXT: v_cvt_f32_u32_e32 v0, s6 949; GCN-NEXT: v_cvt_f32_u32_e32 v1, s7 950; GCN-NEXT: s_sub_u32 s2, 0, s6 951; GCN-NEXT: s_subb_u32 s3, 0, s7 952; GCN-NEXT: s_mov_b32 s8, s4 953; GCN-NEXT: v_mac_f32_e32 v0, 0x4f800000, v1 954; GCN-NEXT: v_rcp_f32_e32 v0, v0 955; GCN-NEXT: v_mov_b32_e32 v1, 0 956; GCN-NEXT: s_mov_b32 s9, s5 957; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 958; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v0 959; GCN-NEXT: v_trunc_f32_e32 v3, v3 960; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v3 961; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 962; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 963; GCN-NEXT: v_mul_hi_u32 v5, s2, v0 964; GCN-NEXT: v_mul_lo_u32 v4, s2, v3 965; GCN-NEXT: v_mul_lo_u32 v7, s3, v0 966; GCN-NEXT: v_mul_lo_u32 v6, s2, v0 967; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 968; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v7 969; GCN-NEXT: v_mul_hi_u32 v5, v0, v6 970; GCN-NEXT: v_mul_lo_u32 v7, v0, v4 971; GCN-NEXT: v_mul_hi_u32 v9, v0, v4 972; GCN-NEXT: v_mul_hi_u32 v8, v3, v6 973; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 974; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v7 975; GCN-NEXT: v_mul_hi_u32 v10, v3, v4 976; GCN-NEXT: v_addc_u32_e32 v7, vcc, v2, v9, vcc 977; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 978; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 979; GCN-NEXT: v_addc_u32_e32 v5, vcc, v7, v8, vcc 980; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v1, vcc 981; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 982; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v4 983; GCN-NEXT: v_addc_u32_e32 v5, vcc, v2, v6, vcc 984; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[0:1] 985; GCN-NEXT: v_mul_lo_u32 v6, s2, v4 986; GCN-NEXT: v_mul_hi_u32 v7, s2, v0 987; GCN-NEXT: v_mul_lo_u32 v8, s3, v0 988; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 989; GCN-NEXT: v_mul_lo_u32 v7, s2, v0 990; GCN-NEXT: v_add_i32_e32 v6, vcc, v8, v6 991; GCN-NEXT: v_mul_lo_u32 v10, v0, v6 992; GCN-NEXT: v_mul_hi_u32 v12, v0, v6 993; GCN-NEXT: v_mul_hi_u32 v11, v0, v7 994; GCN-NEXT: v_mul_hi_u32 v9, v4, v7 995; GCN-NEXT: v_mul_lo_u32 v7, v4, v7 996; GCN-NEXT: v_mul_hi_u32 v8, v4, v6 997; GCN-NEXT: v_add_i32_e32 v10, vcc, v11, v10 998; GCN-NEXT: v_addc_u32_e32 v11, vcc, v2, v12, vcc 999; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 1000; GCN-NEXT: v_add_i32_e32 v7, vcc, v10, v7 1001; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v9, vcc 1002; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v1, vcc 1003; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 1004; GCN-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc 1005; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 1006; GCN-NEXT: v_addc_u32_e64 v1, vcc, v3, v1, s[0:1] 1007; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v4 1008; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1009; GCN-NEXT: v_mul_lo_u32 v3, v1, 24 1010; GCN-NEXT: v_mul_hi_u32 v0, v0, 24 1011; GCN-NEXT: v_mul_hi_u32 v1, v1, 24 1012; GCN-NEXT: v_mov_b32_e32 v5, s7 1013; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v3 1014; GCN-NEXT: v_addc_u32_e32 v0, vcc, v2, v1, vcc 1015; GCN-NEXT: v_mul_lo_u32 v1, s7, v0 1016; GCN-NEXT: v_mul_hi_u32 v3, s6, v0 1017; GCN-NEXT: v_add_i32_e32 v1, vcc, v3, v1 1018; GCN-NEXT: v_mul_lo_u32 v3, s6, v0 1019; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v1 1020; GCN-NEXT: v_sub_i32_e32 v3, vcc, 24, v3 1021; GCN-NEXT: v_subb_u32_e64 v4, s[0:1], v4, v5, vcc 1022; GCN-NEXT: v_subrev_i32_e64 v5, s[0:1], s6, v3 1023; GCN-NEXT: v_subbrev_u32_e64 v4, s[0:1], 0, v4, s[0:1] 1024; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s7, v4 1025; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[0:1] 1026; GCN-NEXT: v_cmp_le_u32_e64 s[0:1], s6, v5 1027; GCN-NEXT: v_cndmask_b32_e64 v5, 0, -1, s[0:1] 1028; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], s7, v4 1029; GCN-NEXT: v_cndmask_b32_e64 v4, v6, v5, s[0:1] 1030; GCN-NEXT: v_add_i32_e64 v5, s[0:1], 2, v0 1031; GCN-NEXT: v_addc_u32_e64 v6, s[0:1], 0, v2, s[0:1] 1032; GCN-NEXT: v_subb_u32_e32 v1, vcc, 0, v1, vcc 1033; GCN-NEXT: v_add_i32_e64 v7, s[0:1], 1, v0 1034; GCN-NEXT: v_addc_u32_e64 v2, s[0:1], 0, v2, s[0:1] 1035; GCN-NEXT: v_cmp_le_u32_e32 vcc, s7, v1 1036; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v4 1037; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc 1038; GCN-NEXT: v_cmp_le_u32_e32 vcc, s6, v3 1039; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc 1040; GCN-NEXT: v_cmp_eq_u32_e32 vcc, s7, v1 1041; GCN-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc 1042; GCN-NEXT: v_cndmask_b32_e64 v2, v2, v6, s[0:1] 1043; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1 1044; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc 1045; GCN-NEXT: v_cndmask_b32_e64 v2, v7, v5, s[0:1] 1046; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc 1047; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 1048; GCN-NEXT: s_endpgm 1049; 1050; GCN-IR-LABEL: s_test_udiv_k_num_i64: 1051; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1052; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1053; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 1054; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6 1055; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7 1056; GCN-IR-NEXT: s_add_i32 s2, s2, 32 1057; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 1058; GCN-IR-NEXT: v_mov_b32_e32 v1, s2 1059; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 1060; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 1061; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc5, v2 1062; GCN-IR-NEXT: v_addc_u32_e64 v1, s[2:3], 0, -1, vcc 1063; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 1064; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] 1065; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc 1066; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] 1067; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1 1068; GCN-IR-NEXT: s_and_b64 s[2:3], s[2:3], vcc 1069; GCN-IR-NEXT: s_and_b64 vcc, exec, s[2:3] 1070; GCN-IR-NEXT: s_cbranch_vccz BB8_4 1071; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1072; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0 1073; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc 1074; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1] 1075; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 1076; GCN-IR-NEXT: v_lshl_b64 v[0:1], 24, v0 1077; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1] 1078; GCN-IR-NEXT: s_cbranch_vccz BB8_5 1079; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1080; GCN-IR-NEXT: s_add_u32 s2, s6, -1 1081; GCN-IR-NEXT: v_lshr_b64 v[6:7], 24, v3 1082; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 58, v2 1083; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 1084; GCN-IR-NEXT: s_addc_u32 s3, s7, -1 1085; GCN-IR-NEXT: v_subb_u32_e64 v5, s[0:1], 0, 0, vcc 1086; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 1087; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 1088; GCN-IR-NEXT: BB8_3: ; %udiv-do-while 1089; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1090; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 1091; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 1092; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 1093; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 1094; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 1095; GCN-IR-NEXT: v_mov_b32_e32 v2, s3 1096; GCN-IR-NEXT: v_sub_i32_e32 v8, vcc, s2, v6 1097; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, v2, v7, vcc 1098; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 1099; GCN-IR-NEXT: v_and_b32_e32 v10, s6, v8 1100; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 1101; GCN-IR-NEXT: v_and_b32_e32 v11, s7, v8 1102; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 1103; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 1104; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc 1105; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] 1106; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 1107; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 1108; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 1109; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 1110; GCN-IR-NEXT: v_subb_u32_e64 v7, s[0:1], v7, v11, s[0:1] 1111; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc 1112; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 1113; GCN-IR-NEXT: s_cbranch_vccz BB8_3 1114; GCN-IR-NEXT: s_branch BB8_6 1115; GCN-IR-NEXT: BB8_4: 1116; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 1117; GCN-IR-NEXT: v_cndmask_b32_e64 v0, 24, 0, s[0:1] 1118; GCN-IR-NEXT: s_branch BB8_7 1119; GCN-IR-NEXT: BB8_5: 1120; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 1121; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 1122; GCN-IR-NEXT: BB8_6: ; %Flow5 1123; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 1124; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 1125; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 1126; GCN-IR-NEXT: BB8_7: ; %udiv-end 1127; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 1128; GCN-IR-NEXT: s_mov_b32 s6, -1 1129; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1130; GCN-IR-NEXT: s_endpgm 1131 %result = udiv i64 24, %x 1132 store i64 %result, i64 addrspace(1)* %out 1133 ret void 1134} 1135 1136; define i64 @v_test_udiv_k_num_i64(i64 %x) { 1137; %result = udiv i64 24, %x 1138; ret i64 %result 1139; } 1140 1141define i64 @v_test_udiv_pow2_k_num_i64(i64 %x) { 1142; GCN-LABEL: v_test_udiv_pow2_k_num_i64: 1143; GCN: ; %bb.0: 1144; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1145; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0 1146; GCN-NEXT: v_cvt_f32_u32_e32 v3, v1 1147; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0, v0 1148; GCN-NEXT: v_subb_u32_e32 v5, vcc, 0, v1, vcc 1149; GCN-NEXT: v_mov_b32_e32 v12, 0 1150; GCN-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3 1151; GCN-NEXT: v_rcp_f32_e32 v2, v2 1152; GCN-NEXT: v_mov_b32_e32 v11, 0 1153; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 1154; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 1155; GCN-NEXT: v_trunc_f32_e32 v3, v3 1156; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 1157; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 1158; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 1159; GCN-NEXT: v_mul_hi_u32 v7, v4, v2 1160; GCN-NEXT: v_mul_lo_u32 v6, v4, v3 1161; GCN-NEXT: v_mul_lo_u32 v8, v5, v2 1162; GCN-NEXT: v_mul_lo_u32 v9, v4, v2 1163; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 1164; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v8 1165; GCN-NEXT: v_mul_lo_u32 v8, v2, v6 1166; GCN-NEXT: v_mul_hi_u32 v10, v2, v9 1167; GCN-NEXT: v_mul_hi_u32 v7, v2, v6 1168; GCN-NEXT: v_mul_hi_u32 v13, v3, v6 1169; GCN-NEXT: v_mul_lo_u32 v6, v3, v6 1170; GCN-NEXT: v_add_i32_e32 v8, vcc, v10, v8 1171; GCN-NEXT: v_mul_lo_u32 v10, v3, v9 1172; GCN-NEXT: v_mul_hi_u32 v9, v3, v9 1173; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v7, vcc 1174; GCN-NEXT: v_add_i32_e32 v8, vcc, v8, v10 1175; GCN-NEXT: v_addc_u32_e32 v7, vcc, v7, v9, vcc 1176; GCN-NEXT: v_addc_u32_e32 v8, vcc, v13, v11, vcc 1177; GCN-NEXT: v_add_i32_e32 v6, vcc, v7, v6 1178; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v6 1179; GCN-NEXT: v_addc_u32_e32 v7, vcc, v12, v8, vcc 1180; GCN-NEXT: v_addc_u32_e64 v6, vcc, v3, v7, s[4:5] 1181; GCN-NEXT: v_mul_lo_u32 v8, v4, v6 1182; GCN-NEXT: v_mul_hi_u32 v9, v4, v2 1183; GCN-NEXT: v_mul_lo_u32 v5, v5, v2 1184; GCN-NEXT: v_mul_lo_u32 v4, v4, v2 1185; GCN-NEXT: v_add_i32_e32 v8, vcc, v9, v8 1186; GCN-NEXT: v_add_i32_e32 v5, vcc, v8, v5 1187; GCN-NEXT: v_mul_lo_u32 v10, v2, v5 1188; GCN-NEXT: v_mul_hi_u32 v13, v2, v4 1189; GCN-NEXT: v_mul_hi_u32 v14, v2, v5 1190; GCN-NEXT: v_mul_hi_u32 v9, v6, v4 1191; GCN-NEXT: v_mul_lo_u32 v4, v6, v4 1192; GCN-NEXT: v_add_i32_e32 v10, vcc, v13, v10 1193; GCN-NEXT: v_mul_hi_u32 v8, v6, v5 1194; GCN-NEXT: v_addc_u32_e32 v13, vcc, v12, v14, vcc 1195; GCN-NEXT: v_mul_lo_u32 v5, v6, v5 1196; GCN-NEXT: v_add_i32_e32 v4, vcc, v10, v4 1197; GCN-NEXT: v_addc_u32_e32 v4, vcc, v13, v9, vcc 1198; GCN-NEXT: v_addc_u32_e32 v6, vcc, v8, v11, vcc 1199; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 1200; GCN-NEXT: v_addc_u32_e32 v5, vcc, v12, v6, vcc 1201; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v7 1202; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v5, s[4:5] 1203; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 1204; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc 1205; GCN-NEXT: v_lshrrev_b32_e32 v2, 17, v2 1206; GCN-NEXT: v_mul_lo_u32 v3, v1, v2 1207; GCN-NEXT: v_mul_hi_u32 v4, v0, v2 1208; GCN-NEXT: v_add_i32_e32 v3, vcc, v4, v3 1209; GCN-NEXT: v_mul_lo_u32 v4, v0, v2 1210; GCN-NEXT: v_sub_i32_e32 v5, vcc, 0, v3 1211; GCN-NEXT: v_sub_i32_e32 v4, vcc, 0x8000, v4 1212; GCN-NEXT: v_subb_u32_e64 v5, s[4:5], v5, v1, vcc 1213; GCN-NEXT: v_sub_i32_e64 v6, s[4:5], v4, v0 1214; GCN-NEXT: v_subbrev_u32_e64 v5, s[4:5], 0, v5, s[4:5] 1215; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v5, v1 1216; GCN-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] 1217; GCN-NEXT: v_cmp_ge_u32_e64 s[4:5], v6, v0 1218; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, s[4:5] 1219; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], v5, v1 1220; GCN-NEXT: v_cndmask_b32_e64 v5, v7, v6, s[4:5] 1221; GCN-NEXT: v_add_i32_e64 v6, s[4:5], 2, v2 1222; GCN-NEXT: v_addc_u32_e64 v7, s[4:5], 0, v12, s[4:5] 1223; GCN-NEXT: v_add_i32_e64 v8, s[4:5], 1, v2 1224; GCN-NEXT: v_subb_u32_e32 v3, vcc, 0, v3, vcc 1225; GCN-NEXT: v_addc_u32_e64 v9, s[4:5], 0, v12, s[4:5] 1226; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v5 1227; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v3, v1 1228; GCN-NEXT: v_cndmask_b32_e64 v5, v8, v6, s[4:5] 1229; GCN-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc 1230; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v4, v0 1231; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc 1232; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v3, v1 1233; GCN-NEXT: v_cndmask_b32_e32 v0, v6, v0, vcc 1234; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 1235; GCN-NEXT: v_cndmask_b32_e64 v1, v9, v7, s[4:5] 1236; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v5, vcc 1237; GCN-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc 1238; GCN-NEXT: s_setpc_b64 s[30:31] 1239; 1240; GCN-IR-LABEL: v_test_udiv_pow2_k_num_i64: 1241; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1242; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1243; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 1244; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, 32, v2 1245; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 1246; GCN-IR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 1247; GCN-IR-NEXT: v_cndmask_b32_e32 v4, v3, v2, vcc 1248; GCN-IR-NEXT: v_add_i32_e32 v5, vcc, 0xffffffd0, v4 1249; GCN-IR-NEXT: v_addc_u32_e64 v6, s[6:7], 0, -1, vcc 1250; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[4:5], 0, v[0:1] 1251; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[5:6] 1252; GCN-IR-NEXT: s_mov_b64 s[8:9], 0x8000 1253; GCN-IR-NEXT: s_or_b64 s[4:5], s[4:5], vcc 1254; GCN-IR-NEXT: v_mov_b32_e32 v2, s8 1255; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[5:6] 1256; GCN-IR-NEXT: v_mov_b32_e32 v7, 0 1257; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5] 1258; GCN-IR-NEXT: s_xor_b64 s[4:5], s[4:5], -1 1259; GCN-IR-NEXT: v_mov_b32_e32 v3, v7 1260; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], vcc 1261; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] 1262; GCN-IR-NEXT: s_cbranch_execz BB9_6 1263; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1264; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v5 1265; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v6, vcc 1266; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v5 1267; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[8:9], v[5:6] 1268; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 1269; GCN-IR-NEXT: v_lshl_b64 v[2:3], s[8:9], v2 1270; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 1271; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 1272; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc 1273; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] 1274; GCN-IR-NEXT: s_cbranch_execz BB9_5 1275; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1276; GCN-IR-NEXT: s_mov_b64 s[4:5], 0x8000 1277; GCN-IR-NEXT: v_lshr_b64 v[12:13], s[4:5], v8 1278; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, -1, v0 1279; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, -1, v1, vcc 1280; GCN-IR-NEXT: v_sub_i32_e32 v10, vcc, 47, v4 1281; GCN-IR-NEXT: v_mov_b32_e32 v14, 0 1282; GCN-IR-NEXT: v_mov_b32_e32 v15, 0 1283; GCN-IR-NEXT: v_subb_u32_e32 v11, vcc, 0, v7, vcc 1284; GCN-IR-NEXT: BB9_3: ; %udiv-do-while 1285; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1286; GCN-IR-NEXT: v_lshl_b64 v[12:13], v[12:13], 1 1287; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 1288; GCN-IR-NEXT: v_or_b32_e32 v4, v12, v4 1289; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 1290; GCN-IR-NEXT: v_sub_i32_e32 v5, vcc, v8, v4 1291; GCN-IR-NEXT: v_subb_u32_e32 v5, vcc, v9, v13, vcc 1292; GCN-IR-NEXT: v_or_b32_e32 v2, v14, v2 1293; GCN-IR-NEXT: v_add_i32_e32 v14, vcc, 1, v10 1294; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v5 1295; GCN-IR-NEXT: v_or_b32_e32 v3, v15, v3 1296; GCN-IR-NEXT: v_addc_u32_e32 v15, vcc, 0, v11, vcc 1297; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[14:15], v[10:11] 1298; GCN-IR-NEXT: v_mov_b32_e32 v10, v14 1299; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 1300; GCN-IR-NEXT: v_and_b32_e32 v5, 1, v7 1301; GCN-IR-NEXT: v_and_b32_e32 v16, v7, v1 1302; GCN-IR-NEXT: v_and_b32_e32 v7, v7, v0 1303; GCN-IR-NEXT: v_sub_i32_e64 v12, s[4:5], v4, v7 1304; GCN-IR-NEXT: v_mov_b32_e32 v11, v15 1305; GCN-IR-NEXT: v_mov_b32_e32 v15, v6 1306; GCN-IR-NEXT: v_subb_u32_e64 v13, s[4:5], v13, v16, s[4:5] 1307; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] 1308; GCN-IR-NEXT: v_mov_b32_e32 v14, v5 1309; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] 1310; GCN-IR-NEXT: s_cbranch_execnz BB9_3 1311; GCN-IR-NEXT: ; %bb.4: ; %Flow 1312; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] 1313; GCN-IR-NEXT: BB9_5: ; %Flow3 1314; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] 1315; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 1316; GCN-IR-NEXT: v_or_b32_e32 v3, v6, v1 1317; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v0 1318; GCN-IR-NEXT: BB9_6: ; %Flow4 1319; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] 1320; GCN-IR-NEXT: v_mov_b32_e32 v0, v2 1321; GCN-IR-NEXT: v_mov_b32_e32 v1, v3 1322; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1323 %result = udiv i64 32768, %x 1324 ret i64 %result 1325} 1326 1327define i64 @v_test_udiv_pow2_k_den_i64(i64 %x) { 1328; GCN-LABEL: v_test_udiv_pow2_k_den_i64: 1329; GCN: ; %bb.0: 1330; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1331; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 15 1332; GCN-NEXT: v_lshrrev_b32_e32 v1, 15, v1 1333; GCN-NEXT: s_setpc_b64 s[30:31] 1334; 1335; GCN-IR-LABEL: v_test_udiv_pow2_k_den_i64: 1336; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1337; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1338; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 1339; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 1340; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 1341; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 1342; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v3, v2, s[4:5] 1343; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 48, v6 1344; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] 1345; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] 1346; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] 1347; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] 1348; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] 1349; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 1350; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] 1351; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] 1352; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc 1353; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] 1354; GCN-IR-NEXT: s_cbranch_execz BB10_6 1355; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1356; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 1357; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc 1358; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 1359; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5] 1360; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 1361; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 1362; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 1363; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 1364; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc 1365; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] 1366; GCN-IR-NEXT: s_cbranch_execz BB10_5 1367; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1368; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 1369; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffcf, v6 1370; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 1371; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc 1372; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 1373; GCN-IR-NEXT: s_movk_i32 s12, 0x7fff 1374; GCN-IR-NEXT: BB10_3: ; %udiv-do-while 1375; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1376; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 1377; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 1378; GCN-IR-NEXT: v_or_b32_e32 v7, v7, v4 1379; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 1380; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, s12, v7 1381; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc 1382; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 1383; GCN-IR-NEXT: v_ashrrev_i32_e32 v9, 31, v4 1384; GCN-IR-NEXT: v_and_b32_e32 v11, 0x8000, v9 1385; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v9 1386; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 1387; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 1388; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc 1389; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1] 1390; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 1391; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 1392; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 1393; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 1394; GCN-IR-NEXT: v_mov_b32_e32 v6, 0 1395; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v7, v11 1396; GCN-IR-NEXT: v_subb_u32_e64 v8, s[4:5], v8, v6, s[4:5] 1397; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] 1398; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 1399; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] 1400; GCN-IR-NEXT: s_cbranch_execnz BB10_3 1401; GCN-IR-NEXT: ; %bb.4: ; %Flow 1402; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] 1403; GCN-IR-NEXT: BB10_5: ; %Flow3 1404; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] 1405; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 1406; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 1407; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0 1408; GCN-IR-NEXT: BB10_6: ; %Flow4 1409; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] 1410; GCN-IR-NEXT: v_mov_b32_e32 v0, v3 1411; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 1412; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1413 %result = udiv i64 %x, 32768 1414 ret i64 %result 1415} 1416 1417define amdgpu_kernel void @s_test_udiv_k_den_i64(i64 addrspace(1)* %out, i64 %x) { 1418; GCN-LABEL: s_test_udiv_k_den_i64: 1419; GCN: ; %bb.0: 1420; GCN-NEXT: v_mov_b32_e32 v0, 0x4f800000 1421; GCN-NEXT: v_madak_f32 v0, 0, v0, 0x41c00000 1422; GCN-NEXT: v_rcp_f32_e32 v0, v0 1423; GCN-NEXT: s_movk_i32 s2, 0xffe8 1424; GCN-NEXT: v_mov_b32_e32 v8, 0 1425; GCN-NEXT: v_mov_b32_e32 v7, 0 1426; GCN-NEXT: v_mul_f32_e32 v0, 0x5f7ffffc, v0 1427; GCN-NEXT: v_mul_f32_e32 v1, 0x2f800000, v0 1428; GCN-NEXT: v_trunc_f32_e32 v1, v1 1429; GCN-NEXT: v_mac_f32_e32 v0, 0xcf800000, v1 1430; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 1431; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 1432; GCN-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9 1433; GCN-NEXT: s_mov_b32 s7, 0xf000 1434; GCN-NEXT: v_mul_hi_u32 v2, v0, s2 1435; GCN-NEXT: v_mul_lo_u32 v3, v1, s2 1436; GCN-NEXT: v_mul_lo_u32 v4, v0, s2 1437; GCN-NEXT: s_mov_b32 s6, -1 1438; GCN-NEXT: v_subrev_i32_e32 v2, vcc, v0, v2 1439; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 1440; GCN-NEXT: v_mul_lo_u32 v5, v0, v2 1441; GCN-NEXT: v_mul_hi_u32 v6, v0, v4 1442; GCN-NEXT: v_mul_hi_u32 v3, v0, v2 1443; GCN-NEXT: v_mul_hi_u32 v9, v1, v2 1444; GCN-NEXT: v_mul_lo_u32 v2, v1, v2 1445; GCN-NEXT: v_add_i32_e32 v5, vcc, v6, v5 1446; GCN-NEXT: v_mul_lo_u32 v6, v1, v4 1447; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 1448; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v3, vcc 1449; GCN-NEXT: s_waitcnt lgkmcnt(0) 1450; GCN-NEXT: s_mov_b32 s4, s8 1451; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v6 1452; GCN-NEXT: v_addc_u32_e32 v3, vcc, v3, v4, vcc 1453; GCN-NEXT: v_addc_u32_e32 v4, vcc, v9, v7, vcc 1454; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 1455; GCN-NEXT: v_add_i32_e64 v0, s[0:1], v0, v2 1456; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc 1457; GCN-NEXT: v_mul_hi_u32 v4, v0, s2 1458; GCN-NEXT: v_addc_u32_e64 v2, vcc, v1, v3, s[0:1] 1459; GCN-NEXT: v_mul_lo_u32 v5, v2, s2 1460; GCN-NEXT: v_mul_lo_u32 v6, v0, s2 1461; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v0, v4 1462; GCN-NEXT: s_mov_b32 s5, s9 1463; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v5 1464; GCN-NEXT: v_mul_lo_u32 v5, v0, v4 1465; GCN-NEXT: v_mul_hi_u32 v9, v0, v6 1466; GCN-NEXT: v_mul_hi_u32 v10, v0, v4 1467; GCN-NEXT: v_mul_hi_u32 v11, v2, v4 1468; GCN-NEXT: v_add_i32_e32 v5, vcc, v9, v5 1469; GCN-NEXT: v_addc_u32_e32 v9, vcc, v8, v10, vcc 1470; GCN-NEXT: v_mul_lo_u32 v10, v2, v6 1471; GCN-NEXT: v_mul_hi_u32 v6, v2, v6 1472; GCN-NEXT: v_mul_lo_u32 v2, v2, v4 1473; GCN-NEXT: v_add_i32_e32 v5, vcc, v5, v10 1474; GCN-NEXT: v_addc_u32_e32 v5, vcc, v9, v6, vcc 1475; GCN-NEXT: v_addc_u32_e32 v4, vcc, v11, v7, vcc 1476; GCN-NEXT: v_add_i32_e32 v2, vcc, v5, v2 1477; GCN-NEXT: v_addc_u32_e32 v4, vcc, v8, v4, vcc 1478; GCN-NEXT: v_add_i32_e32 v1, vcc, v1, v3 1479; GCN-NEXT: v_addc_u32_e64 v1, vcc, v1, v4, s[0:1] 1480; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v2 1481; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc 1482; GCN-NEXT: v_mul_lo_u32 v2, s10, v1 1483; GCN-NEXT: v_mul_hi_u32 v3, s10, v0 1484; GCN-NEXT: v_mul_hi_u32 v4, s10, v1 1485; GCN-NEXT: v_mul_hi_u32 v5, s11, v1 1486; GCN-NEXT: v_mul_lo_u32 v1, s11, v1 1487; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 1488; GCN-NEXT: v_addc_u32_e32 v3, vcc, v8, v4, vcc 1489; GCN-NEXT: v_mul_lo_u32 v4, s11, v0 1490; GCN-NEXT: v_mul_hi_u32 v0, s11, v0 1491; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 1492; GCN-NEXT: v_addc_u32_e32 v0, vcc, v3, v0, vcc 1493; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v7, vcc 1494; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 1495; GCN-NEXT: v_addc_u32_e32 v1, vcc, v8, v2, vcc 1496; GCN-NEXT: v_mul_lo_u32 v2, v1, 24 1497; GCN-NEXT: v_mul_hi_u32 v3, v0, 24 1498; GCN-NEXT: v_mul_lo_u32 v4, v0, 24 1499; GCN-NEXT: v_add_i32_e32 v2, vcc, v3, v2 1500; GCN-NEXT: v_sub_i32_e32 v4, vcc, s10, v4 1501; GCN-NEXT: v_mov_b32_e32 v3, s11 1502; GCN-NEXT: v_subb_u32_e32 v2, vcc, v3, v2, vcc 1503; GCN-NEXT: v_subrev_i32_e32 v3, vcc, 24, v4 1504; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v2, vcc 1505; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v3 1506; GCN-NEXT: v_cndmask_b32_e64 v3, 0, -1, vcc 1507; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 1508; GCN-NEXT: v_cndmask_b32_e32 v3, -1, v3, vcc 1509; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v0 1510; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v1, vcc 1511; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v0 1512; GCN-NEXT: v_cmp_lt_u32_e64 s[0:1], 23, v4 1513; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc 1514; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[0:1] 1515; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], 0, v2 1516; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v3 1517; GCN-NEXT: v_cndmask_b32_e64 v2, -1, v4, s[0:1] 1518; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v2 1519; GCN-NEXT: v_cndmask_b32_e32 v3, v8, v6, vcc 1520; GCN-NEXT: v_cndmask_b32_e32 v2, v7, v5, vcc 1521; GCN-NEXT: v_cndmask_b32_e64 v1, v1, v3, s[0:1] 1522; GCN-NEXT: v_cndmask_b32_e64 v0, v0, v2, s[0:1] 1523; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1524; GCN-NEXT: s_endpgm 1525; 1526; GCN-IR-LABEL: s_test_udiv_k_den_i64: 1527; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1528; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 1529; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 1530; GCN-IR-NEXT: s_flbit_i32_b32 s2, s6 1531; GCN-IR-NEXT: s_flbit_i32_b32 s3, s7 1532; GCN-IR-NEXT: s_add_i32 s2, s2, 32 1533; GCN-IR-NEXT: v_mov_b32_e32 v0, s3 1534; GCN-IR-NEXT: v_mov_b32_e32 v1, s2 1535; GCN-IR-NEXT: v_cmp_eq_u32_e64 vcc, s7, 0 1536; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc 1537; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 59, v2 1538; GCN-IR-NEXT: v_subb_u32_e64 v1, s[2:3], 0, 0, vcc 1539; GCN-IR-NEXT: v_cmp_eq_u64_e64 s[0:1], s[6:7], 0 1540; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, 63, v[0:1] 1541; GCN-IR-NEXT: s_or_b64 s[0:1], s[0:1], vcc 1542; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[0:1] 1543; GCN-IR-NEXT: s_xor_b64 s[2:3], s[0:1], -1 1544; GCN-IR-NEXT: s_and_b64 s[2:3], s[2:3], vcc 1545; GCN-IR-NEXT: s_and_b64 vcc, exec, s[2:3] 1546; GCN-IR-NEXT: s_cbranch_vccz BB11_4 1547; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1548; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v0 1549; GCN-IR-NEXT: v_addc_u32_e32 v4, vcc, 0, v1, vcc 1550; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[0:1], v[3:4], v[0:1] 1551; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, 63, v0 1552; GCN-IR-NEXT: v_lshl_b64 v[0:1], s[6:7], v0 1553; GCN-IR-NEXT: s_andn2_b64 vcc, exec, s[0:1] 1554; GCN-IR-NEXT: s_cbranch_vccz BB11_5 1555; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1556; GCN-IR-NEXT: v_lshr_b64 v[6:7], s[6:7], v3 1557; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 0xffffffc4, v2 1558; GCN-IR-NEXT: v_mov_b32_e32 v8, 0 1559; GCN-IR-NEXT: v_addc_u32_e64 v5, s[0:1], 0, -1, vcc 1560; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 1561; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 1562; GCN-IR-NEXT: BB11_3: ; %udiv-do-while 1563; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1564; GCN-IR-NEXT: v_lshl_b64 v[6:7], v[6:7], 1 1565; GCN-IR-NEXT: v_lshrrev_b32_e32 v2, 31, v1 1566; GCN-IR-NEXT: v_or_b32_e32 v6, v6, v2 1567; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 1568; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, 23, v6 1569; GCN-IR-NEXT: v_subb_u32_e32 v2, vcc, 0, v7, vcc 1570; GCN-IR-NEXT: v_or_b32_e32 v0, v8, v0 1571; GCN-IR-NEXT: v_ashrrev_i32_e32 v8, 31, v2 1572; GCN-IR-NEXT: v_and_b32_e32 v10, 24, v8 1573; GCN-IR-NEXT: v_and_b32_e32 v2, 1, v8 1574; GCN-IR-NEXT: v_add_i32_e32 v8, vcc, 1, v4 1575; GCN-IR-NEXT: v_or_b32_e32 v1, v9, v1 1576; GCN-IR-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc 1577; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] 1578; GCN-IR-NEXT: v_mov_b32_e32 v4, v8 1579; GCN-IR-NEXT: v_sub_i32_e64 v6, s[0:1], v6, v10 1580; GCN-IR-NEXT: v_mov_b32_e32 v5, v9 1581; GCN-IR-NEXT: v_mov_b32_e32 v9, v3 1582; GCN-IR-NEXT: v_subbrev_u32_e64 v7, s[0:1], 0, v7, s[0:1] 1583; GCN-IR-NEXT: s_and_b64 vcc, exec, vcc 1584; GCN-IR-NEXT: v_mov_b32_e32 v8, v2 1585; GCN-IR-NEXT: s_cbranch_vccz BB11_3 1586; GCN-IR-NEXT: s_branch BB11_6 1587; GCN-IR-NEXT: BB11_4: 1588; GCN-IR-NEXT: v_mov_b32_e32 v0, s7 1589; GCN-IR-NEXT: v_cndmask_b32_e64 v1, v0, 0, s[0:1] 1590; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 1591; GCN-IR-NEXT: v_cndmask_b32_e64 v0, v0, 0, s[0:1] 1592; GCN-IR-NEXT: s_branch BB11_7 1593; GCN-IR-NEXT: BB11_5: 1594; GCN-IR-NEXT: v_mov_b32_e32 v2, 0 1595; GCN-IR-NEXT: v_mov_b32_e32 v3, 0 1596; GCN-IR-NEXT: BB11_6: ; %Flow5 1597; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[0:1], 1 1598; GCN-IR-NEXT: v_or_b32_e32 v0, v2, v0 1599; GCN-IR-NEXT: v_or_b32_e32 v1, v3, v1 1600; GCN-IR-NEXT: BB11_7: ; %udiv-end 1601; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 1602; GCN-IR-NEXT: s_mov_b32 s6, -1 1603; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1604; GCN-IR-NEXT: s_endpgm 1605 %result = udiv i64 %x, 24 1606 store i64 %result, i64 addrspace(1)* %out 1607 ret void 1608} 1609 1610define i64 @v_test_udiv_k_den_i64(i64 %x) { 1611; GCN-LABEL: v_test_udiv_k_den_i64: 1612; GCN: ; %bb.0: 1613; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1614; GCN-NEXT: v_mov_b32_e32 v2, 0x4f800000 1615; GCN-NEXT: v_madak_f32 v2, 0, v2, 0x41c00000 1616; GCN-NEXT: v_rcp_f32_e32 v2, v2 1617; GCN-NEXT: s_movk_i32 s6, 0xffe8 1618; GCN-NEXT: v_mov_b32_e32 v10, 0 1619; GCN-NEXT: v_mov_b32_e32 v9, 0 1620; GCN-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 1621; GCN-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 1622; GCN-NEXT: v_trunc_f32_e32 v3, v3 1623; GCN-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 1624; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 1625; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 1626; GCN-NEXT: v_mul_hi_u32 v4, v2, s6 1627; GCN-NEXT: v_mul_lo_u32 v5, v3, s6 1628; GCN-NEXT: v_mul_lo_u32 v6, v2, s6 1629; GCN-NEXT: v_subrev_i32_e32 v4, vcc, v2, v4 1630; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 1631; GCN-NEXT: v_mul_lo_u32 v7, v2, v4 1632; GCN-NEXT: v_mul_hi_u32 v8, v2, v6 1633; GCN-NEXT: v_mul_hi_u32 v5, v2, v4 1634; GCN-NEXT: v_mul_hi_u32 v11, v3, v4 1635; GCN-NEXT: v_mul_lo_u32 v4, v3, v4 1636; GCN-NEXT: v_add_i32_e32 v7, vcc, v8, v7 1637; GCN-NEXT: v_mul_lo_u32 v8, v3, v6 1638; GCN-NEXT: v_mul_hi_u32 v6, v3, v6 1639; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v5, vcc 1640; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v8 1641; GCN-NEXT: v_addc_u32_e32 v5, vcc, v5, v6, vcc 1642; GCN-NEXT: v_addc_u32_e32 v6, vcc, v11, v9, vcc 1643; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 1644; GCN-NEXT: v_add_i32_e64 v2, s[4:5], v2, v4 1645; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc 1646; GCN-NEXT: v_mul_hi_u32 v6, v2, s6 1647; GCN-NEXT: v_addc_u32_e64 v4, vcc, v3, v5, s[4:5] 1648; GCN-NEXT: v_mul_lo_u32 v7, v4, s6 1649; GCN-NEXT: v_mul_lo_u32 v8, v2, s6 1650; GCN-NEXT: v_subrev_i32_e32 v6, vcc, v2, v6 1651; GCN-NEXT: v_add_i32_e32 v6, vcc, v6, v7 1652; GCN-NEXT: v_mul_lo_u32 v7, v2, v6 1653; GCN-NEXT: v_mul_hi_u32 v11, v2, v8 1654; GCN-NEXT: v_mul_hi_u32 v12, v2, v6 1655; GCN-NEXT: v_mul_hi_u32 v13, v4, v6 1656; GCN-NEXT: v_add_i32_e32 v7, vcc, v11, v7 1657; GCN-NEXT: v_addc_u32_e32 v11, vcc, v10, v12, vcc 1658; GCN-NEXT: v_mul_lo_u32 v12, v4, v8 1659; GCN-NEXT: v_mul_hi_u32 v8, v4, v8 1660; GCN-NEXT: v_mul_lo_u32 v4, v4, v6 1661; GCN-NEXT: v_add_i32_e32 v7, vcc, v7, v12 1662; GCN-NEXT: v_addc_u32_e32 v7, vcc, v11, v8, vcc 1663; GCN-NEXT: v_addc_u32_e32 v6, vcc, v13, v9, vcc 1664; GCN-NEXT: v_add_i32_e32 v4, vcc, v7, v4 1665; GCN-NEXT: v_addc_u32_e32 v6, vcc, v10, v6, vcc 1666; GCN-NEXT: v_add_i32_e32 v3, vcc, v3, v5 1667; GCN-NEXT: v_addc_u32_e64 v3, vcc, v3, v6, s[4:5] 1668; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v4 1669; GCN-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc 1670; GCN-NEXT: v_mul_lo_u32 v4, v0, v3 1671; GCN-NEXT: v_mul_hi_u32 v5, v0, v2 1672; GCN-NEXT: v_mul_hi_u32 v6, v0, v3 1673; GCN-NEXT: v_mul_hi_u32 v7, v1, v3 1674; GCN-NEXT: v_mul_lo_u32 v3, v1, v3 1675; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 1676; GCN-NEXT: v_addc_u32_e32 v5, vcc, v10, v6, vcc 1677; GCN-NEXT: v_mul_lo_u32 v6, v1, v2 1678; GCN-NEXT: v_mul_hi_u32 v2, v1, v2 1679; GCN-NEXT: v_add_i32_e32 v4, vcc, v4, v6 1680; GCN-NEXT: v_addc_u32_e32 v2, vcc, v5, v2, vcc 1681; GCN-NEXT: v_addc_u32_e32 v4, vcc, v7, v9, vcc 1682; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 1683; GCN-NEXT: v_addc_u32_e32 v3, vcc, v10, v4, vcc 1684; GCN-NEXT: v_mul_lo_u32 v4, v3, 24 1685; GCN-NEXT: v_mul_hi_u32 v5, v2, 24 1686; GCN-NEXT: v_mul_lo_u32 v6, v2, 24 1687; GCN-NEXT: v_add_i32_e32 v4, vcc, v5, v4 1688; GCN-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 1689; GCN-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc 1690; GCN-NEXT: v_subrev_i32_e32 v4, vcc, 24, v0 1691; GCN-NEXT: v_subbrev_u32_e32 v5, vcc, 0, v1, vcc 1692; GCN-NEXT: v_cmp_lt_u32_e32 vcc, 23, v4 1693; GCN-NEXT: v_cndmask_b32_e64 v4, 0, -1, vcc 1694; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 1695; GCN-NEXT: v_cndmask_b32_e32 v4, -1, v4, vcc 1696; GCN-NEXT: v_add_i32_e32 v5, vcc, 2, v2 1697; GCN-NEXT: v_addc_u32_e32 v6, vcc, 0, v3, vcc 1698; GCN-NEXT: v_add_i32_e32 v7, vcc, 1, v2 1699; GCN-NEXT: v_cmp_lt_u32_e64 s[4:5], 23, v0 1700; GCN-NEXT: v_addc_u32_e32 v8, vcc, 0, v3, vcc 1701; GCN-NEXT: v_cndmask_b32_e64 v0, 0, -1, s[4:5] 1702; GCN-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 1703; GCN-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 1704; GCN-NEXT: v_cndmask_b32_e64 v0, -1, v0, s[4:5] 1705; GCN-NEXT: v_cndmask_b32_e32 v4, v7, v5, vcc 1706; GCN-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, v0 1707; GCN-NEXT: v_cndmask_b32_e32 v1, v8, v6, vcc 1708; GCN-NEXT: v_cndmask_b32_e64 v0, v2, v4, s[4:5] 1709; GCN-NEXT: v_cndmask_b32_e64 v1, v3, v1, s[4:5] 1710; GCN-NEXT: s_setpc_b64 s[30:31] 1711; 1712; GCN-IR-LABEL: v_test_udiv_k_den_i64: 1713; GCN-IR: ; %bb.0: ; %_udiv-special-cases 1714; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1715; GCN-IR-NEXT: v_ffbh_u32_e32 v2, v0 1716; GCN-IR-NEXT: v_add_i32_e64 v2, s[4:5], 32, v2 1717; GCN-IR-NEXT: v_ffbh_u32_e32 v3, v1 1718; GCN-IR-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v1 1719; GCN-IR-NEXT: v_cndmask_b32_e64 v6, v3, v2, s[4:5] 1720; GCN-IR-NEXT: v_sub_i32_e64 v4, s[4:5], 59, v6 1721; GCN-IR-NEXT: v_subb_u32_e64 v5, s[4:5], 0, 0, s[4:5] 1722; GCN-IR-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1] 1723; GCN-IR-NEXT: v_cmp_lt_u64_e64 s[4:5], 63, v[4:5] 1724; GCN-IR-NEXT: s_or_b64 s[4:5], vcc, s[4:5] 1725; GCN-IR-NEXT: v_cmp_ne_u64_e32 vcc, 63, v[4:5] 1726; GCN-IR-NEXT: s_xor_b64 s[6:7], s[4:5], -1 1727; GCN-IR-NEXT: v_cndmask_b32_e64 v2, v1, 0, s[4:5] 1728; GCN-IR-NEXT: v_cndmask_b32_e64 v3, v0, 0, s[4:5] 1729; GCN-IR-NEXT: s_and_b64 s[4:5], s[6:7], vcc 1730; GCN-IR-NEXT: s_and_saveexec_b64 s[6:7], s[4:5] 1731; GCN-IR-NEXT: s_cbranch_execz BB12_6 1732; GCN-IR-NEXT: ; %bb.1: ; %udiv-bb1 1733; GCN-IR-NEXT: v_add_i32_e32 v7, vcc, 1, v4 1734; GCN-IR-NEXT: v_addc_u32_e32 v8, vcc, 0, v5, vcc 1735; GCN-IR-NEXT: v_sub_i32_e64 v2, s[4:5], 63, v4 1736; GCN-IR-NEXT: v_cmp_ge_u64_e32 vcc, v[7:8], v[4:5] 1737; GCN-IR-NEXT: v_mov_b32_e32 v4, 0 1738; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[0:1], v2 1739; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 1740; GCN-IR-NEXT: s_mov_b64 s[10:11], 0 1741; GCN-IR-NEXT: s_and_saveexec_b64 s[4:5], vcc 1742; GCN-IR-NEXT: s_xor_b64 s[8:9], exec, s[4:5] 1743; GCN-IR-NEXT: s_cbranch_execz BB12_5 1744; GCN-IR-NEXT: ; %bb.2: ; %udiv-preheader 1745; GCN-IR-NEXT: v_lshr_b64 v[7:8], v[0:1], v7 1746; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, 0xffffffc4, v6 1747; GCN-IR-NEXT: v_mov_b32_e32 v9, 0 1748; GCN-IR-NEXT: v_mov_b32_e32 v10, 0 1749; GCN-IR-NEXT: v_addc_u32_e64 v1, s[4:5], 0, -1, vcc 1750; GCN-IR-NEXT: BB12_3: ; %udiv-do-while 1751; GCN-IR-NEXT: ; =>This Inner Loop Header: Depth=1 1752; GCN-IR-NEXT: v_lshl_b64 v[7:8], v[7:8], 1 1753; GCN-IR-NEXT: v_lshrrev_b32_e32 v4, 31, v3 1754; GCN-IR-NEXT: v_or_b32_e32 v6, v7, v4 1755; GCN-IR-NEXT: v_lshl_b64 v[2:3], v[2:3], 1 1756; GCN-IR-NEXT: v_sub_i32_e32 v4, vcc, 23, v6 1757; GCN-IR-NEXT: v_subb_u32_e32 v4, vcc, 0, v8, vcc 1758; GCN-IR-NEXT: v_or_b32_e32 v2, v9, v2 1759; GCN-IR-NEXT: v_add_i32_e32 v9, vcc, 1, v0 1760; GCN-IR-NEXT: v_ashrrev_i32_e32 v7, 31, v4 1761; GCN-IR-NEXT: v_or_b32_e32 v3, v10, v3 1762; GCN-IR-NEXT: v_addc_u32_e32 v10, vcc, 0, v1, vcc 1763; GCN-IR-NEXT: v_cmp_lt_u64_e32 vcc, v[9:10], v[0:1] 1764; GCN-IR-NEXT: v_and_b32_e32 v4, 1, v7 1765; GCN-IR-NEXT: v_and_b32_e32 v7, 24, v7 1766; GCN-IR-NEXT: v_mov_b32_e32 v0, v9 1767; GCN-IR-NEXT: v_mov_b32_e32 v5, 0 1768; GCN-IR-NEXT: v_sub_i32_e64 v7, s[4:5], v6, v7 1769; GCN-IR-NEXT: v_mov_b32_e32 v1, v10 1770; GCN-IR-NEXT: v_mov_b32_e32 v10, v5 1771; GCN-IR-NEXT: v_subbrev_u32_e64 v8, s[4:5], 0, v8, s[4:5] 1772; GCN-IR-NEXT: s_or_b64 s[10:11], vcc, s[10:11] 1773; GCN-IR-NEXT: v_mov_b32_e32 v9, v4 1774; GCN-IR-NEXT: s_andn2_b64 exec, exec, s[10:11] 1775; GCN-IR-NEXT: s_cbranch_execnz BB12_3 1776; GCN-IR-NEXT: ; %bb.4: ; %Flow 1777; GCN-IR-NEXT: s_or_b64 exec, exec, s[10:11] 1778; GCN-IR-NEXT: BB12_5: ; %Flow3 1779; GCN-IR-NEXT: s_or_b64 exec, exec, s[8:9] 1780; GCN-IR-NEXT: v_lshl_b64 v[0:1], v[2:3], 1 1781; GCN-IR-NEXT: v_or_b32_e32 v2, v5, v1 1782; GCN-IR-NEXT: v_or_b32_e32 v3, v4, v0 1783; GCN-IR-NEXT: BB12_6: ; %Flow4 1784; GCN-IR-NEXT: s_or_b64 exec, exec, s[6:7] 1785; GCN-IR-NEXT: v_mov_b32_e32 v0, v3 1786; GCN-IR-NEXT: v_mov_b32_e32 v1, v2 1787; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1788 %result = udiv i64 %x, 24 1789 ret i64 %result 1790} 1791 1792define amdgpu_kernel void @s_test_udiv24_k_num_i64(i64 addrspace(1)* %out, i64 %x) { 1793; GCN-LABEL: s_test_udiv24_k_num_i64: 1794; GCN: ; %bb.0: 1795; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1796; GCN-NEXT: s_mov_b32 s4, 0x41c00000 1797; GCN-NEXT: s_waitcnt lgkmcnt(0) 1798; GCN-NEXT: s_lshr_b32 s2, s3, 8 1799; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 1800; GCN-NEXT: s_mov_b32 s3, 0xf000 1801; GCN-NEXT: s_mov_b32 s2, -1 1802; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 1803; GCN-NEXT: v_mul_f32_e32 v1, s4, v1 1804; GCN-NEXT: v_trunc_f32_e32 v1, v1 1805; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 1806; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4 1807; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 1808; GCN-NEXT: v_mov_b32_e32 v1, 0 1809; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1810; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1811; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1812; GCN-NEXT: s_endpgm 1813; 1814; GCN-IR-LABEL: s_test_udiv24_k_num_i64: 1815; GCN-IR: ; %bb.0: 1816; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1817; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 1818; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 1819; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8 1820; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 1821; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 1822; GCN-IR-NEXT: s_mov_b32 s2, -1 1823; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 1824; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1 1825; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 1826; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 1827; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4 1828; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 1829; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 1830; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1831; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1832; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 1833; GCN-IR-NEXT: s_endpgm 1834 %x.shr = lshr i64 %x, 40 1835 %result = udiv i64 24, %x.shr 1836 store i64 %result, i64 addrspace(1)* %out 1837 ret void 1838} 1839 1840define amdgpu_kernel void @s_test_udiv24_k_den_i64(i64 addrspace(1)* %out, i64 %x) { 1841; GCN-LABEL: s_test_udiv24_k_den_i64: 1842; GCN: ; %bb.0: 1843; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1844; GCN-NEXT: s_mov_b32 s7, 0xf000 1845; GCN-NEXT: s_mov_b32 s6, -1 1846; GCN-NEXT: s_waitcnt lgkmcnt(0) 1847; GCN-NEXT: s_lshr_b32 s2, s3, 8 1848; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 1849; GCN-NEXT: s_mov_b32 s2, 0x46b6fe00 1850; GCN-NEXT: s_mov_b32 s4, s0 1851; GCN-NEXT: s_mov_b32 s5, s1 1852; GCN-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 1853; GCN-NEXT: v_trunc_f32_e32 v1, v1 1854; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 1855; GCN-NEXT: v_mad_f32 v0, -v1, s2, v0 1856; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2 1857; GCN-NEXT: v_mov_b32_e32 v1, 0 1858; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1859; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1860; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1861; GCN-NEXT: s_endpgm 1862; 1863; GCN-IR-LABEL: s_test_udiv24_k_den_i64: 1864; GCN-IR: ; %bb.0: 1865; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 1866; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 1867; GCN-IR-NEXT: s_mov_b32 s6, -1 1868; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) 1869; GCN-IR-NEXT: s_lshr_b32 s2, s3, 8 1870; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 1871; GCN-IR-NEXT: s_mov_b32 s2, 0x46b6fe00 1872; GCN-IR-NEXT: s_mov_b32 s4, s0 1873; GCN-IR-NEXT: s_mov_b32 s5, s1 1874; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38331158, v0 1875; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 1876; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 1877; GCN-IR-NEXT: v_mad_f32 v0, -v1, s2, v0 1878; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s2 1879; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 1880; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1881; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1882; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 1883; GCN-IR-NEXT: s_endpgm 1884 %x.shr = lshr i64 %x, 40 1885 %result = udiv i64 %x.shr, 23423 1886 store i64 %result, i64 addrspace(1)* %out 1887 ret void 1888} 1889 1890define i64 @v_test_udiv24_k_num_i64(i64 %x) { 1891; GCN-LABEL: v_test_udiv24_k_num_i64: 1892; GCN: ; %bb.0: 1893; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1894; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1 1895; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0 1896; GCN-NEXT: s_mov_b32 s4, 0x41c00000 1897; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 1898; GCN-NEXT: v_mul_f32_e32 v1, s4, v1 1899; GCN-NEXT: v_trunc_f32_e32 v1, v1 1900; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 1901; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4 1902; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 1903; GCN-NEXT: v_mov_b32_e32 v1, 0 1904; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1905; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1906; GCN-NEXT: s_setpc_b64 s[30:31] 1907; 1908; GCN-IR-LABEL: v_test_udiv24_k_num_i64: 1909; GCN-IR: ; %bb.0: 1910; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1911; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 1912; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0 1913; GCN-IR-NEXT: s_mov_b32 s4, 0x41c00000 1914; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 1915; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1 1916; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 1917; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 1918; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4 1919; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 1920; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 1921; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1922; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1923; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1924 %x.shr = lshr i64 %x, 40 1925 %result = udiv i64 24, %x.shr 1926 ret i64 %result 1927} 1928 1929define i64 @v_test_udiv24_pow2_k_num_i64(i64 %x) { 1930; GCN-LABEL: v_test_udiv24_pow2_k_num_i64: 1931; GCN: ; %bb.0: 1932; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1933; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v1 1934; GCN-NEXT: v_cvt_f32_u32_e32 v0, v0 1935; GCN-NEXT: s_mov_b32 s4, 0x47000000 1936; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v0 1937; GCN-NEXT: v_mul_f32_e32 v1, s4, v1 1938; GCN-NEXT: v_trunc_f32_e32 v1, v1 1939; GCN-NEXT: v_cvt_u32_f32_e32 v2, v1 1940; GCN-NEXT: v_mad_f32 v1, -v1, v0, s4 1941; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 1942; GCN-NEXT: v_mov_b32_e32 v1, 0 1943; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1944; GCN-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1945; GCN-NEXT: s_setpc_b64 s[30:31] 1946; 1947; GCN-IR-LABEL: v_test_udiv24_pow2_k_num_i64: 1948; GCN-IR: ; %bb.0: 1949; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1950; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 1951; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0 1952; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 1953; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v1, v0 1954; GCN-IR-NEXT: v_mul_f32_e32 v1, s4, v1 1955; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 1956; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 1957; GCN-IR-NEXT: v_mad_f32 v1, -v1, v0, s4 1958; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 1959; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 1960; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1961; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1962; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1963 %x.shr = lshr i64 %x, 40 1964 %result = udiv i64 32768, %x.shr 1965 ret i64 %result 1966} 1967 1968define i64 @v_test_udiv24_pow2_k_den_i64(i64 %x) { 1969; GCN-LABEL: v_test_udiv24_pow2_k_den_i64: 1970; GCN: ; %bb.0: 1971; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1972; GCN-NEXT: v_lshrrev_b32_e32 v0, 23, v1 1973; GCN-NEXT: v_mov_b32_e32 v1, 0 1974; GCN-NEXT: s_setpc_b64 s[30:31] 1975; 1976; GCN-IR-LABEL: v_test_udiv24_pow2_k_den_i64: 1977; GCN-IR: ; %bb.0: 1978; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) 1979; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v1 1980; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, v0 1981; GCN-IR-NEXT: s_mov_b32 s4, 0x47000000 1982; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x38000000, v0 1983; GCN-IR-NEXT: v_trunc_f32_e32 v1, v1 1984; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v1 1985; GCN-IR-NEXT: v_mad_f32 v0, -v1, s4, v0 1986; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, s4 1987; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 1988; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v2, vcc 1989; GCN-IR-NEXT: v_and_b32_e32 v0, 0xffffff, v0 1990; GCN-IR-NEXT: s_setpc_b64 s[30:31] 1991 %x.shr = lshr i64 %x, 40 1992 %result = udiv i64 %x.shr, 32768 1993 ret i64 %result 1994} 1995