1; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM 2; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM 3; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB 4; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG --check-prefix=ARM-LONG-MACHO 5; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=+long-calls | FileCheck %s --check-prefix=ARM-LONG --check-prefix=ARM-LONG-ELF 6; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=+long-calls | FileCheck %s --check-prefix=THUMB-LONG 7; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -mattr=-fpregs | FileCheck %s --check-prefix=ARM-NOVFP 8; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -mattr=-fpregs | FileCheck %s --check-prefix=ARM-NOVFP 9; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -mattr=-fpregs | FileCheck %s --check-prefix=THUMB-NOVFP 10 11; Note that some of these tests assume that relocations are either 12; movw/movt or constant pool loads. Different platforms will select 13; different approaches. 14 15define i32 @t0(i1 zeroext %a) nounwind { 16 %1 = zext i1 %a to i32 17 ret i32 %1 18} 19 20define i32 @t1(i8 signext %a) nounwind { 21 %1 = sext i8 %a to i32 22 ret i32 %1 23} 24 25define i32 @t2(i8 zeroext %a) nounwind { 26 %1 = zext i8 %a to i32 27 ret i32 %1 28} 29 30define i32 @t3(i16 signext %a) nounwind { 31 %1 = sext i16 %a to i32 32 ret i32 %1 33} 34 35define i32 @t4(i16 zeroext %a) nounwind { 36 %1 = zext i16 %a to i32 37 ret i32 %1 38} 39 40define void @foo(i8 %a, i16 %b) nounwind { 41; ARM-LABEL: foo: 42; THUMB-LABEL: foo: 43;; Materialize i1 1 44; ARM: movw [[REG0:r[0-9]+]], #1 45; THUMB: movs [[REG0:r[0-9]+]], #1 46;; zero-ext 47; ARM: and [[REG1:r[0-9]+]], [[REG0]], #1 48; THUMB: and [[REG1:r[0-9]+]], [[REG0]], #1 49 %1 = call i32 @t0(i1 zeroext 1) 50; ARM: sxtb r0, {{r[0-9]+}} 51; THUMB: sxtb r0, {{r[0-9]+}} 52 %2 = call i32 @t1(i8 signext %a) 53; ARM: and r0, {{r[0-9]+}}, #255 54; THUMB: and r0, {{r[0-9]+}}, #255 55 %3 = call i32 @t2(i8 zeroext %a) 56; ARM: sxth r0, {{r[0-9]+}} 57; THUMB: sxth r0, {{r[0-9]+}} 58 %4 = call i32 @t3(i16 signext %b) 59; ARM: uxth r0, {{r[0-9]+}} 60; THUMB: uxth r0, {{r[0-9]+}} 61 %5 = call i32 @t4(i16 zeroext %b) 62 63;; A few test to check materialization 64;; Note: i1 1 was materialized with t1 call 65; ARM: movw {{r[0-9]+}}, #255 66%6 = call i32 @t2(i8 zeroext 255) 67; ARM: movw {{r[0-9]+}}, #65535 68; THUMB: movw {{r[0-9]+}}, #65535 69%7 = call i32 @t4(i16 zeroext 65535) 70 ret void 71} 72 73define void @foo2() nounwind { 74 %1 = call signext i16 @t5() 75 %2 = call zeroext i16 @t6() 76 %3 = call signext i8 @t7() 77 %4 = call zeroext i8 @t8() 78 %5 = call zeroext i1 @t9() 79 ret void 80} 81 82declare signext i16 @t5(); 83declare zeroext i16 @t6(); 84declare signext i8 @t7(); 85declare zeroext i8 @t8(); 86declare zeroext i1 @t9(); 87 88define i32 @t10() { 89entry: 90; ARM-LABEL: @t10 91; ARM-DAG: movw [[R0:l?r[0-9]*]], #0 92; ARM-DAG: movw [[R1:l?r[0-9]*]], #248 93; ARM-DAG: movw [[R2:l?r[0-9]*]], #187 94; ARM-DAG: movw [[R3:l?r[0-9]*]], #28 95; ARM-DAG: movw [[R4:l?r[0-9]*]], #40 96; ARM-DAG: movw [[R5:l?r[0-9]*]], #186 97; ARM-DAG: and [[R0]], [[R0]], #255 98; ARM-DAG: and [[R1]], [[R1]], #255 99; ARM-DAG: and [[R2]], [[R2]], #255 100; ARM-DAG: and [[R3]], [[R3]], #255 101; ARM-DAG: and [[R4]], [[R4]], #255 102; ARM-DAG: str [[R4]], [sp] 103; ARM-DAG: and [[R5]], [[R5]], #255 104; ARM-DAG: str [[R5]], [sp, #4] 105; ARM: bl {{_?}}bar 106; ARM-LONG-LABEL: @t10 107 108; ARM-LONG-MACHO: {{(movw)|(ldr)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} 109; ARM-LONG-MACHO: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}} 110; ARM-LONG-MACHO: ldr [[R:r[0-9]+]], {{\[}}[[R1]]] 111 112; ARM-LONG-ELF: movw [[R1:r[0-9]*]], :lower16:bar 113; ARM-LONG-ELF: movt [[R1]], :upper16:bar 114; ARM-LONG-ELF: ldr [[R:r[0-9]+]], {{\[}}[[R1]]] 115 116; ARM-LONG: blx [[R]] 117; THUMB-LABEL: @t10 118; THUMB-DAG: movs [[R0:l?r[0-9]*]], #0 119; THUMB-DAG: movs [[R1:l?r[0-9]*]], #248 120; THUMB-DAG: movs [[R2:l?r[0-9]*]], #187 121; THUMB-DAG: movs [[R3:l?r[0-9]*]], #28 122; THUMB-DAG: movw [[R4:l?r[0-9]*]], #40 123; THUMB-DAG: movw [[R5:l?r[0-9]*]], #186 124; THUMB-DAG: and [[R0]], [[R0]], #255 125; THUMB-DAG: and [[R1]], [[R1]], #255 126; THUMB-DAG: and [[R2]], [[R2]], #255 127; THUMB-DAG: and [[R3]], [[R3]], #255 128; THUMB-DAG: and [[R4]], [[R4]], #255 129; THUMB-DAG: str.w [[R4]], [sp] 130; THUMB-DAG: and [[R5]], [[R5]], #255 131; THUMB-DAG: str.w [[R5]], [sp, #4] 132; THUMB: bl {{_?}}bar 133; THUMB-LONG-LABEL: @t10 134; THUMB-LONG: {{(movw)|(ldr.n)}} [[R1:l?r[0-9]*]], {{(:lower16:L_bar\$non_lazy_ptr)|(.LCPI)}} 135; THUMB-LONG: {{(movt [[R1]], :upper16:L_bar\$non_lazy_ptr)?}} 136; THUMB-LONG: ldr{{(.w)?}} [[R:r[0-9]+]], {{\[}}[[R1]]{{\]}} 137; THUMB-LONG: blx [[R]] 138 %call = call i32 @bar(i8 zeroext 0, i8 zeroext -8, i8 zeroext -69, i8 zeroext 28, i8 zeroext 40, i8 zeroext -70) 139 ret i32 0 140} 141 142declare i32 @bar(i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext, i8 zeroext) 143 144define i32 @bar0(i32 %i) nounwind { 145 ret i32 0 146} 147 148define void @foo3() uwtable { 149; ARM-LABEL: @foo3 150; ARM: {{(movw r[0-9]+, :lower16:_?bar0)|(ldr r[0-9]+, .LCPI)}} 151; ARM: {{(movt r[0-9]+, :upper16:_?bar0)|(ldr r[0-9]+, \[r[0-9]+\])}} 152; ARM: movw {{r[0-9]+}}, #0 153; ARM: blx {{r[0-9]+}} 154; THUMB: {{(movw r[0-9]+, :lower16:_?bar0)|(ldr.n r[0-9]+, .LCPI)}} 155; THUMB: {{(movt r[0-9]+, :upper16:_?bar0)|(ldr r[0-9]+, \[r[0-9]+\])}} 156; THUMB: movs {{r[0-9]+}}, #0 157; THUMB: blx {{r[0-9]+}} 158 %fptr = alloca i32 (i32)*, align 8 159 store i32 (i32)* @bar0, i32 (i32)** %fptr, align 8 160 %1 = load i32 (i32)*, i32 (i32)** %fptr, align 8 161 %call = call i32 %1(i32 0) 162 ret void 163} 164 165define i32 @LibCall(i32 %a, i32 %b) { 166entry: 167; ARM-LABEL: LibCall: 168; ARM: bl {{___udivsi3|__aeabi_uidiv}} 169; ARM-LONG-LABEL: LibCall: 170 171; ARM-LONG-MACHO: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}} 172; ARM-LONG-MACHO: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} 173; ARM-LONG-MACHO: ldr r2, [r2] 174 175; ARM-LONG-ELF: movw r2, :lower16:__aeabi_uidiv 176; ARM-LONG-ELF: movt r2, :upper16:__aeabi_uidiv 177 178; ARM-LONG: blx r2 179; THUMB-LABEL: LibCall: 180; THUMB: bl {{___udivsi3|__aeabi_uidiv}} 181; THUMB-LONG-LABEL: LibCall 182; THUMB-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr.n r2, .LCPI)}} 183; THUMB-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} 184; THUMB-LONG: ldr r2, [r2] 185; THUMB-LONG: blx r2 186 %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] 187 ret i32 %tmp1 188} 189 190; Make sure we reuse the original ___udivsi3 rather than creating a new one 191; called ___udivsi3.1 or whatever. 192define i32 @LibCall2(i32 %a, i32 %b) { 193entry: 194; ARM-LABEL: LibCall2: 195; ARM: bl {{___udivsi3|__aeabi_uidiv}} 196; ARM-LONG-LABEL: LibCall2: 197 198; ARM-LONG-MACHO: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr r2, .LCPI)}} 199; ARM-LONG-MACHO: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} 200; ARM-LONG-MACHO: ldr r2, [r2] 201 202; ARM-LONG-ELF: movw r2, :lower16:__aeabi_uidiv 203; ARM-LONG-ELF: movt r2, :upper16:__aeabi_uidiv 204 205; ARM-LONG: blx r2 206; THUMB-LABEL: LibCall2: 207; THUMB: bl {{___udivsi3|__aeabi_uidiv}} 208; THUMB-LONG-LABEL: LibCall2 209; THUMB-LONG: {{(movw r2, :lower16:L___udivsi3\$non_lazy_ptr)|(ldr.n r2, .LCPI)}} 210; THUMB-LONG: {{(movt r2, :upper16:L___udivsi3\$non_lazy_ptr)?}} 211; THUMB-LONG: ldr r2, [r2] 212; THUMB-LONG: blx r2 213 %tmp1 = udiv i32 %a, %b ; <i32> [#uses=1] 214 ret i32 %tmp1 215} 216 217; Test fastcc 218 219define fastcc void @fast_callee(float %i) ssp { 220entry: 221; ARM-LABEL: fast_callee: 222; ARM: vmov r0, s0 223; THUMB-LABEL: fast_callee: 224; THUMB: vmov r0, s0 225; ARM-NOVFP: fast_callee 226; ARM-NOVFP-NOT: s0 227; THUMB-NOVFP: fast_callee 228; THUMB-NOVFP-NOT: s0 229 call void @print(float %i) 230 ret void 231} 232 233define void @fast_caller() ssp { 234entry: 235; ARM-LABEL: fast_caller: 236; ARM: vldr s0, 237; THUMB-LABEL: fast_caller: 238; THUMB: vldr s0, 239; ARM-NOVFP-LABEL: fast_caller: 240; ARM-NOVFP: movw r0, #13107 241; ARM-NOVFP: movt r0, #16611 242; THUMB-NOVFP-LABEL: fast_caller: 243; THUMB-NOVFP: movw r0, #13107 244; THUMB-NOVFP: movt r0, #16611 245 call fastcc void @fast_callee(float 0x401C666660000000) 246 ret void 247} 248 249define void @no_fast_callee(float %i) ssp { 250entry: 251; ARM-LABEL: no_fast_callee: 252; ARM: vmov s0, r0 253; THUMB-LABEL: no_fast_callee: 254; THUMB: vmov s0, r0 255; ARM-NOVFP-LABEL: no_fast_callee: 256; ARM-NOVFP-NOT: s0 257; THUMB-NOVFP-LABEL: no_fast_callee: 258; THUMB-NOVFP-NOT: s0 259 call void @print(float %i) 260 ret void 261} 262 263define void @no_fast_caller() ssp { 264entry: 265; ARM-LABEL: no_fast_caller: 266; ARM: vmov r0, s0 267; THUMB-LABEL: no_fast_caller: 268; THUMB: vmov r0, s0 269; ARM-NOVFP-LABEL: no_fast_caller: 270; ARM-NOVFP: movw r0, #13107 271; ARM-NOVFP: movt r0, #16611 272; THUMB-NOVFP-LABEL: no_fast_caller: 273; THUMB-NOVFP: movw r0, #13107 274; THUMB-NOVFP: movt r0, #16611 275 call void @no_fast_callee(float 0x401C666660000000) 276 ret void 277} 278 279declare void @bar2(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) 280 281define void @call_undef_args() { 282; ARM-LABEL: call_undef_args: 283; ARM: movw r0, #1 284; ARM-NEXT: movw r1, #2 285; ARM-NEXT: movw r2, #3 286; ARM-NEXT: movw r3, #4 287; ARM-NOT: str {{r[0-9]+}}, [sp] 288; ARM: movw [[REG:l?r[0-9]*]], #6 289; ARM-NEXT: str [[REG]], [sp, #4] 290 call void @bar2(i32 1, i32 2, i32 3, i32 4, i32 undef, i32 6) 291 ret void 292} 293 294declare void @print(float) 295