1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc -O3 -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \ 3; RUN: -verify-machineinstrs -mcpu=pwr8 < %s | \ 4; RUN: FileCheck --check-prefix=CHECK-P8 %s 5; RUN: llc -O3 -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \ 6; RUN: -verify-machineinstrs -mcpu=pwr7 < %s | \ 7; RUN: FileCheck --check-prefix=CHECK-P7 %s 8 9define <16 x i8> @rotl_v16i8(<16 x i8> %a) { 10; CHECK-P8-LABEL: rotl_v16i8: 11; CHECK-P8: # %bb.0: # %entry 12; CHECK-P8-NEXT: addis r3, r2, .LCPI0_0@toc@ha 13; CHECK-P8-NEXT: addi r3, r3, .LCPI0_0@toc@l 14; CHECK-P8-NEXT: lvx v3, 0, r3 15; CHECK-P8-NEXT: vrlb v2, v2, v3 16; CHECK-P8-NEXT: blr 17; 18; CHECK-P7-LABEL: rotl_v16i8: 19; CHECK-P7: # %bb.0: # %entry 20; CHECK-P7-NEXT: addis r3, r2, .LCPI0_0@toc@ha 21; CHECK-P7-NEXT: addi r3, r3, .LCPI0_0@toc@l 22; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 23; CHECK-P7-NEXT: vrlb v2, v2, v3 24; CHECK-P7-NEXT: blr 25entry: 26 %b = shl <16 x i8> %a, <i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 7, i8 7, i8 8, i8 8> 27 %c = lshr <16 x i8> %a, <i8 7, i8 7, i8 6, i8 6, i8 5, i8 5, i8 4, i8 4, i8 3, i8 3, i8 2, i8 2, i8 1, i8 1, i8 0, i8 0> 28 %d = or <16 x i8> %b, %c 29 ret <16 x i8> %d 30} 31 32define <8 x i16> @rotl_v8i16(<8 x i16> %a) { 33; CHECK-P8-LABEL: rotl_v8i16: 34; CHECK-P8: # %bb.0: # %entry 35; CHECK-P8-NEXT: addis r3, r2, .LCPI1_0@toc@ha 36; CHECK-P8-NEXT: addi r3, r3, .LCPI1_0@toc@l 37; CHECK-P8-NEXT: lvx v3, 0, r3 38; CHECK-P8-NEXT: vrlh v2, v2, v3 39; CHECK-P8-NEXT: blr 40; 41; CHECK-P7-LABEL: rotl_v8i16: 42; CHECK-P7: # %bb.0: # %entry 43; CHECK-P7-NEXT: addis r3, r2, .LCPI1_0@toc@ha 44; CHECK-P7-NEXT: addi r3, r3, .LCPI1_0@toc@l 45; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 46; CHECK-P7-NEXT: vrlh v2, v2, v3 47; CHECK-P7-NEXT: blr 48entry: 49 %b = shl <8 x i16> %a, <i16 1, i16 2, i16 3, i16 5, i16 7, i16 11, i16 13, i16 16> 50 %c = lshr <8 x i16> %a, <i16 15, i16 14, i16 13, i16 11, i16 9, i16 5, i16 3, i16 0> 51 %d = or <8 x i16> %b, %c 52 ret <8 x i16> %d 53} 54 55define <4 x i32> @rotl_v4i32_0(<4 x i32> %a) { 56; CHECK-P8-LABEL: rotl_v4i32_0: 57; CHECK-P8: # %bb.0: # %entry 58; CHECK-P8-NEXT: addis r3, r2, .LCPI2_0@toc@ha 59; CHECK-P8-NEXT: addi r3, r3, .LCPI2_0@toc@l 60; CHECK-P8-NEXT: lvx v3, 0, r3 61; CHECK-P8-NEXT: vrlw v2, v2, v3 62; CHECK-P8-NEXT: blr 63; 64; CHECK-P7-LABEL: rotl_v4i32_0: 65; CHECK-P7: # %bb.0: # %entry 66; CHECK-P7-NEXT: addis r3, r2, .LCPI2_0@toc@ha 67; CHECK-P7-NEXT: addi r3, r3, .LCPI2_0@toc@l 68; CHECK-P7-NEXT: lxvw4x vs35, 0, r3 69; CHECK-P7-NEXT: vrlw v2, v2, v3 70; CHECK-P7-NEXT: blr 71entry: 72 %b = shl <4 x i32> %a, <i32 29, i32 19, i32 17, i32 11> 73 %c = lshr <4 x i32> %a, <i32 3, i32 13, i32 15, i32 21> 74 %d = or <4 x i32> %b, %c 75 ret <4 x i32> %d 76} 77 78define <4 x i32> @rotl_v4i32_1(<4 x i32> %a) { 79; CHECK-P8-LABEL: rotl_v4i32_1: 80; CHECK-P8: # %bb.0: # %entry 81; CHECK-P8-NEXT: vspltisw v3, -16 82; CHECK-P8-NEXT: vspltisw v4, 7 83; CHECK-P8-NEXT: vsubuwm v3, v4, v3 84; CHECK-P8-NEXT: vrlw v2, v2, v3 85; CHECK-P8-NEXT: blr 86; 87; CHECK-P7-LABEL: rotl_v4i32_1: 88; CHECK-P7: # %bb.0: # %entry 89; CHECK-P7-NEXT: vspltisw v3, -16 90; CHECK-P7-NEXT: vspltisw v4, 7 91; CHECK-P7-NEXT: vsubuwm v3, v4, v3 92; CHECK-P7-NEXT: vrlw v2, v2, v3 93; CHECK-P7-NEXT: blr 94entry: 95 %b = shl <4 x i32> %a, <i32 23, i32 23, i32 23, i32 23> 96 %c = lshr <4 x i32> %a, <i32 9, i32 9, i32 9, i32 9> 97 %d = or <4 x i32> %b, %c 98 ret <4 x i32> %d 99} 100 101define <2 x i64> @rotl_v2i64(<2 x i64> %a) { 102; CHECK-P8-LABEL: rotl_v2i64: 103; CHECK-P8: # %bb.0: # %entry 104; CHECK-P8-NEXT: addis r3, r2, .LCPI4_0@toc@ha 105; CHECK-P8-NEXT: addi r3, r3, .LCPI4_0@toc@l 106; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 107; CHECK-P8-NEXT: xxswapd vs35, vs0 108; CHECK-P8-NEXT: vrld v2, v2, v3 109; CHECK-P8-NEXT: blr 110; 111; CHECK-P7-LABEL: rotl_v2i64: 112; CHECK-P7: # %bb.0: # %entry 113; CHECK-P7-NEXT: addi r3, r1, -48 114; CHECK-P7-NEXT: stxvd2x vs34, 0, r3 115; CHECK-P7-NEXT: ld r3, -40(r1) 116; CHECK-P7-NEXT: sldi r4, r3, 53 117; CHECK-P7-NEXT: rldicl r3, r3, 53, 11 118; CHECK-P7-NEXT: std r4, -8(r1) 119; CHECK-P7-NEXT: ld r4, -48(r1) 120; CHECK-P7-NEXT: sldi r5, r4, 41 121; CHECK-P7-NEXT: rldicl r4, r4, 41, 23 122; CHECK-P7-NEXT: std r5, -16(r1) 123; CHECK-P7-NEXT: addi r5, r1, -16 124; CHECK-P7-NEXT: lxvw4x vs0, 0, r5 125; CHECK-P7-NEXT: std r3, -24(r1) 126; CHECK-P7-NEXT: addi r3, r1, -32 127; CHECK-P7-NEXT: std r4, -32(r1) 128; CHECK-P7-NEXT: lxvw4x vs1, 0, r3 129; CHECK-P7-NEXT: xxlor vs34, vs0, vs1 130; CHECK-P7-NEXT: blr 131entry: 132 %b = shl <2 x i64> %a, <i64 41, i64 53> 133 %c = lshr <2 x i64> %a, <i64 23, i64 11> 134 %d = or <2 x i64> %b, %c 135 ret <2 x i64> %d 136} 137