1; Check that the GHC calling convention works (s390x)
2;
3; RUN: llc -mtriple=s390x-ibm-linux < %s | FileCheck %s
4
5@base  = external dso_local global i64 ; assigned to register: r7
6@sp    = external dso_local global i64 ; assigned to register: r8
7@hp    = external dso_local global i64 ; assigned to register: r10
8@r1    = external dso_local global i64 ; assigned to register: r11
9@r2    = external dso_local global i64 ; assigned to register: r12
10@r3    = external dso_local global i64 ; assigned to register: r13
11@r4    = external dso_local global i64 ; assigned to register: r6
12@r5    = external dso_local global i64 ; assigned to register: r2
13@r6    = external dso_local global i64 ; assigned to register: r3
14@r7    = external dso_local global i64 ; assigned to register: r4
15@r8    = external dso_local global i64 ; assigned to register: r5
16@splim = external dso_local global i64 ; assigned to register: r9
17
18@f1 = external dso_local global float  ; assigned to register: s8
19@f2 = external dso_local global float  ; assigned to register: s9
20@f3 = external dso_local global float  ; assigned to register: s10
21@f4 = external dso_local global float  ; assigned to register: s11
22@f5 = external dso_local global float  ; assigned to register: s0
23@f6 = external dso_local global float  ; assigned to register: s1
24
25@d1 = external dso_local global double ; assigned to register: d12
26@d2 = external dso_local global double ; assigned to register: d13
27@d3 = external dso_local global double ; assigned to register: d14
28@d4 = external dso_local global double ; assigned to register: d15
29@d5 = external dso_local global double ; assigned to register: d2
30@d6 = external dso_local global double ; assigned to register: d3
31
32define ghccc void @foo() nounwind {
33entry:
34  ; CHECK:      larl    {{%r[0-9]+}}, d6
35  ; CHECK-NEXT: ld      %f3, 0({{%r[0-9]+}})
36  ; CHECK-NEXT: larl    {{%r[0-9]+}}, d5
37  ; CHECK-NEXT: ld      %f2, 0({{%r[0-9]+}})
38  ; CHECK-NEXT: larl    {{%r[0-9]+}}, d4
39  ; CHECK-NEXT: ld      %f15, 0({{%r[0-9]+}})
40  ; CHECK-NEXT: larl    {{%r[0-9]+}}, d3
41  ; CHECK-NEXT: ld      %f14, 0({{%r[0-9]+}})
42  ; CHECK-NEXT: larl    {{%r[0-9]+}}, d2
43  ; CHECK-NEXT: ld      %f13, 0({{%r[0-9]+}})
44  ; CHECK-NEXT: larl    {{%r[0-9]+}}, d1
45  ; CHECK-NEXT: ld      %f12, 0({{%r[0-9]+}})
46  ; CHECK-NEXT: larl    {{%r[0-9]+}}, f6
47  ; CHECK-NEXT: le      %f1, 0({{%r[0-9]+}})
48  ; CHECK-NEXT: larl    {{%r[0-9]+}}, f5
49  ; CHECK-NEXT: le      %f0, 0({{%r[0-9]+}})
50  ; CHECK-NEXT: larl    {{%r[0-9]+}}, f4
51  ; CHECK-NEXT: le      %f11, 0({{%r[0-9]+}})
52  ; CHECK-NEXT: larl    {{%r[0-9]+}}, f3
53  ; CHECK-NEXT: le      %f10, 0({{%r[0-9]+}})
54  ; CHECK-NEXT: larl    {{%r[0-9]+}}, f2
55  ; CHECK-NEXT: le      %f9, 0({{%r[0-9]+}})
56  ; CHECK-NEXT: larl    {{%r[0-9]+}}, f1
57  ; CHECK-NEXT: le      %f8, 0({{%r[0-9]+}})
58  ; CHECK-NEXT: lgrl    %r9,  splim
59  ; CHECK-NEXT: lgrl    %r5,  r8
60  ; CHECK-NEXT: lgrl    %r4,  r7
61  ; CHECK-NEXT: lgrl    %r3,  r6
62  ; CHECK-NEXT: lgrl    %r2,  r5
63  ; CHECK-NEXT: lgrl    %r6,  r4
64  ; CHECK-NEXT: lgrl    %r13, r3
65  ; CHECK-NEXT: lgrl    %r12, r2
66  ; CHECK-NEXT: lgrl    %r11, r1
67  ; CHECK-NEXT: lgrl    %r10, hp
68  ; CHECK-NEXT: lgrl    %r8,  sp
69  ; CHECK-NEXT: lgrl    %r7,  base
70  %0  = load double, double* @d6
71  %1  = load double, double* @d5
72  %2  = load double, double* @d4
73  %3  = load double, double* @d3
74  %4  = load double, double* @d2
75  %5  = load double, double* @d1
76  %6  = load float, float* @f6
77  %7  = load float, float* @f5
78  %8  = load float, float* @f4
79  %9  = load float, float* @f3
80  %10 = load float, float* @f2
81  %11 = load float, float* @f1
82  %12 = load i64, i64* @splim
83  %13 = load i64, i64* @r8
84  %14 = load i64, i64* @r7
85  %15 = load i64, i64* @r6
86  %16 = load i64, i64* @r5
87  %17 = load i64, i64* @r4
88  %18 = load i64, i64* @r3
89  %19 = load i64, i64* @r2
90  %20 = load i64, i64* @r1
91  %21 = load i64, i64* @hp
92  %22 = load i64, i64* @sp
93  %23 = load i64, i64* @base
94  ; CHECK: brasl %r14, bar
95  tail call ghccc void @bar(i64 %23, i64 %22, i64 %21, i64 %20, i64 %19, i64 %18, i64 %17, i64 %16, i64 %15, i64 %14, i64 %13, i64 %12,
96                            float %11, float %10, float %9, float %8, float %7, float %6,
97                            double %5, double %4, double %3, double %2, double %1, double %0) nounwind
98  ret void
99}
100
101declare ghccc void @bar(i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64,
102                        float, float, float, float, float, float,
103                        double, double, double, double, double, double)
104