1# Check that the extra operand for the full register added by RegAlloc does
2# not have a latency that interferes with the latency adjustment
3# (ReadAdvance) for the MSY register operand.
4
5# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=machine-scheduler \
6# RUN:  -debug-only=machine-scheduler -o - 2>&1 | FileCheck %s
7# REQUIRES: asserts
8
9# CHECK: ScheduleDAGMI::schedule starting
10# CHECK: SU(4): renamable $r2l = MSR renamable $r2l(tied-def 0), renamable $r2l
11# CHECK:   Latency : 6
12# CHECK: SU(5): renamable $r2l = MSY renamable $r2l(tied-def 0), renamable $r1d, -4, $noreg, implicit $r2d
13# CHECK:   Predecessors:
14# CHECK:     SU(4): Data Latency=2 Reg=$r2l
15# CHECK:     SU(4): Data Latency=0 Reg=$r2d
16
17---
18name:            Perl_do_sv_dump
19alignment:       16
20tracksRegLiveness: true
21body:             |
22    bb.0 :
23    %1:addr64bit = IMPLICIT_DEF
24    %2:addr64bit = IMPLICIT_DEF
25    %3:vr64bit = IMPLICIT_DEF
26
27    bb.1 :
28    %2:addr64bit = ALGFI %2, 4294967291, implicit-def dead $cc
29    %2.subreg_l32:addr64bit = MSR %2.subreg_l32, %2.subreg_l32
30    %2.subreg_l32:addr64bit = MSY %2.subreg_l32, %1, -4, $noreg
31...
32