1; Combined logical operations involving complement on z15
2;
3; RUN: llc -mcpu=z15 < %s -mtriple=s390x-linux-gnu | FileCheck %s
4
5; And-with-complement 32-bit.
6define i32 @f1(i32 %dummy, i32 %a, i32 %b) {
7; CHECK-LABEL: f1:
8; CHECK: ncrk %r2, %r3, %r4
9; CHECK: br %r14
10  %neg = xor i32 %b, -1
11  %ret = and i32 %neg, %a
12  ret i32 %ret
13}
14
15; And-with-complement 64-bit.
16define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
17; CHECK-LABEL: f2:
18; CHECK: ncgrk %r2, %r3, %r4
19; CHECK: br %r14
20  %neg = xor i64 %b, -1
21  %ret = and i64 %neg, %a
22  ret i64 %ret
23}
24
25; Or-with-complement 32-bit.
26define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
27; CHECK-LABEL: f3:
28; CHECK: ocrk %r2, %r3, %r4
29; CHECK: br %r14
30  %neg = xor i32 %b, -1
31  %ret = or i32 %neg, %a
32  ret i32 %ret
33}
34
35; Or-with-complement 64-bit.
36define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
37; CHECK-LABEL: f4:
38; CHECK: ocgrk %r2, %r3, %r4
39; CHECK: br %r14
40  %neg = xor i64 %b, -1
41  %ret = or i64 %neg, %a
42  ret i64 %ret
43}
44
45; NAND 32-bit.
46define i32 @f5(i32 %dummy, i32 %a, i32 %b) {
47; CHECK-LABEL: f5:
48; CHECK: nnrk %r2, %r3, %r4
49; CHECK: br %r14
50  %tmp = and i32 %a, %b
51  %ret = xor i32 %tmp, -1
52  ret i32 %ret
53}
54
55; NAND 64-bit.
56define i64 @f6(i64 %dummy, i64 %a, i64 %b) {
57; CHECK-LABEL: f6:
58; CHECK: nngrk %r2, %r3, %r4
59; CHECK: br %r14
60  %tmp = and i64 %a, %b
61  %ret = xor i64 %tmp, -1
62  ret i64 %ret
63}
64
65; NOR 32-bit.
66define i32 @f7(i32 %dummy, i32 %a, i32 %b) {
67; CHECK-LABEL: f7:
68; CHECK: nork %r2, %r3, %r4
69; CHECK: br %r14
70  %tmp = or i32 %a, %b
71  %ret = xor i32 %tmp, -1
72  ret i32 %ret
73}
74
75; NOR 64-bit.
76define i64 @f8(i64 %dummy, i64 %a, i64 %b) {
77; CHECK-LABEL: f8:
78; CHECK: nogrk %r2, %r3, %r4
79; CHECK: br %r14
80  %tmp = or i64 %a, %b
81  %ret = xor i64 %tmp, -1
82  ret i64 %ret
83}
84
85; NXOR 32-bit.
86define i32 @f9(i32 %dummy, i32 %a, i32 %b) {
87; CHECK-LABEL: f9:
88; CHECK: nxrk %r2, %r3, %r4
89; CHECK: br %r14
90  %tmp = xor i32 %a, %b
91  %ret = xor i32 %tmp, -1
92  ret i32 %ret
93}
94
95; NXOR 64-bit.
96define i64 @f10(i64 %dummy, i64 %a, i64 %b) {
97; CHECK-LABEL: f10:
98; CHECK: nxgrk %r2, %r3, %r4
99; CHECK: br %r14
100  %tmp = xor i64 %a, %b
101  %ret = xor i64 %tmp, -1
102  ret i64 %ret
103}
104
105; Or-with-complement 32-bit of a constant.
106define i32 @f11(i32 %a) {
107; CHECK-LABEL: f11:
108; CHECK: lhi [[REG:%r[0-5]]], -256
109; CHECK: ocrk %r2, [[REG]], %r2
110; CHECK: br %r14
111  %neg = xor i32 %a, -1
112  %ret = or i32 %neg, -256
113  ret i32 %ret
114}
115
116; Or-with-complement 64-bit of a constant.
117define i64 @f12(i64 %a) {
118; CHECK-LABEL: f12:
119; CHECK: lghi [[REG:%r[0-5]]], -256
120; CHECK: ocgrk %r2, [[REG]], %r2
121; CHECK: br %r14
122  %neg = xor i64 %a, -1
123  %ret = or i64 %neg, -256
124  ret i64 %ret
125}
126
127; NXOR 32-bit (alternate match).
128define i32 @f13(i32 %a) {
129; CHECK-LABEL: f13:
130; CHECK: lhi [[REG:%r[0-5]]], -256
131; CHECK: nxrk %r2, %r2, [[REG]]
132; CHECK: br %r14
133  ; Use an opaque const so the pattern doesn't get optimized away early.
134  %const = bitcast i32 -256 to i32
135  %neg = xor i32 %a, -1
136  %ret = xor i32 %neg, %const
137  ret i32 %ret
138}
139
140; NXOR 64-bit (alternate match).
141define i64 @f14(i64 %a) {
142; CHECK-LABEL: f14:
143; CHECK: lghi [[REG:%r[0-5]]], -256
144; CHECK: nxgrk %r2, %r2, [[REG]]
145; CHECK: br %r14
146  ; Use an opaque const so the pattern doesn't get optimized away early.
147  %const = bitcast i64 -256 to i64
148  %neg = xor i64 %a, -1
149  %ret = xor i64 %neg, %const
150  ret i64 %ret
151}
152
153