1# RUN: llc %s -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=postmisched \ 2# RUN: -debug-only=machine-scheduler -o - 2>&1 | FileCheck %s 3# REQUIRES: asserts 4 5# Test that the cycle index is the same before and after scheduling an 6# instruction with 6 decoder slots. 7 8# CHECK: ++ | Current cycle index: 3 9# CHECK-NEXT: ++ | Resource counters: Z13_FXaUnit:2 10# CHECK-NEXT: ** ScheduleDAGMI::schedule picking next node 11# CHECK-NEXT: ** Available: {SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone, SU(6):LARL/FXa} 12# CHECK-NEXT: ** Best so far: SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone Grouping cost:-1 Height:43 13# CHECK-NEXT: ** Tried : SU(6):LARL/FXa Height:14 14# CHECK-NEXT: ** Scheduling SU(3) Grouping cost:-1 15# CHECK-NEXT: ++ HazardRecognizer emitting SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone 16# CHECK-NEXT: ++ Decode group before emission: <empty> 17# CHECK-NEXT: ++ Completed decode group: { SU(3):DL/FXa(4cyc)/LSU/6uops/GroupsAlone } (6 decoder slots) 18# CHECK-NEXT: ++ | Current decoder group: <empty> 19# CHECK-NEXT: ++ | Current cycle index: 3 20 21 22--- | 23 ; ModuleID = '<stdin>' 24 source_filename = "<stdin>" 25 target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64" 26 target triple = "s390x--linux-gnu" 27 28 %0 = type { i8, i8, i8, i8, i16, i32, i32, i32 } 29 30 @TTSize = external dso_local local_unnamed_addr global i32, align 4 31 @AS_TTable = external dso_local local_unnamed_addr global %0*, align 8 32 @Variant = external dso_local local_unnamed_addr global i32, align 4 33 34 define dso_local void @LearnStoreTT(i32 signext %arg, i32 zeroext %arg1, i32 signext %arg2) #0 { 35 bb: 36 %tmp = load i32, i32* @TTSize, align 4 37 %tmp3 = urem i32 %arg1, %tmp 38 %tmp4 = load %0*, %0** @AS_TTable, align 8 39 %tmp5 = zext i32 %tmp3 to i64 40 %tmp6 = load i32, i32* @Variant, align 4 41 %tmp7 = add i32 %tmp6, -3 42 %tmp8 = icmp ugt i32 %tmp7, 1 43 %tmp9 = select i1 %tmp8, i8 3, i8 1 44 store i8 %tmp9, i8* undef, align 1 45 store i32 %arg, i32* undef, align 4 46 %tmp10 = trunc i32 %arg2 to i8 47 store i8 %tmp10, i8* null, align 1 48 %tmp11 = getelementptr inbounds %0, %0* %tmp4, i64 %tmp5, i32 2 49 store i8 0, i8* %tmp11, align 2 50 ret void 51 } 52 53 attributes #0 = { "target-cpu"="z13" } 54 55... 56--- 57name: LearnStoreTT 58alignment: 16 59tracksRegLiveness: true 60liveins: 61 - { reg: '$r2d' } 62 - { reg: '$r3d' } 63 - { reg: '$r4d' } 64frameInfo: 65 maxCallFrameSize: 0 66body: | 67 bb.0.bb: 68 liveins: $r2d, $r3d, $r4d 69 70 $r1d = LGR $r3d, implicit-def $r0q 71 renamable $r3d = LARL @TTSize 72 renamable $r0d = LLILL 0, implicit killed $r0q, implicit-def $r0q 73 renamable $r0q = DL killed renamable $r0q, killed renamable $r3d, 0, $noreg :: (dereferenceable load (s32) from @TTSize) 74 renamable $r3d = LGRL @AS_TTable :: (dereferenceable load (s64) from @AS_TTable) 75 renamable $r1d = LLGFR renamable $r0l, implicit killed $r0q 76 renamable $r5d = LARL @Variant 77 renamable $r0l = LHI -3 78 renamable $r0l = A killed renamable $r0l, killed renamable $r5d, 0, $noreg, implicit-def dead $cc :: (dereferenceable load (s32) from @Variant) 79 CLFI killed renamable $r0l, 1, implicit-def $cc 80 renamable $r0l = LHI 1 81 renamable $r0l = LOCHI killed renamable $r0l, 3, 14, 2, implicit killed $cc 82 STC killed renamable $r0l, undef renamable $r1d, 0, $noreg :: (store (s8) into `i8* undef`) 83 ST renamable $r2l, undef renamable $r1d, 0, $noreg, implicit killed $r2d :: (store (s32) into `i32* undef`) 84 STC renamable $r4l, $noreg, 0, $noreg, implicit killed $r4d :: (store (s8) into `i8* null`) 85 renamable $r1d = MGHI killed renamable $r1d, 20 86 renamable $r0l = LHI 0 87 STC killed renamable $r0l, killed renamable $r3d, 2, killed renamable $r1d :: (store (s8) into %ir.tmp11, align 2) 88 Return 89 90... 91