1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; Test sequences that can use RISBG with a zeroed first operand. 3; The tests here assume that RISBLG isn't available. 4; 5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z10 | FileCheck %s 6 7; Test an extraction of bit 0 from a right-shifted value. 8define i32 @f1(i32 %foo) { 9; CHECK-LABEL: f1: 10; CHECK: # %bb.0: 11; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 12; CHECK-NEXT: risbg %r2, %r2, 63, 191, 54 13; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 14; CHECK-NEXT: br %r14 15 %shr = lshr i32 %foo, 10 16 %and = and i32 %shr, 1 17 ret i32 %and 18} 19 20; ...and again with i64. 21define i64 @f2(i64 %foo) { 22; CHECK-LABEL: f2: 23; CHECK: # %bb.0: 24; CHECK-NEXT: risbg %r2, %r2, 63, 191, 54 25; CHECK-NEXT: br %r14 26 %shr = lshr i64 %foo, 10 27 %and = and i64 %shr, 1 28 ret i64 %and 29} 30 31; Test an extraction of other bits from a right-shifted value. 32define i32 @f3(i32 %foo) { 33; CHECK-LABEL: f3: 34; CHECK: # %bb.0: 35; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 36; CHECK-NEXT: risbg %r2, %r2, 60, 189, 42 37; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 38; CHECK-NEXT: br %r14 39 %shr = lshr i32 %foo, 22 40 %and = and i32 %shr, 12 41 ret i32 %and 42} 43 44; ...and again with i64. 45define i64 @f4(i64 %foo) { 46; CHECK-LABEL: f4: 47; CHECK: # %bb.0: 48; CHECK-NEXT: risbg %r2, %r2, 60, 189, 42 49; CHECK-NEXT: br %r14 50 %shr = lshr i64 %foo, 22 51 %and = and i64 %shr, 12 52 ret i64 %and 53} 54 55; Test an extraction of most bits from a right-shifted value. 56; The range should be reduced to exclude the zeroed high bits. 57define i32 @f5(i32 %foo) { 58; CHECK-LABEL: f5: 59; CHECK: # %bb.0: 60; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 61; CHECK-NEXT: risbg %r2, %r2, 34, 188, 62 62; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 63; CHECK-NEXT: br %r14 64 %shr = lshr i32 %foo, 2 65 %and = and i32 %shr, -8 66 ret i32 %and 67} 68 69; ...and again with i64. 70define i64 @f6(i64 %foo) { 71; CHECK-LABEL: f6: 72; CHECK: # %bb.0: 73; CHECK-NEXT: risbg %r2, %r2, 2, 188, 62 74; CHECK-NEXT: br %r14 75 %shr = lshr i64 %foo, 2 76 %and = and i64 %shr, -8 77 ret i64 %and 78} 79 80; Try the next value up (mask ....1111001). This needs a separate shift 81; and mask. 82define i32 @f7(i32 %foo) { 83; CHECK-LABEL: f7: 84; CHECK: # %bb.0: 85; CHECK-NEXT: srl %r2, 2 86; CHECK-NEXT: nill %r2, 65529 87; CHECK-NEXT: br %r14 88 %shr = lshr i32 %foo, 2 89 %and = and i32 %shr, -7 90 ret i32 %and 91} 92 93; ...and again with i64. 94define i64 @f8(i64 %foo) { 95; CHECK-LABEL: f8: 96; CHECK: # %bb.0: 97; CHECK-NEXT: srlg %r2, %r2, 2 98; CHECK-NEXT: nill %r2, 65529 99; CHECK-NEXT: br %r14 100 %shr = lshr i64 %foo, 2 101 %and = and i64 %shr, -7 102 ret i64 %and 103} 104 105; Test an extraction of bits from a left-shifted value. The range should 106; be reduced to exclude the zeroed low bits. 107define i32 @f9(i32 %foo) { 108; CHECK-LABEL: f9: 109; CHECK: # %bb.0: 110; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 111; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2 112; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 113; CHECK-NEXT: br %r14 114 %shr = shl i32 %foo, 2 115 %and = and i32 %shr, 255 116 ret i32 %and 117} 118 119; ...and again with i64. 120define i64 @f10(i64 %foo) { 121; CHECK-LABEL: f10: 122; CHECK: # %bb.0: 123; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2 124; CHECK-NEXT: br %r14 125 %shr = shl i64 %foo, 2 126 %and = and i64 %shr, 255 127 ret i64 %and 128} 129 130; Try a wrap-around mask (mask ....111100001111). This needs a separate shift 131; and mask. 132define i32 @f11(i32 %foo) { 133; CHECK-LABEL: f11: 134; CHECK: # %bb.0: 135; CHECK-NEXT: sll %r2, 2 136; CHECK-NEXT: nill %r2, 65295 137; CHECK-NEXT: br %r14 138 %shr = shl i32 %foo, 2 139 %and = and i32 %shr, -241 140 ret i32 %and 141} 142 143; ...and again with i64. 144define i64 @f12(i64 %foo) { 145; CHECK-LABEL: f12: 146; CHECK: # %bb.0: 147; CHECK-NEXT: sllg %r2, %r2, 2 148; CHECK-NEXT: nill %r2, 65295 149; CHECK-NEXT: br %r14 150 %shr = shl i64 %foo, 2 151 %and = and i64 %shr, -241 152 ret i64 %and 153} 154 155; Test an extraction from a rotated value, no mask wraparound. 156; This is equivalent to the lshr case, because the bits from the 157; shl are not used. 158define i32 @f13(i32 %foo) { 159; CHECK-LABEL: f13: 160; CHECK: # %bb.0: 161; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 162; CHECK-NEXT: risbg %r2, %r2, 56, 188, 46 163; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 164; CHECK-NEXT: br %r14 165 %parta = shl i32 %foo, 14 166 %partb = lshr i32 %foo, 18 167 %rotl = or i32 %parta, %partb 168 %and = and i32 %rotl, 248 169 ret i32 %and 170} 171 172; ...and again with i64. 173define i64 @f14(i64 %foo) { 174; CHECK-LABEL: f14: 175; CHECK: # %bb.0: 176; CHECK-NEXT: risbg %r2, %r2, 56, 188, 14 177; CHECK-NEXT: br %r14 178 %parta = shl i64 %foo, 14 179 %partb = lshr i64 %foo, 50 180 %rotl = or i64 %parta, %partb 181 %and = and i64 %rotl, 248 182 ret i64 %and 183} 184 185; Try a case in which only the bits from the shl are used. 186define i32 @f15(i32 %foo) { 187; CHECK-LABEL: f15: 188; CHECK: # %bb.0: 189; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 190; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14 191; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 192; CHECK-NEXT: br %r14 193 %parta = shl i32 %foo, 14 194 %partb = lshr i32 %foo, 18 195 %rotl = or i32 %parta, %partb 196 %and = and i32 %rotl, 114688 197 ret i32 %and 198} 199 200; ...and again with i64. 201define i64 @f16(i64 %foo) { 202; CHECK-LABEL: f16: 203; CHECK: # %bb.0: 204; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14 205; CHECK-NEXT: br %r14 206 %parta = shl i64 %foo, 14 207 %partb = lshr i64 %foo, 50 208 %rotl = or i64 %parta, %partb 209 %and = and i64 %rotl, 114688 210 ret i64 %and 211} 212 213; Test a 32-bit rotate in which both parts of the OR are needed. 214; This needs a separate shift and mask. 215define i32 @f17(i32 %foo) { 216; CHECK-LABEL: f17: 217; CHECK: # %bb.0: 218; CHECK-NEXT: rll %r2, %r2, 4 219; CHECK-NEXT: nilf %r2, 126 220; CHECK-NEXT: br %r14 221 %parta = shl i32 %foo, 4 222 %partb = lshr i32 %foo, 28 223 %rotl = or i32 %parta, %partb 224 %and = and i32 %rotl, 126 225 ret i32 %and 226} 227 228; ...and for i64, where RISBG should do the rotate too. 229define i64 @f18(i64 %foo) { 230; CHECK-LABEL: f18: 231; CHECK: # %bb.0: 232; CHECK-NEXT: risbg %r2, %r2, 57, 190, 4 233; CHECK-NEXT: br %r14 234 %parta = shl i64 %foo, 4 235 %partb = lshr i64 %foo, 60 236 %rotl = or i64 %parta, %partb 237 %and = and i64 %rotl, 126 238 ret i64 %and 239} 240 241; Test an arithmetic shift right in which some of the sign bits are kept. 242; This needs a separate shift and mask. 243define i32 @f19(i32 %foo) { 244; CHECK-LABEL: f19: 245; CHECK: # %bb.0: 246; CHECK-NEXT: sra %r2, 28 247; CHECK-NEXT: nilf %r2, 30 248; CHECK-NEXT: br %r14 249 %shr = ashr i32 %foo, 28 250 %and = and i32 %shr, 30 251 ret i32 %and 252} 253 254; ...and again with i64. In this case RISBG is the best way of doing the AND. 255define i64 @f20(i64 %foo) { 256; CHECK-LABEL: f20: 257; CHECK: # %bb.0: 258; CHECK-NEXT: srag %r0, %r2, 60 259; CHECK-NEXT: risbg %r2, %r0, 59, 190, 0 260; CHECK-NEXT: br %r14 261 %shr = ashr i64 %foo, 60 262 %and = and i64 %shr, 30 263 ret i64 %and 264} 265 266; Now try an arithmetic right shift in which the sign bits aren't needed. 267; Introduce a second use of %shr so that the ashr doesn't decompose to 268; an lshr. 269; NOTE: the extra move to %r2 should not be needed (temporary FAIL) 270define i32 @f21(i32 %foo, i32 *%dest) { 271; CHECK-LABEL: f21: 272; CHECK: # %bb.0: 273; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 274; CHECK-NEXT: risbg %r0, %r2, 60, 190, 36 275; CHECK-NEXT: lr %r1, %r2 276; CHECK-NEXT: sra %r1, 28 277; CHECK-NEXT: st %r1, 0(%r3) 278; CHECK-NEXT: lr %r2, %r0 279; CHECK-NEXT: br %r14 280 %shr = ashr i32 %foo, 28 281 store i32 %shr, i32 *%dest 282 %and = and i32 %shr, 14 283 ret i32 %and 284} 285 286; ...and again with i64. 287define i64 @f22(i64 %foo, i64 *%dest) { 288; CHECK-LABEL: f22: 289; CHECK: # %bb.0: 290; CHECK-NEXT: srag %r0, %r2, 60 291; CHECK-NEXT: risbg %r2, %r2, 60, 190, 4 292; CHECK-NEXT: stg %r0, 0(%r3) 293; CHECK-NEXT: br %r14 294 %shr = ashr i64 %foo, 60 295 store i64 %shr, i64 *%dest 296 %and = and i64 %shr, 14 297 ret i64 %and 298} 299 300; Check that we use RISBG for shifted values even if the AND is a 301; natural zero extension. 302define i64 @f23(i64 %foo) { 303; CHECK-LABEL: f23: 304; CHECK: # %bb.0: 305; CHECK-NEXT: risbg %r2, %r2, 56, 191, 62 306; CHECK-NEXT: br %r14 307 %shr = lshr i64 %foo, 2 308 %and = and i64 %shr, 255 309 ret i64 %and 310} 311 312; Test a case where the AND comes before a rotate. This needs a separate 313; mask and rotate. 314define i32 @f24(i32 %foo) { 315; CHECK-LABEL: f24: 316; CHECK: # %bb.0: 317; CHECK-NEXT: nilf %r2, 254 318; CHECK-NEXT: rll %r2, %r2, 29 319; CHECK-NEXT: br %r14 320 %and = and i32 %foo, 254 321 %parta = lshr i32 %and, 3 322 %partb = shl i32 %and, 29 323 %rotl = or i32 %parta, %partb 324 ret i32 %rotl 325} 326 327; ...and again with i64, where a single RISBG is enough. 328define i64 @f25(i64 %foo) { 329; CHECK-LABEL: f25: 330; CHECK: # %bb.0: 331; CHECK-NEXT: risbg %r2, %r2, 57, 187, 3 332; CHECK-NEXT: br %r14 333 %and = and i64 %foo, 14 334 %parta = shl i64 %and, 3 335 %partb = lshr i64 %and, 61 336 %rotl = or i64 %parta, %partb 337 ret i64 %rotl 338} 339 340; Test a wrap-around case in which the AND comes before a rotate. 341; This again needs a separate mask and rotate. 342define i32 @f26(i32 %foo) { 343; CHECK-LABEL: f26: 344; CHECK: # %bb.0: 345; CHECK-NEXT: nill %r2, 65487 346; CHECK-NEXT: rll %r2, %r2, 5 347; CHECK-NEXT: br %r14 348 %and = and i32 %foo, -49 349 %parta = shl i32 %and, 5 350 %partb = lshr i32 %and, 27 351 %rotl = or i32 %parta, %partb 352 ret i32 %rotl 353} 354 355; ...and again with i64, where a single RISBG is OK. 356define i64 @f27(i64 %foo) { 357; CHECK-LABEL: f27: 358; CHECK: # %bb.0: 359; CHECK-NEXT: risbg %r2, %r2, 55, 180, 5 360; CHECK-NEXT: br %r14 361 %and = and i64 %foo, -49 362 %parta = shl i64 %and, 5 363 %partb = lshr i64 %and, 59 364 %rotl = or i64 %parta, %partb 365 ret i64 %rotl 366} 367 368; Test a case where the AND comes before a shift left. 369define i32 @f28(i32 %foo) { 370; CHECK-LABEL: f28: 371; CHECK: # %bb.0: 372; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 373; CHECK-NEXT: risbg %r2, %r2, 32, 173, 17 374; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 375; CHECK-NEXT: br %r14 376 %and = and i32 %foo, 32766 377 %shl = shl i32 %and, 17 378 ret i32 %shl 379} 380 381; ...and again with i64. 382define i64 @f29(i64 %foo) { 383; CHECK-LABEL: f29: 384; CHECK: # %bb.0: 385; CHECK-NEXT: risbg %r2, %r2, 0, 141, 49 386; CHECK-NEXT: br %r14 387 %and = and i64 %foo, 32766 388 %shl = shl i64 %and, 49 389 ret i64 %shl 390} 391 392; Test the next shift up from f28, in which the mask should get shortened. 393define i32 @f30(i32 %foo) { 394; CHECK-LABEL: f30: 395; CHECK: # %bb.0: 396; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 397; CHECK-NEXT: risbg %r2, %r2, 32, 172, 18 398; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 399; CHECK-NEXT: br %r14 400 %and = and i32 %foo, 32766 401 %shl = shl i32 %and, 18 402 ret i32 %shl 403} 404 405; ...and again with i64. 406define i64 @f31(i64 %foo) { 407; CHECK-LABEL: f31: 408; CHECK: # %bb.0: 409; CHECK-NEXT: risbg %r2, %r2, 0, 140, 50 410; CHECK-NEXT: br %r14 411 %and = and i64 %foo, 32766 412 %shl = shl i64 %and, 50 413 ret i64 %shl 414} 415 416; Test a wrap-around case in which the shift left comes after the AND. 417; We can't use RISBG for the shift in that case. 418define i32 @f32(i32 %foo) { 419; CHECK-LABEL: f32: 420; CHECK: # %bb.0: 421; CHECK-NEXT: nilf %r2, 4194297 422; CHECK-NEXT: sll %r2, 10 423; CHECK-NEXT: br %r14 424 %and = and i32 %foo, -7 425 %shl = shl i32 %and, 10 426 ret i32 %shl 427} 428 429; ...and again with i64. 430define i64 @f33(i64 %foo) { 431; CHECK-LABEL: f33: 432; CHECK: # %bb.0: 433; CHECK-NEXT: llihf %r0, 4194303 434; CHECK-NEXT: oilf %r0, 4294967289 435; CHECK-NEXT: ngr %r0, %r2 436; CHECK-NEXT: sllg %r2, %r0, 10 437; CHECK-NEXT: br %r14 438 %and = and i64 %foo, -7 439 %shl = shl i64 %and, 10 440 ret i64 %shl 441} 442 443; Test a case where the AND comes before a shift right. 444define i32 @f34(i32 %foo) { 445; CHECK-LABEL: f34: 446; CHECK: # %bb.0: 447; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 448; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55 449; CHECK-NEXT: # kill: def $r2l killed $r2l killed $r2d 450; CHECK-NEXT: br %r14 451 %and = and i32 %foo, 65535 452 %shl = lshr i32 %and, 9 453 ret i32 %shl 454} 455 456; ...and again with i64. 457define i64 @f35(i64 %foo) { 458; CHECK-LABEL: f35: 459; CHECK: # %bb.0: 460; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55 461; CHECK-NEXT: br %r14 462 %and = and i64 %foo, 65535 463 %shl = lshr i64 %and, 9 464 ret i64 %shl 465} 466 467; Test a wrap-around case where the AND comes before a shift right. 468; We can't use RISBG for the shift in that case. 469define i32 @f36(i32 %foo) { 470; CHECK-LABEL: f36: 471; CHECK: # %bb.0: 472; CHECK-NEXT: nill %r2, 65510 473; CHECK-NEXT: srl %r2, 1 474; CHECK-NEXT: br %r14 475 %and = and i32 %foo, -25 476 %shl = lshr i32 %and, 1 477 ret i32 %shl 478} 479 480; ...and again with i64. 481define i64 @f37(i64 %foo) { 482; CHECK-LABEL: f37: 483; CHECK: # %bb.0: 484; CHECK-NEXT: nill %r2, 65510 485; CHECK-NEXT: srlg %r2, %r2, 1 486; CHECK-NEXT: br %r14 487 %and = and i64 %foo, -25 488 %shl = lshr i64 %and, 1 489 ret i64 %shl 490} 491 492; Test a combination involving a large ASHR and a shift left. We can't 493; use RISBG there. 494define i64 @f38(i64 %foo) { 495; CHECK-LABEL: f38: 496; CHECK: # %bb.0: 497; CHECK-NEXT: srag %r0, %r2, 32 498; CHECK-NEXT: sllg %r2, %r0, 5 499; CHECK-NEXT: br %r14 500 %ashr = ashr i64 %foo, 32 501 %shl = shl i64 %ashr, 5 502 ret i64 %shl 503} 504 505; Try a similar thing in which no shifted sign bits are kept. 506define i64 @f39(i64 %foo, i64 *%dest) { 507; CHECK-LABEL: f39: 508; CHECK: # %bb.0: 509; CHECK-NEXT: srag %r0, %r2, 35 510; CHECK-NEXT: risbg %r2, %r2, 33, 189, 31 511; CHECK-NEXT: stg %r0, 0(%r3) 512; CHECK-NEXT: br %r14 513 %ashr = ashr i64 %foo, 35 514 store i64 %ashr, i64 *%dest 515 %shl = shl i64 %ashr, 2 516 %and = and i64 %shl, 2147483647 517 ret i64 %and 518} 519 520; ...and again with the next highest shift value, where one sign bit is kept. 521define i64 @f40(i64 %foo, i64 *%dest) { 522; CHECK-LABEL: f40: 523; CHECK: # %bb.0: 524; CHECK-NEXT: srag %r0, %r2, 36 525; CHECK-NEXT: risbg %r2, %r0, 33, 189, 2 526; CHECK-NEXT: stg %r0, 0(%r3) 527; CHECK-NEXT: br %r14 528 %ashr = ashr i64 %foo, 36 529 store i64 %ashr, i64 *%dest 530 %shl = shl i64 %ashr, 2 531 %and = and i64 %shl, 2147483647 532 ret i64 %and 533} 534 535; Check a case where the result is zero-extended. 536define i64 @f41(i32 %a) { 537; CHECK-LABEL: f41: 538; CHECK: # %bb.0: 539; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 540; CHECK-NEXT: risbg %r2, %r2, 36, 191, 62 541; CHECK-NEXT: br %r14 542 %shl = shl i32 %a, 2 543 %shr = lshr i32 %shl, 4 544 %ext = zext i32 %shr to i64 545 ret i64 %ext 546} 547 548; In this case the sign extension is converted to a pair of 32-bit shifts, 549; which is then extended to 64 bits. We previously used the wrong bit size 550; when testing whether the shifted-in bits of the shift right were significant. 551define i64 @f42(i1 %x) { 552; CHECK-LABEL: f42: 553; CHECK: # %bb.0: 554; CHECK-NEXT: nilf %r2, 1 555; CHECK-NEXT: lcr %r0, %r2 556; CHECK-NEXT: llgcr %r2, %r0 557; CHECK-NEXT: br %r14 558 %ext = sext i1 %x to i8 559 %ext2 = zext i8 %ext to i64 560 ret i64 %ext2 561} 562 563; Check that we get the case where a 64-bit shift is used by a 32-bit and. 564define signext i32 @f43(i64 %x) { 565; CHECK-LABEL: f43: 566; CHECK: # %bb.0: 567; CHECK-NEXT: risbg %r0, %r2, 32, 189, 52 568; CHECK-NEXT: lgfr %r2, %r0 569; CHECK-NEXT: br %r14 570 %shr3 = lshr i64 %x, 12 571 %shr3.tr = trunc i64 %shr3 to i32 572 %conv = and i32 %shr3.tr, -4 573 ret i32 %conv 574} 575 576; Check that we don't get the case where the 32-bit and mask is not contiguous 577define signext i32 @f44(i64 %x) { 578; CHECK-LABEL: f44: 579; CHECK: # %bb.0: 580; CHECK-NEXT: srlg %r0, %r2, 12 581; CHECK-NEXT: lghi %r2, 10 582; CHECK-NEXT: ngr %r2, %r0 583; CHECK-NEXT: br %r14 584 %shr4 = lshr i64 %x, 12 585 %conv = trunc i64 %shr4 to i32 586 %and = and i32 %conv, 10 587 ret i32 %and 588} 589