1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; Test sequences that can use RISBG with a zeroed first operand. 3; The tests here assume that RISBLG is available. 4; 5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z196 | FileCheck %s 6 7; Test an extraction of bit 0 from a right-shifted value. 8define i32 @f1(i32 %foo) { 9; CHECK-LABEL: f1: 10; CHECK: # %bb.0: 11; CHECK-NEXT: risblg %r2, %r2, 31, 159, 54 12; CHECK-NEXT: br %r14 13 %shr = lshr i32 %foo, 10 14 %and = and i32 %shr, 1 15 ret i32 %and 16} 17 18; ...and again with i64. 19define i64 @f2(i64 %foo) { 20; CHECK-LABEL: f2: 21; CHECK: # %bb.0: 22; CHECK-NEXT: risbg %r2, %r2, 63, 191, 54 23; CHECK-NEXT: br %r14 24 %shr = lshr i64 %foo, 10 25 %and = and i64 %shr, 1 26 ret i64 %and 27} 28 29; Test an extraction of other bits from a right-shifted value. 30define i32 @f3(i32 %foo) { 31; CHECK-LABEL: f3: 32; CHECK: # %bb.0: 33; CHECK-NEXT: risblg %r2, %r2, 28, 157, 42 34; CHECK-NEXT: br %r14 35 %shr = lshr i32 %foo, 22 36 %and = and i32 %shr, 12 37 ret i32 %and 38} 39 40; ...and again with i64. 41define i64 @f4(i64 %foo) { 42; CHECK-LABEL: f4: 43; CHECK: # %bb.0: 44; CHECK-NEXT: risbg %r2, %r2, 60, 189, 42 45; CHECK-NEXT: br %r14 46 %shr = lshr i64 %foo, 22 47 %and = and i64 %shr, 12 48 ret i64 %and 49} 50 51; Test an extraction of most bits from a right-shifted value. 52; The range should be reduced to exclude the zeroed high bits. 53define i32 @f5(i32 %foo) { 54; CHECK-LABEL: f5: 55; CHECK: # %bb.0: 56; CHECK-NEXT: risblg %r2, %r2, 2, 156, 62 57; CHECK-NEXT: br %r14 58 %shr = lshr i32 %foo, 2 59 %and = and i32 %shr, -8 60 ret i32 %and 61} 62 63; ...and again with i64. 64define i64 @f6(i64 %foo) { 65; CHECK-LABEL: f6: 66; CHECK: # %bb.0: 67; CHECK-NEXT: risbg %r2, %r2, 2, 188, 62 68; CHECK-NEXT: br %r14 69 %shr = lshr i64 %foo, 2 70 %and = and i64 %shr, -8 71 ret i64 %and 72} 73 74; Try the next value up (mask ....1111001). This needs a separate shift 75; and mask. 76define i32 @f7(i32 %foo) { 77; CHECK-LABEL: f7: 78; CHECK: # %bb.0: 79; CHECK-NEXT: srl %r2, 2 80; CHECK-NEXT: nill %r2, 65529 81; CHECK-NEXT: br %r14 82 %shr = lshr i32 %foo, 2 83 %and = and i32 %shr, -7 84 ret i32 %and 85} 86 87; ...and again with i64. 88define i64 @f8(i64 %foo) { 89; CHECK-LABEL: f8: 90; CHECK: # %bb.0: 91; CHECK-NEXT: srlg %r2, %r2, 2 92; CHECK-NEXT: nill %r2, 65529 93; CHECK-NEXT: br %r14 94 %shr = lshr i64 %foo, 2 95 %and = and i64 %shr, -7 96 ret i64 %and 97} 98 99; Test an extraction of bits from a left-shifted value. The range should 100; be reduced to exclude the zeroed low bits. 101define i32 @f9(i32 %foo) { 102; CHECK-LABEL: f9: 103; CHECK: # %bb.0: 104; CHECK-NEXT: risblg %r2, %r2, 24, 157, 2 105; CHECK-NEXT: br %r14 106 %shr = shl i32 %foo, 2 107 %and = and i32 %shr, 255 108 ret i32 %and 109} 110 111; ...and again with i64. 112define i64 @f10(i64 %foo) { 113; CHECK-LABEL: f10: 114; CHECK: # %bb.0: 115; CHECK-NEXT: risbg %r2, %r2, 56, 189, 2 116; CHECK-NEXT: br %r14 117 %shr = shl i64 %foo, 2 118 %and = and i64 %shr, 255 119 ret i64 %and 120} 121 122; Try a wrap-around mask (mask ....111100001111). This needs a separate shift 123; and mask. 124define i32 @f11(i32 %foo) { 125; CHECK-LABEL: f11: 126; CHECK: # %bb.0: 127; CHECK-NEXT: sll %r2, 2 128; CHECK-NEXT: nill %r2, 65295 129; CHECK-NEXT: br %r14 130 %shr = shl i32 %foo, 2 131 %and = and i32 %shr, -241 132 ret i32 %and 133} 134 135; ...and again with i64. 136define i64 @f12(i64 %foo) { 137; CHECK-LABEL: f12: 138; CHECK: # %bb.0: 139; CHECK-NEXT: sllg %r2, %r2, 2 140; CHECK-NEXT: nill %r2, 65295 141; CHECK-NEXT: br %r14 142 %shr = shl i64 %foo, 2 143 %and = and i64 %shr, -241 144 ret i64 %and 145} 146 147; Test an extraction from a rotated value, no mask wraparound. 148; This is equivalent to the lshr case, because the bits from the 149; shl are not used. 150define i32 @f13(i32 %foo) { 151; CHECK-LABEL: f13: 152; CHECK: # %bb.0: 153; CHECK-NEXT: risblg %r2, %r2, 24, 156, 46 154; CHECK-NEXT: br %r14 155 %parta = shl i32 %foo, 14 156 %partb = lshr i32 %foo, 18 157 %rotl = or i32 %parta, %partb 158 %and = and i32 %rotl, 248 159 ret i32 %and 160} 161 162; ...and again with i64. 163define i64 @f14(i64 %foo) { 164; CHECK-LABEL: f14: 165; CHECK: # %bb.0: 166; CHECK-NEXT: risbg %r2, %r2, 56, 188, 14 167; CHECK-NEXT: br %r14 168 %parta = shl i64 %foo, 14 169 %partb = lshr i64 %foo, 50 170 %rotl = or i64 %parta, %partb 171 %and = and i64 %rotl, 248 172 ret i64 %and 173} 174 175; Try a case in which only the bits from the shl are used. 176define i32 @f15(i32 %foo) { 177; CHECK-LABEL: f15: 178; CHECK: # %bb.0: 179; CHECK-NEXT: risblg %r2, %r2, 15, 145, 14 180; CHECK-NEXT: br %r14 181 %parta = shl i32 %foo, 14 182 %partb = lshr i32 %foo, 18 183 %rotl = or i32 %parta, %partb 184 %and = and i32 %rotl, 114688 185 ret i32 %and 186} 187 188; ...and again with i64. 189define i64 @f16(i64 %foo) { 190; CHECK-LABEL: f16: 191; CHECK: # %bb.0: 192; CHECK-NEXT: risbg %r2, %r2, 47, 177, 14 193; CHECK-NEXT: br %r14 194 %parta = shl i64 %foo, 14 195 %partb = lshr i64 %foo, 50 196 %rotl = or i64 %parta, %partb 197 %and = and i64 %rotl, 114688 198 ret i64 %and 199} 200 201; Test a 32-bit rotate in which both parts of the OR are needed. 202; This needs a separate shift and mask. 203define i32 @f17(i32 %foo) { 204; CHECK-LABEL: f17: 205; CHECK: # %bb.0: 206; CHECK-NEXT: rll %r2, %r2, 4 207; CHECK-NEXT: nilf %r2, 126 208; CHECK-NEXT: br %r14 209 %parta = shl i32 %foo, 4 210 %partb = lshr i32 %foo, 28 211 %rotl = or i32 %parta, %partb 212 %and = and i32 %rotl, 126 213 ret i32 %and 214} 215 216; ...and for i64, where RISBG should do the rotate too. 217define i64 @f18(i64 %foo) { 218; CHECK-LABEL: f18: 219; CHECK: # %bb.0: 220; CHECK-NEXT: risbg %r2, %r2, 57, 190, 4 221; CHECK-NEXT: br %r14 222 %parta = shl i64 %foo, 4 223 %partb = lshr i64 %foo, 60 224 %rotl = or i64 %parta, %partb 225 %and = and i64 %rotl, 126 226 ret i64 %and 227} 228 229; Test an arithmetic shift right in which some of the sign bits are kept. 230; This needs a separate shift and mask. 231define i32 @f19(i32 %foo) { 232; CHECK-LABEL: f19: 233; CHECK: # %bb.0: 234; CHECK-NEXT: sra %r2, 28 235; CHECK-NEXT: nilf %r2, 30 236; CHECK-NEXT: br %r14 237 %shr = ashr i32 %foo, 28 238 %and = and i32 %shr, 30 239 ret i32 %and 240} 241 242; ...and again with i64. In this case RISBG is the best way of doing the AND. 243define i64 @f20(i64 %foo) { 244; CHECK-LABEL: f20: 245; CHECK: # %bb.0: 246; CHECK-NEXT: srag %r0, %r2, 60 247; CHECK-NEXT: risbg %r2, %r0, 59, 190, 0 248; CHECK-NEXT: br %r14 249 %shr = ashr i64 %foo, 60 250 %and = and i64 %shr, 30 251 ret i64 %and 252} 253 254; Now try an arithmetic right shift in which the sign bits aren't needed. 255; Introduce a second use of %shr so that the ashr doesn't decompose to 256; an lshr. 257define i32 @f21(i32 %foo, i32 *%dest) { 258; CHECK-LABEL: f21: 259; CHECK: # %bb.0: 260; CHECK-NEXT: srak %r0, %r2, 28 261; CHECK-NEXT: risblg %r2, %r2, 28, 158, 36 262; CHECK-NEXT: st %r0, 0(%r3) 263; CHECK-NEXT: br %r14 264 %shr = ashr i32 %foo, 28 265 store i32 %shr, i32 *%dest 266 %and = and i32 %shr, 14 267 ret i32 %and 268} 269 270; ...and again with i64. 271define i64 @f22(i64 %foo, i64 *%dest) { 272; CHECK-LABEL: f22: 273; CHECK: # %bb.0: 274; CHECK-NEXT: srag %r0, %r2, 60 275; CHECK-NEXT: risbg %r2, %r2, 60, 190, 4 276; CHECK-NEXT: stg %r0, 0(%r3) 277; CHECK-NEXT: br %r14 278 %shr = ashr i64 %foo, 60 279 store i64 %shr, i64 *%dest 280 %and = and i64 %shr, 14 281 ret i64 %and 282} 283 284; Check that we use RISBG for shifted values even if the AND is a 285; natural zero extension. 286define i64 @f23(i64 %foo) { 287; CHECK-LABEL: f23: 288; CHECK: # %bb.0: 289; CHECK-NEXT: risbg %r2, %r2, 56, 191, 62 290; CHECK-NEXT: br %r14 291 %shr = lshr i64 %foo, 2 292 %and = and i64 %shr, 255 293 ret i64 %and 294} 295 296; Test a case where the AND comes before a rotate. This needs a separate 297; mask and rotate. 298define i32 @f24(i32 %foo) { 299; CHECK-LABEL: f24: 300; CHECK: # %bb.0: 301; CHECK-NEXT: nilf %r2, 254 302; CHECK-NEXT: rll %r2, %r2, 29 303; CHECK-NEXT: br %r14 304 %and = and i32 %foo, 254 305 %parta = lshr i32 %and, 3 306 %partb = shl i32 %and, 29 307 %rotl = or i32 %parta, %partb 308 ret i32 %rotl 309} 310 311; ...and again with i64, where a single RISBG is enough. 312define i64 @f25(i64 %foo) { 313; CHECK-LABEL: f25: 314; CHECK: # %bb.0: 315; CHECK-NEXT: risbg %r2, %r2, 57, 187, 3 316; CHECK-NEXT: br %r14 317 %and = and i64 %foo, 14 318 %parta = shl i64 %and, 3 319 %partb = lshr i64 %and, 61 320 %rotl = or i64 %parta, %partb 321 ret i64 %rotl 322} 323 324; Test a wrap-around case in which the AND comes before a rotate. 325; This again needs a separate mask and rotate. 326define i32 @f26(i32 %foo) { 327; CHECK-LABEL: f26: 328; CHECK: # %bb.0: 329; CHECK-NEXT: nill %r2, 65487 330; CHECK-NEXT: rll %r2, %r2, 5 331; CHECK-NEXT: br %r14 332 %and = and i32 %foo, -49 333 %parta = shl i32 %and, 5 334 %partb = lshr i32 %and, 27 335 %rotl = or i32 %parta, %partb 336 ret i32 %rotl 337} 338 339; ...and again with i64, where a single RISBG is OK. 340define i64 @f27(i64 %foo) { 341; CHECK-LABEL: f27: 342; CHECK: # %bb.0: 343; CHECK-NEXT: risbg %r2, %r2, 55, 180, 5 344; CHECK-NEXT: br %r14 345 %and = and i64 %foo, -49 346 %parta = shl i64 %and, 5 347 %partb = lshr i64 %and, 59 348 %rotl = or i64 %parta, %partb 349 ret i64 %rotl 350} 351 352; Test a case where the AND comes before a shift left. 353define i32 @f28(i32 %foo) { 354; CHECK-LABEL: f28: 355; CHECK: # %bb.0: 356; CHECK-NEXT: risblg %r2, %r2, 0, 141, 17 357; CHECK-NEXT: br %r14 358 %and = and i32 %foo, 32766 359 %shl = shl i32 %and, 17 360 ret i32 %shl 361} 362 363; ...and again with i64. 364define i64 @f29(i64 %foo) { 365; CHECK-LABEL: f29: 366; CHECK: # %bb.0: 367; CHECK-NEXT: risbg %r2, %r2, 0, 141, 49 368; CHECK-NEXT: br %r14 369 %and = and i64 %foo, 32766 370 %shl = shl i64 %and, 49 371 ret i64 %shl 372} 373 374; Test the next shift up from f28, in which the mask should get shortened. 375define i32 @f30(i32 %foo) { 376; CHECK-LABEL: f30: 377; CHECK: # %bb.0: 378; CHECK-NEXT: risblg %r2, %r2, 0, 140, 18 379; CHECK-NEXT: br %r14 380 %and = and i32 %foo, 32766 381 %shl = shl i32 %and, 18 382 ret i32 %shl 383} 384 385; ...and again with i64. 386define i64 @f31(i64 %foo) { 387; CHECK-LABEL: f31: 388; CHECK: # %bb.0: 389; CHECK-NEXT: risbg %r2, %r2, 0, 140, 50 390; CHECK-NEXT: br %r14 391 %and = and i64 %foo, 32766 392 %shl = shl i64 %and, 50 393 ret i64 %shl 394} 395 396; Test a wrap-around case in which the shift left comes after the AND. 397; We can't use RISBG for the shift in that case. 398define i32 @f32(i32 %foo) { 399; CHECK-LABEL: f32: 400; CHECK: # %bb.0: 401; CHECK-NEXT: nilf %r2, 4194297 402; CHECK-NEXT: sll %r2, 10 403; CHECK-NEXT: br %r14 404 %and = and i32 %foo, -7 405 %shl = shl i32 %and, 10 406 ret i32 %shl 407} 408 409; ...and again with i64. 410define i64 @f33(i64 %foo) { 411; CHECK-LABEL: f33: 412; CHECK: # %bb.0: 413; CHECK-NEXT: llihf %r0, 4194303 414; CHECK-NEXT: oilf %r0, 4294967289 415; CHECK-NEXT: ngr %r0, %r2 416; CHECK-NEXT: sllg %r2, %r0, 10 417; CHECK-NEXT: br %r14 418 %and = and i64 %foo, -7 419 %shl = shl i64 %and, 10 420 ret i64 %shl 421} 422 423; Test a case where the AND comes before a shift right. 424define i32 @f34(i32 %foo) { 425; CHECK-LABEL: f34: 426; CHECK: # %bb.0: 427; CHECK-NEXT: risblg %r2, %r2, 25, 159, 55 428; CHECK-NEXT: br %r14 429 %and = and i32 %foo, 65535 430 %shl = lshr i32 %and, 9 431 ret i32 %shl 432} 433 434; ...and again with i64. 435define i64 @f35(i64 %foo) { 436; CHECK-LABEL: f35: 437; CHECK: # %bb.0: 438; CHECK-NEXT: risbg %r2, %r2, 57, 191, 55 439; CHECK-NEXT: br %r14 440 %and = and i64 %foo, 65535 441 %shl = lshr i64 %and, 9 442 ret i64 %shl 443} 444 445; Test a wrap-around case where the AND comes before a shift right. 446; We can't use RISBG for the shift in that case. 447define i32 @f36(i32 %foo) { 448; CHECK-LABEL: f36: 449; CHECK: # %bb.0: 450; CHECK-NEXT: nill %r2, 65510 451; CHECK-NEXT: srl %r2, 1 452; CHECK-NEXT: br %r14 453 %and = and i32 %foo, -25 454 %shl = lshr i32 %and, 1 455 ret i32 %shl 456} 457 458; ...and again with i64. 459define i64 @f37(i64 %foo) { 460; CHECK-LABEL: f37: 461; CHECK: # %bb.0: 462; CHECK-NEXT: nill %r2, 65510 463; CHECK-NEXT: srlg %r2, %r2, 1 464; CHECK-NEXT: br %r14 465 %and = and i64 %foo, -25 466 %shl = lshr i64 %and, 1 467 ret i64 %shl 468} 469 470; Test a combination involving a large ASHR and a shift left. We can't 471; use RISBG there. 472define i64 @f38(i64 %foo) { 473; CHECK-LABEL: f38: 474; CHECK: # %bb.0: 475; CHECK-NEXT: srag %r0, %r2, 32 476; CHECK-NEXT: sllg %r2, %r0, 5 477; CHECK-NEXT: br %r14 478 %ashr = ashr i64 %foo, 32 479 %shl = shl i64 %ashr, 5 480 ret i64 %shl 481} 482 483; Try a similar thing in which no shifted sign bits are kept. 484define i64 @f39(i64 %foo, i64 *%dest) { 485; CHECK-LABEL: f39: 486; CHECK: # %bb.0: 487; CHECK-NEXT: srag %r0, %r2, 35 488; CHECK-NEXT: risbg %r2, %r2, 33, 189, 31 489; CHECK-NEXT: stg %r0, 0(%r3) 490; CHECK-NEXT: br %r14 491 %ashr = ashr i64 %foo, 35 492 store i64 %ashr, i64 *%dest 493 %shl = shl i64 %ashr, 2 494 %and = and i64 %shl, 2147483647 495 ret i64 %and 496} 497 498; ...and again with the next highest shift value, where one sign bit is kept. 499define i64 @f40(i64 %foo, i64 *%dest) { 500; CHECK-LABEL: f40: 501; CHECK: # %bb.0: 502; CHECK-NEXT: srag %r0, %r2, 36 503; CHECK-NEXT: risbg %r2, %r0, 33, 189, 2 504; CHECK-NEXT: stg %r0, 0(%r3) 505; CHECK-NEXT: br %r14 506 %ashr = ashr i64 %foo, 36 507 store i64 %ashr, i64 *%dest 508 %shl = shl i64 %ashr, 2 509 %and = and i64 %shl, 2147483647 510 ret i64 %and 511} 512 513; Check a case where the result is zero-extended. 514define i64 @f41(i32 %a) { 515; CHECK-LABEL: f41: 516; CHECK: # %bb.0: 517; CHECK-NEXT: # kill: def $r2l killed $r2l def $r2d 518; CHECK-NEXT: risbg %r2, %r2, 36, 191, 62 519; CHECK-NEXT: br %r14 520 %shl = shl i32 %a, 2 521 %shr = lshr i32 %shl, 4 522 %ext = zext i32 %shr to i64 523 ret i64 %ext 524} 525 526; In this case the sign extension is converted to a pair of 32-bit shifts, 527; which is then extended to 64 bits. We previously used the wrong bit size 528; when testing whether the shifted-in bits of the shift right were significant. 529define i64 @f42(i1 %x) { 530; CHECK-LABEL: f42: 531; CHECK: # %bb.0: 532; CHECK-NEXT: nilf %r2, 1 533; CHECK-NEXT: lcr %r0, %r2 534; CHECK-NEXT: llgcr %r2, %r0 535; CHECK-NEXT: br %r14 536 %ext = sext i1 %x to i8 537 %ext2 = zext i8 %ext to i64 538 ret i64 %ext2 539} 540 541; Check that we get the case where a 64-bit shift is used by a 32-bit and. 542; Note that this cannot use RISBLG, but should use RISBG. 543define signext i32 @f43(i64 %x) { 544; CHECK-LABEL: f43: 545; CHECK: # %bb.0: 546; CHECK-NEXT: risbg %r0, %r2, 32, 189, 52 547; CHECK-NEXT: lgfr %r2, %r0 548; CHECK-NEXT: br %r14 549 %shr3 = lshr i64 %x, 12 550 %shr3.tr = trunc i64 %shr3 to i32 551 %conv = and i32 %shr3.tr, -4 552 ret i32 %conv 553} 554 555; Check that we don't get the case where the 32-bit and mask is not contiguous 556define signext i32 @f44(i64 %x) { 557; CHECK-LABEL: f44: 558; CHECK: # %bb.0: 559; CHECK-NEXT: srlg %r2, %r2, 12 560; CHECK-NEXT: lghi %r0, 10 561; CHECK-NEXT: ngr %r2, %r0 562; CHECK-NEXT: br %r14 563 %shr4 = lshr i64 %x, 12 564 %conv = trunc i64 %shr4 to i32 565 %and = and i32 %conv, 10 566 ret i32 %and 567} 568