1; Test that vector compare / select combinations do not produce any
2; unnecessary pack /unpack / shift instructions.
3;
4; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
5; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s -check-prefix=CHECK-Z14
6
7define <2 x i8> @fun0(<2 x i8> %val1, <2 x i8> %val2, <2 x i8> %val3, <2 x i8> %val4) {
8; CHECK-LABEL: fun0:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vceqb %v0, %v24, %v26
11; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
12; CHECK-NEXT:    br %r14
13  %cmp = icmp eq <2 x i8> %val1, %val2
14  %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
15  ret <2 x i8> %sel
16}
17
18define <2 x i16> @fun1(<2 x i8> %val1, <2 x i8> %val2, <2 x i16> %val3, <2 x i16> %val4) {
19; CHECK-LABEL: fun1:
20; CHECK:       # %bb.0:
21; CHECK-NEXT:    vceqb %v0, %v24, %v26
22; CHECK-NEXT:    vuphb %v0, %v0
23; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
24; CHECK-NEXT:    br %r14
25  %cmp = icmp eq <2 x i8> %val1, %val2
26  %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
27  ret <2 x i16> %sel
28}
29
30define <16 x i8> @fun2(<16 x i8> %val1, <16 x i8> %val2, <16 x i8> %val3, <16 x i8> %val4) {
31; CHECK-LABEL: fun2:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    vceqb %v0, %v24, %v26
34; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
35; CHECK-NEXT:    br %r14
36  %cmp = icmp eq <16 x i8> %val1, %val2
37  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
38  ret <16 x i8> %sel
39}
40
41define <16 x i16> @fun3(<16 x i8> %val1, <16 x i8> %val2, <16 x i16> %val3, <16 x i16> %val4) {
42; CHECK-LABEL: fun3:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vceqb %v0, %v24, %v26
45; CHECK-DAG:     vuphb [[REG0:%v[0-9]+]], %v0
46; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
47; CHECK-DAG:     vuphb [[REG1]], [[REG1]]
48; CHECK-NEXT:    vsel %v24, %v28, %v25, [[REG0]]
49; CHECK-NEXT:    vsel %v26, %v30, %v27, [[REG1]]
50; CHECK-NEXT:    br %r14
51  %cmp = icmp eq <16 x i8> %val1, %val2
52  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
53  ret <16 x i16> %sel
54}
55
56define <32 x i8> @fun4(<32 x i8> %val1, <32 x i8> %val2, <32 x i8> %val3, <32 x i8> %val4) {
57; CHECK-LABEL: fun4:
58; CHECK:       # %bb.0:
59; CHECK-DAG:     vceqb [[REG0:%v[0-9]+]], %v26, %v30
60; CHECK-DAG:     vceqb [[REG1:%v[0-9]+]], %v24, %v28
61; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
62; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
63; CHECK-NEXT:    br %r14
64  %cmp = icmp eq <32 x i8> %val1, %val2
65  %sel = select <32 x i1> %cmp, <32 x i8> %val3, <32 x i8> %val4
66  ret <32 x i8> %sel
67}
68
69define <2 x i8> @fun5(<2 x i16> %val1, <2 x i16> %val2, <2 x i8> %val3, <2 x i8> %val4) {
70; CHECK-LABEL: fun5:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vceqh %v0, %v24, %v26
73; CHECK-NEXT:    vpkh %v0, %v0, %v0
74; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
75; CHECK-NEXT:    br %r14
76  %cmp = icmp eq <2 x i16> %val1, %val2
77  %sel = select <2 x i1> %cmp, <2 x i8> %val3, <2 x i8> %val4
78  ret <2 x i8> %sel
79}
80
81define <2 x i16> @fun6(<2 x i16> %val1, <2 x i16> %val2, <2 x i16> %val3, <2 x i16> %val4) {
82; CHECK-LABEL: fun6:
83; CHECK:       # %bb.0:
84; CHECK-NEXT:    vceqh %v0, %v24, %v26
85; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
86; CHECK-NEXT:    br %r14
87  %cmp = icmp eq <2 x i16> %val1, %val2
88  %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
89  ret <2 x i16> %sel
90}
91
92define <2 x i32> @fun7(<2 x i16> %val1, <2 x i16> %val2, <2 x i32> %val3, <2 x i32> %val4) {
93; CHECK-LABEL: fun7:
94; CHECK:       # %bb.0:
95; CHECK-NEXT:    vceqh %v0, %v24, %v26
96; CHECK-NEXT:    vuphh %v0, %v0
97; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
98; CHECK-NEXT:    br %r14
99  %cmp = icmp eq <2 x i16> %val1, %val2
100  %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
101  ret <2 x i32> %sel
102}
103
104define <8 x i8> @fun8(<8 x i16> %val1, <8 x i16> %val2, <8 x i8> %val3, <8 x i8> %val4) {
105; CHECK-LABEL: fun8:
106; CHECK:       # %bb.0:
107; CHECK-NEXT:    vceqh %v0, %v24, %v26
108; CHECK-NEXT:    vpkh %v0, %v0, %v0
109; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
110; CHECK-NEXT:    br %r14
111  %cmp = icmp eq <8 x i16> %val1, %val2
112  %sel = select <8 x i1> %cmp, <8 x i8> %val3, <8 x i8> %val4
113  ret <8 x i8> %sel
114}
115
116define <8 x i16> @fun9(<8 x i16> %val1, <8 x i16> %val2, <8 x i16> %val3, <8 x i16> %val4) {
117; CHECK-LABEL: fun9:
118; CHECK:       # %bb.0:
119; CHECK-NEXT:    vceqh %v0, %v24, %v26
120; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
121; CHECK-NEXT:    br %r14
122  %cmp = icmp eq <8 x i16> %val1, %val2
123  %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
124  ret <8 x i16> %sel
125}
126
127define <8 x i32> @fun10(<8 x i16> %val1, <8 x i16> %val2, <8 x i32> %val3, <8 x i32> %val4) {
128; CHECK-LABEL: fun10:
129; CHECK:       # %bb.0:
130; CHECK-NEXT:    vceqh %v0, %v24, %v26
131; CHECK-DAG:     vuphh [[REG0:%v[0-9]+]], %v0
132; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
133; CHECK-DAG:     vuphh [[REG1]], [[REG1]]
134; CHECK-NEXT:    vsel %v24, %v28, %v25, [[REG0]]
135; CHECK-NEXT:    vsel %v26, %v30, %v27, [[REG1]]
136; CHECK-NEXT:    br %r14
137  %cmp = icmp eq <8 x i16> %val1, %val2
138  %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
139  ret <8 x i32> %sel
140}
141
142define <16 x i8> @fun11(<16 x i16> %val1, <16 x i16> %val2, <16 x i8> %val3, <16 x i8> %val4) {
143; CHECK-LABEL: fun11:
144; CHECK:       # %bb.0:
145; CHECK-NEXT:    vceqh %v0, %v26, %v30
146; CHECK-NEXT:    vceqh %v1, %v24, %v28
147; CHECK-NEXT:    vpkh %v0, %v1, %v0
148; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
149; CHECK-NEXT:    br %r14
150  %cmp = icmp eq <16 x i16> %val1, %val2
151  %sel = select <16 x i1> %cmp, <16 x i8> %val3, <16 x i8> %val4
152  ret <16 x i8> %sel
153}
154
155define <16 x i16> @fun12(<16 x i16> %val1, <16 x i16> %val2, <16 x i16> %val3, <16 x i16> %val4) {
156; CHECK-LABEL: fun12:
157; CHECK:       # %bb.0:
158; CHECK-DAG:     vceqh [[REG0:%v[0-9]+]], %v26, %v30
159; CHECK-DAG:     vceqh [[REG1:%v[0-9]+]], %v24, %v28
160; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
161; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
162; CHECK-NEXT:    br %r14
163  %cmp = icmp eq <16 x i16> %val1, %val2
164  %sel = select <16 x i1> %cmp, <16 x i16> %val3, <16 x i16> %val4
165  ret <16 x i16> %sel
166}
167
168define <2 x i16> @fun13(<2 x i32> %val1, <2 x i32> %val2, <2 x i16> %val3, <2 x i16> %val4) {
169; CHECK-LABEL: fun13:
170; CHECK:       # %bb.0:
171; CHECK-NEXT:    vceqf %v0, %v24, %v26
172; CHECK-NEXT:    vpkf %v0, %v0, %v0
173; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
174; CHECK-NEXT:    br %r14
175  %cmp = icmp eq <2 x i32> %val1, %val2
176  %sel = select <2 x i1> %cmp, <2 x i16> %val3, <2 x i16> %val4
177  ret <2 x i16> %sel
178}
179
180define <2 x i32> @fun14(<2 x i32> %val1, <2 x i32> %val2, <2 x i32> %val3, <2 x i32> %val4) {
181; CHECK-LABEL: fun14:
182; CHECK:       # %bb.0:
183; CHECK-NEXT:    vceqf %v0, %v24, %v26
184; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
185; CHECK-NEXT:    br %r14
186  %cmp = icmp eq <2 x i32> %val1, %val2
187  %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
188  ret <2 x i32> %sel
189}
190
191define <2 x i64> @fun15(<2 x i32> %val1, <2 x i32> %val2, <2 x i64> %val3, <2 x i64> %val4) {
192; CHECK-LABEL: fun15:
193; CHECK:       # %bb.0:
194; CHECK-NEXT:    vceqf %v0, %v24, %v26
195; CHECK-NEXT:    vuphf %v0, %v0
196; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
197; CHECK-NEXT:    br %r14
198  %cmp = icmp eq <2 x i32> %val1, %val2
199  %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
200  ret <2 x i64> %sel
201}
202
203define <4 x i16> @fun16(<4 x i32> %val1, <4 x i32> %val2, <4 x i16> %val3, <4 x i16> %val4) {
204; CHECK-LABEL: fun16:
205; CHECK:       # %bb.0:
206; CHECK-NEXT:    vceqf %v0, %v24, %v26
207; CHECK-NEXT:    vpkf %v0, %v0, %v0
208; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
209; CHECK-NEXT:    br %r14
210  %cmp = icmp eq <4 x i32> %val1, %val2
211  %sel = select <4 x i1> %cmp, <4 x i16> %val3, <4 x i16> %val4
212  ret <4 x i16> %sel
213}
214
215define <4 x i32> @fun17(<4 x i32> %val1, <4 x i32> %val2, <4 x i32> %val3, <4 x i32> %val4) {
216; CHECK-LABEL: fun17:
217; CHECK:       # %bb.0:
218; CHECK-NEXT:    vceqf %v0, %v24, %v26
219; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
220; CHECK-NEXT:    br %r14
221  %cmp = icmp eq <4 x i32> %val1, %val2
222  %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
223  ret <4 x i32> %sel
224}
225
226define <4 x i64> @fun18(<4 x i32> %val1, <4 x i32> %val2, <4 x i64> %val3, <4 x i64> %val4) {
227; CHECK-LABEL: fun18:
228; CHECK:       # %bb.0:
229; CHECK-NEXT:    vceqf %v0, %v24, %v26
230; CHECK-DAG:     vuphf [[REG0:%v[0-9]+]], %v0
231; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], %v0, %v0
232; CHECK-DAG:     vuphf [[REG1]], [[REG1]]
233; CHECK-NEXT:    vsel %v24, %v28, %v25, [[REG0]]
234; CHECK-NEXT:    vsel %v26, %v30, %v27, [[REG1]]
235; CHECK-NEXT:    br %r14
236  %cmp = icmp eq <4 x i32> %val1, %val2
237  %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
238  ret <4 x i64> %sel
239}
240
241define <8 x i16> @fun19(<8 x i32> %val1, <8 x i32> %val2, <8 x i16> %val3, <8 x i16> %val4) {
242; CHECK-LABEL: fun19:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vceqf %v0, %v26, %v30
245; CHECK-NEXT:    vceqf %v1, %v24, %v28
246; CHECK-NEXT:    vpkf %v0, %v1, %v0
247; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
248; CHECK-NEXT:    br %r14
249  %cmp = icmp eq <8 x i32> %val1, %val2
250  %sel = select <8 x i1> %cmp, <8 x i16> %val3, <8 x i16> %val4
251  ret <8 x i16> %sel
252}
253
254define <8 x i32> @fun20(<8 x i32> %val1, <8 x i32> %val2, <8 x i32> %val3, <8 x i32> %val4) {
255; CHECK-LABEL: fun20:
256; CHECK:       # %bb.0:
257; CHECK-DAG:     vceqf [[REG0:%v[0-9]+]], %v26, %v30
258; CHECK-DAG:     vceqf [[REG1:%v[0-9]+]], %v24, %v28
259; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
260; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
261; CHECK-NEXT:    br %r14
262  %cmp = icmp eq <8 x i32> %val1, %val2
263  %sel = select <8 x i1> %cmp, <8 x i32> %val3, <8 x i32> %val4
264  ret <8 x i32> %sel
265}
266
267define <2 x i32> @fun21(<2 x i64> %val1, <2 x i64> %val2, <2 x i32> %val3, <2 x i32> %val4) {
268; CHECK-LABEL: fun21:
269; CHECK:       # %bb.0:
270; CHECK-NEXT:    vceqg %v0, %v24, %v26
271; CHECK-NEXT:    vpkg %v0, %v0, %v0
272; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
273; CHECK-NEXT:    br %r14
274  %cmp = icmp eq <2 x i64> %val1, %val2
275  %sel = select <2 x i1> %cmp, <2 x i32> %val3, <2 x i32> %val4
276  ret <2 x i32> %sel
277}
278
279define <2 x i64> @fun22(<2 x i64> %val1, <2 x i64> %val2, <2 x i64> %val3, <2 x i64> %val4) {
280; CHECK-LABEL: fun22:
281; CHECK:       # %bb.0:
282; CHECK-NEXT:    vceqg %v0, %v24, %v26
283; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
284; CHECK-NEXT:    br %r14
285  %cmp = icmp eq <2 x i64> %val1, %val2
286  %sel = select <2 x i1> %cmp, <2 x i64> %val3, <2 x i64> %val4
287  ret <2 x i64> %sel
288}
289
290define <4 x i32> @fun23(<4 x i64> %val1, <4 x i64> %val2, <4 x i32> %val3, <4 x i32> %val4) {
291; CHECK-LABEL: fun23:
292; CHECK:       # %bb.0:
293; CHECK-NEXT:    vceqg %v0, %v26, %v30
294; CHECK-NEXT:    vceqg %v1, %v24, %v28
295; CHECK-NEXT:    vpkg %v0, %v1, %v0
296; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
297; CHECK-NEXT:    br %r14
298  %cmp = icmp eq <4 x i64> %val1, %val2
299  %sel = select <4 x i1> %cmp, <4 x i32> %val3, <4 x i32> %val4
300  ret <4 x i32> %sel
301}
302
303define <4 x i64> @fun24(<4 x i64> %val1, <4 x i64> %val2, <4 x i64> %val3, <4 x i64> %val4) {
304; CHECK-LABEL: fun24:
305; CHECK:       # %bb.0:
306; CHECK-DAG:     vceqg [[REG0:%v[0-9]+]], %v26, %v30
307; CHECK-DAG:     vceqg [[REG1:%v[0-9]+]], %v24, %v28
308; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
309; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
310; CHECK-NEXT:    br %r14
311  %cmp = icmp eq <4 x i64> %val1, %val2
312  %sel = select <4 x i1> %cmp, <4 x i64> %val3, <4 x i64> %val4
313  ret <4 x i64> %sel
314}
315
316define <2 x float> @fun25(<2 x float> %val1, <2 x float> %val2, <2 x float> %val3, <2 x float> %val4) {
317; CHECK-LABEL: fun25:
318; CHECK:       # %bb.0:
319; CHECK-NEXT:    vmrlf %v0, %v26, %v26
320; CHECK-NEXT:    vmrlf %v1, %v24, %v24
321; CHECK-NEXT:    vldeb %v0, %v0
322; CHECK-NEXT:    vldeb %v1, %v1
323; CHECK-NEXT:    vfchdb %v0, %v1, %v0
324; CHECK-NEXT:    vmrhf %v1, %v26, %v26
325; CHECK-NEXT:    vmrhf %v2, %v24, %v24
326; CHECK-NEXT:    vldeb %v1, %v1
327; CHECK-NEXT:    vldeb %v2, %v2
328; CHECK-NEXT:    vfchdb %v1, %v2, %v1
329; CHECK-NEXT:    vpkg %v0, %v1, %v0
330; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
331; CHECK-NEXT:    br %r14
332
333; CHECK-Z14-LABEL: fun25:
334; CHECK-Z14:       # %bb.0:
335; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
336; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
337; CHECK-Z14-NEXT:    br %r14
338
339  %cmp = fcmp ogt <2 x float> %val1, %val2
340  %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
341  ret <2 x float> %sel
342}
343
344define <2 x double> @fun26(<2 x float> %val1, <2 x float> %val2, <2 x double> %val3, <2 x double> %val4) {
345; CHECK-LABEL: fun26:
346; CHECK:       # %bb.0:
347; CHECK-NEXT:    vmrlf %v0, %v26, %v26
348; CHECK-NEXT:    vmrlf %v1, %v24, %v24
349; CHECK-NEXT:    vldeb %v0, %v0
350; CHECK-NEXT:    vldeb %v1, %v1
351; CHECK-NEXT:    vfchdb %v0, %v1, %v0
352; CHECK-NEXT:    vmrhf %v1, %v26, %v26
353; CHECK-NEXT:    vmrhf %v2, %v24, %v24
354; CHECK-NEXT:    vldeb %v1, %v1
355; CHECK-NEXT:    vldeb %v2, %v2
356; CHECK-NEXT:    vfchdb %v1, %v2, %v1
357; CHECK-NEXT:    vpkg %v0, %v1, %v0
358; CHECK-NEXT:    vuphf %v0, %v0
359; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
360; CHECK-NEXT:    br %r14
361
362; CHECK-Z14-LABEL: fun26:
363; CHECK-Z14:       # %bb.0:
364; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
365; CHECK-Z14-NEXT:    vuphf   %v0, %v0
366; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
367; CHECK-Z14-NEXT:    br %r14
368
369  %cmp = fcmp ogt <2 x float> %val1, %val2
370  %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
371  ret <2 x double> %sel
372}
373
374; Test a widening select of floats.
375define <2 x float> @fun27(<2 x i8> %val1, <2 x i8> %val2, <2 x float> %val3, <2 x float> %val4) {
376; CHECK-LABEL: fun27:
377; CHECK:       # %bb.0:
378; CHECK-NEXT:    vceqb %v0, %v24, %v26
379; CHECK-NEXT:    vuphb %v0, %v0
380; CHECK-NEXT:    vuphh %v0, %v0
381; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
382; CHECK-NEXT:    br %r14
383
384  %cmp = icmp eq <2 x i8> %val1, %val2
385  %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
386  ret <2 x float> %sel
387}
388
389define <4 x float> @fun28(<4 x float> %val1, <4 x float> %val2, <4 x float> %val3, <4 x float> %val4) {
390; CHECK-LABEL: fun28:
391; CHECK:       # %bb.0:
392; CHECK-NEXT:    vmrlf %v0, %v26, %v26
393; CHECK-NEXT:    vmrlf %v1, %v24, %v24
394; CHECK-NEXT:    vldeb %v0, %v0
395; CHECK-NEXT:    vldeb %v1, %v1
396; CHECK-NEXT:    vfchdb %v0, %v1, %v0
397; CHECK-NEXT:    vmrhf %v1, %v26, %v26
398; CHECK-NEXT:    vmrhf %v2, %v24, %v24
399; CHECK-NEXT:    vldeb %v1, %v1
400; CHECK-NEXT:    vldeb %v2, %v2
401; CHECK-NEXT:    vfchdb %v1, %v2, %v1
402; CHECK-NEXT:    vpkg %v0, %v1, %v0
403; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
404; CHECK-NEXT:    br %r14
405
406; CHECK-Z14-LABEL: fun28:
407; CHECK-Z14:       # %bb.0:
408; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
409; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v30, %v0
410; CHECK-Z14-NEXT:    br %r14
411
412  %cmp = fcmp ogt <4 x float> %val1, %val2
413  %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
414  ret <4 x float> %sel
415}
416
417define <4 x double> @fun29(<4 x float> %val1, <4 x float> %val2, <4 x double> %val3, <4 x double> %val4) {
418; CHECK-LABEL: fun29:
419; CHECK:       # %bb.0:
420; CHECK-NEXT:    vmrlf %v0, %v26, %v26
421; CHECK-NEXT:    vmrlf %v1, %v24, %v24
422; CHECK-NEXT:    vldeb %v0, %v0
423; CHECK-NEXT:    vldeb %v1, %v1
424; CHECK-NEXT:    vfchdb %v0, %v1, %v0
425; CHECK-NEXT:    vmrhf %v1, %v26, %v26
426; CHECK-NEXT:    vmrhf %v2, %v24, %v24
427; CHECK-NEXT:    vldeb %v1, %v1
428; CHECK-NEXT:    vldeb %v2, %v2
429; CHECK-NEXT:    vfchdb %v1, %v2, %v1
430; CHECK-NEXT:    vpkg [[REG0:%v[0-9]+]], %v1, %v0
431; CHECK-DAG:     vmrlg [[REG1:%v[0-9]+]], [[REG0]], [[REG0]]
432; CHECK-DAG:     vuphf [[REG1]], [[REG1]]
433; CHECK-DAG:     vuphf [[REG2:%v[0-9]+]], [[REG0]]
434; CHECK-NEXT:    vsel %v24, %v28, %v25, [[REG2]]
435; CHECK-NEXT:    vsel %v26, %v30, %v27, [[REG1]]
436; CHECK-NEXT:    br %r14
437
438; CHECK-Z14-LABEL: fun29:
439; CHECK-Z14:       # %bb.0:
440; CHECK-Z14-NEXT:    vfchsb  %v0, %v24, %v26
441; CHECK-Z14-DAG:     vuphf   [[REG0:%v[0-9]+]], %v0
442; CHECK-Z14-DAG:     vmrlg   [[REG1:%v[0-9]+]], %v0, %v0
443; CHECK-Z14-DAG:     vuphf   [[REG1]], [[REG1]]
444; CHECK-Z14-NEXT:    vsel    %v24, %v28, %v25, [[REG0]]
445; CHECK-Z14-NEXT:    vsel    %v26, %v30, %v27, [[REG1]]
446; CHECK-Z14-NEXT:    br %r14
447
448  %cmp = fcmp ogt <4 x float> %val1, %val2
449  %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
450  ret <4 x double> %sel
451}
452
453define <8 x float> @fun30(<8 x float> %val1, <8 x float> %val2, <8 x float> %val3, <8 x float> %val4) {
454; CHECK-Z14-LABEL: fun30:
455; CHECK-Z14:       # %bb.0:
456; CHECK-Z14-DAG:     vfchsb  [[REG0:%v[0-9]+]], %v26, %v30
457; CHECK-Z14-DAG:     vfchsb  [[REG1:%v[0-9]+]], %v24, %v28
458; CHECK-Z14-DAG:     vsel    %v24, %v25, %v29, [[REG1]]
459; CHECK-Z14-DAG:     vsel    %v26, %v27, %v31, [[REG0]]
460; CHECK-Z14-NEXT:    br %r14
461  %cmp = fcmp ogt <8 x float> %val1, %val2
462  %sel = select <8 x i1> %cmp, <8 x float> %val3, <8 x float> %val4
463  ret <8 x float> %sel
464}
465
466define <2 x float> @fun31(<2 x double> %val1, <2 x double> %val2, <2 x float> %val3, <2 x float> %val4) {
467; CHECK-LABEL: fun31:
468; CHECK:       # %bb.0:
469; CHECK-NEXT:    vfchdb %v0, %v24, %v26
470; CHECK-NEXT:    vpkg %v0, %v0, %v0
471; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
472; CHECK-NEXT:    br %r14
473
474  %cmp = fcmp ogt <2 x double> %val1, %val2
475  %sel = select <2 x i1> %cmp, <2 x float> %val3, <2 x float> %val4
476  ret <2 x float> %sel
477}
478
479define <2 x double> @fun32(<2 x double> %val1, <2 x double> %val2, <2 x double> %val3, <2 x double> %val4) {
480; CHECK-LABEL: fun32:
481; CHECK:       # %bb.0:
482; CHECK-NEXT:    vfchdb %v0, %v24, %v26
483; CHECK-NEXT:    vsel %v24, %v28, %v30, %v0
484; CHECK-NEXT:    br %r14
485  %cmp = fcmp ogt <2 x double> %val1, %val2
486  %sel = select <2 x i1> %cmp, <2 x double> %val3, <2 x double> %val4
487  ret <2 x double> %sel
488}
489
490define <4 x float> @fun33(<4 x double> %val1, <4 x double> %val2, <4 x float> %val3, <4 x float> %val4) {
491; CHECK-LABEL: fun33:
492; CHECK:       # %bb.0:
493; CHECK-NEXT:    vfchdb %v0, %v26, %v30
494; CHECK-NEXT:    vfchdb %v1, %v24, %v28
495; CHECK-NEXT:    vpkg %v0, %v1, %v0
496; CHECK-NEXT:    vsel %v24, %v25, %v27, %v0
497; CHECK-NEXT:    br %r14
498  %cmp = fcmp ogt <4 x double> %val1, %val2
499  %sel = select <4 x i1> %cmp, <4 x float> %val3, <4 x float> %val4
500  ret <4 x float> %sel
501}
502
503define <4 x double> @fun34(<4 x double> %val1, <4 x double> %val2, <4 x double> %val3, <4 x double> %val4) {
504; CHECK-LABEL: fun34:
505; CHECK:       # %bb.0:
506; CHECK-DAG:     vfchdb [[REG0:%v[0-9]+]], %v26, %v30
507; CHECK-DAG:     vfchdb [[REG1:%v[0-9]+]], %v24, %v28
508; CHECK-DAG:     vsel %v24, %v25, %v29, [[REG1]]
509; CHECK-DAG:     vsel %v26, %v27, %v31, [[REG0]]
510; CHECK-NEXT:    br %r14
511  %cmp = fcmp ogt <4 x double> %val1, %val2
512  %sel = select <4 x i1> %cmp, <4 x double> %val3, <4 x double> %val4
513  ret <4 x double> %sel
514}
515