1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi %s -verify-machineinstrs -o - | FileCheck %s
3
4define i32 @csinc_const_65(i32 %a) {
5; CHECK-LABEL: csinc_const_65:
6; CHECK:       @ %bb.0: @ %entry
7; CHECK-NEXT:    movs r1, #5
8; CHECK-NEXT:    cmp r0, #45
9; CHECK-NEXT:    cinc r0, r1, gt
10; CHECK-NEXT:    bx lr
11entry:
12  %cmp = icmp sgt i32 %a, 45
13  %spec.select = select i1 %cmp, i32 6, i32 5
14  ret i32 %spec.select
15}
16
17define i32 @csinc_const_56(i32 %a) {
18; CHECK-LABEL: csinc_const_56:
19; CHECK:       @ %bb.0: @ %entry
20; CHECK-NEXT:    movs r1, #5
21; CHECK-NEXT:    cmp r0, #45
22; CHECK-NEXT:    cinc r0, r1, le
23; CHECK-NEXT:    bx lr
24entry:
25  %cmp = icmp sgt i32 %a, 45
26  %spec.select = select i1 %cmp, i32 5, i32 6
27  ret i32 %spec.select
28}
29
30define i32 @csinc_const_zext(i32 %a) {
31; CHECK-LABEL: csinc_const_zext:
32; CHECK:       @ %bb.0: @ %entry
33; CHECK-NEXT:    cmp r0, #45
34; CHECK-NEXT:    cset r0, gt
35; CHECK-NEXT:    bx lr
36entry:
37  %cmp = icmp sgt i32 %a, 45
38  %spec.select = zext i1 %cmp to i32
39  ret i32 %spec.select
40}
41
42define i32 @csinv_const_56(i32 %a) {
43; CHECK-LABEL: csinv_const_56:
44; CHECK:       @ %bb.0: @ %entry
45; CHECK-NEXT:    movs r1, #5
46; CHECK-NEXT:    cmp r0, #45
47; CHECK-NEXT:    cinv r0, r1, gt
48; CHECK-NEXT:    bx lr
49entry:
50  %cmp = icmp sgt i32 %a, 45
51  %spec.select = select i1 %cmp, i32 -6, i32 5
52  ret i32 %spec.select
53}
54
55define i32 @csinv_const_65(i32 %a) {
56; CHECK-LABEL: csinv_const_65:
57; CHECK:       @ %bb.0: @ %entry
58; CHECK-NEXT:    movs r1, #5
59; CHECK-NEXT:    cmp r0, #45
60; CHECK-NEXT:    cinv r0, r1, le
61; CHECK-NEXT:    bx lr
62entry:
63  %cmp = icmp sgt i32 %a, 45
64  %spec.select = select i1 %cmp, i32 5, i32 -6
65  ret i32 %spec.select
66}
67
68define i32 @csinv_const_sext(i32 %a) {
69; CHECK-LABEL: csinv_const_sext:
70; CHECK:       @ %bb.0: @ %entry
71; CHECK-NEXT:    cmp r0, #45
72; CHECK-NEXT:    csetm r0, gt
73; CHECK-NEXT:    bx lr
74entry:
75  %cmp = icmp sgt i32 %a, 45
76  %spec.select = sext i1 %cmp to i32
77  ret i32 %spec.select
78}
79
80define i32 @csneg_const(i32 %a) {
81; CHECK-LABEL: csneg_const:
82; CHECK:       @ %bb.0: @ %entry
83; CHECK-NEXT:    movs r1, #1
84; CHECK-NEXT:    cmp r0, #45
85; CHECK-NEXT:    cneg r0, r1, le
86; CHECK-NEXT:    bx lr
87entry:
88  %cmp = icmp sgt i32 %a, 45
89  %spec.select = select i1 %cmp, i32 1, i32 -1
90  ret i32 %spec.select
91}
92
93define i32 @csneg_const_r(i32 %a) {
94; CHECK-LABEL: csneg_const_r:
95; CHECK:       @ %bb.0: @ %entry
96; CHECK-NEXT:    movs r1, #1
97; CHECK-NEXT:    cmp r0, #45
98; CHECK-NEXT:    cneg r0, r1, gt
99; CHECK-NEXT:    bx lr
100entry:
101  %cmp = icmp sgt i32 %a, 45
102  %spec.select = select i1 %cmp, i32 -1, i32 1
103  ret i32 %spec.select
104}
105
106define i32 @csel_var(i32 %a, i32 %b, i32 %c) {
107; CHECK-LABEL: csel_var:
108; CHECK:       @ %bb.0: @ %entry
109; CHECK-NEXT:    cmp r0, #45
110; CHECK-NEXT:    csel r0, r1, r2, gt
111; CHECK-NEXT:    bx lr
112entry:
113  %cmp = icmp sgt i32 %a, 45
114  %spec.select = select i1 %cmp, i32 %b, i32 %c
115  ret i32 %spec.select
116}
117
118define i32 @csinc_var(i32 %a, i32 %b, i32 %c) {
119; CHECK-LABEL: csinc_var:
120; CHECK:       @ %bb.0: @ %entry
121; CHECK-NEXT:    cmp r0, #45
122; CHECK-NEXT:    csinc r0, r1, r2, gt
123; CHECK-NEXT:    bx lr
124entry:
125  %cmp = icmp sgt i32 %a, 45
126  %cplus1 = add nsw i32 %c, 1
127  %spec.select = select i1 %cmp, i32 %b, i32 %cplus1
128  ret i32 %spec.select
129}
130
131define i32 @csinc_swap_var(i32 %a, i32 %b, i32 %c) {
132; CHECK-LABEL: csinc_swap_var:
133; CHECK:       @ %bb.0: @ %entry
134; CHECK-NEXT:    cmp r0, #45
135; CHECK-NEXT:    csinc r0, r2, r1, le
136; CHECK-NEXT:    bx lr
137entry:
138  %cmp = icmp sgt i32 %a, 45
139  %bplus1 = add nsw i32 %b, 1
140  %spec.select = select i1 %cmp, i32 %bplus1, i32 %c
141  ret i32 %spec.select
142}
143
144define i32 @csinv_var(i32 %a, i32 %b, i32 %c) {
145; CHECK-LABEL: csinv_var:
146; CHECK:       @ %bb.0: @ %entry
147; CHECK-NEXT:    cmp r0, #45
148; CHECK-NEXT:    csinv r0, r1, r2, gt
149; CHECK-NEXT:    bx lr
150entry:
151  %cmp = icmp sgt i32 %a, 45
152  %cinv = xor i32 %c, -1
153  %spec.select = select i1 %cmp, i32 %b, i32 %cinv
154  ret i32 %spec.select
155}
156
157define i32 @csinv_swap_var(i32 %a, i32 %b, i32 %c) {
158; CHECK-LABEL: csinv_swap_var:
159; CHECK:       @ %bb.0: @ %entry
160; CHECK-NEXT:    cmp r0, #45
161; CHECK-NEXT:    csinv r0, r2, r1, le
162; CHECK-NEXT:    bx lr
163entry:
164  %cmp = icmp sgt i32 %a, 45
165  %binv = xor i32 %b, -1
166  %spec.select = select i1 %cmp, i32 %binv, i32 %c
167  ret i32 %spec.select
168}
169
170define i32 @csneg_var(i32 %a, i32 %b, i32 %c) {
171; CHECK-LABEL: csneg_var:
172; CHECK:       @ %bb.0: @ %entry
173; CHECK-NEXT:    cmp r0, #45
174; CHECK-NEXT:    csneg r0, r1, r2, gt
175; CHECK-NEXT:    bx lr
176entry:
177  %cmp = icmp sgt i32 %a, 45
178  %cneg = sub i32 0, %c
179  %spec.select = select i1 %cmp, i32 %b, i32 %cneg
180  ret i32 %spec.select
181}
182
183define i32 @csneg_swap_var_sgt(i32 %a, i32 %b, i32 %c) {
184; CHECK-LABEL: csneg_swap_var_sgt:
185; CHECK:       @ %bb.0: @ %entry
186; CHECK-NEXT:    cmp r0, #45
187; CHECK-NEXT:    csneg r0, r2, r1, le
188; CHECK-NEXT:    bx lr
189entry:
190  %cmp = icmp sgt i32 %a, 45
191  %bneg = sub i32 0, %b
192  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
193  ret i32 %spec.select
194}
195
196define i32 @csneg_swap_var_sge(i32 %a, i32 %b, i32 %c) {
197; CHECK-LABEL: csneg_swap_var_sge:
198; CHECK:       @ %bb.0: @ %entry
199; CHECK-NEXT:    cmp r0, #44
200; CHECK-NEXT:    csneg r0, r2, r1, le
201; CHECK-NEXT:    bx lr
202entry:
203  %cmp = icmp sge i32 %a, 45
204  %bneg = sub i32 0, %b
205  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
206  ret i32 %spec.select
207}
208
209define i32 @csneg_swap_var_sle(i32 %a, i32 %b, i32 %c) {
210; CHECK-LABEL: csneg_swap_var_sle:
211; CHECK:       @ %bb.0: @ %entry
212; CHECK-NEXT:    cmp r0, #46
213; CHECK-NEXT:    csneg r0, r2, r1, ge
214; CHECK-NEXT:    bx lr
215entry:
216  %cmp = icmp sle i32 %a, 45
217  %bneg = sub i32 0, %b
218  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
219  ret i32 %spec.select
220}
221
222define i32 @csneg_swap_var_slt(i32 %a, i32 %b, i32 %c) {
223; CHECK-LABEL: csneg_swap_var_slt:
224; CHECK:       @ %bb.0: @ %entry
225; CHECK-NEXT:    cmp r0, #45
226; CHECK-NEXT:    csneg r0, r2, r1, ge
227; CHECK-NEXT:    bx lr
228entry:
229  %cmp = icmp slt i32 %a, 45
230  %bneg = sub i32 0, %b
231  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
232  ret i32 %spec.select
233}
234
235define i32 @csneg_swap_var_ugt(i32 %a, i32 %b, i32 %c) {
236; CHECK-LABEL: csneg_swap_var_ugt:
237; CHECK:       @ %bb.0: @ %entry
238; CHECK-NEXT:    cmp r0, #45
239; CHECK-NEXT:    csneg r0, r2, r1, ls
240; CHECK-NEXT:    bx lr
241entry:
242  %cmp = icmp ugt i32 %a, 45
243  %bneg = sub i32 0, %b
244  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
245  ret i32 %spec.select
246}
247
248define i32 @csneg_swap_var_uge(i32 %a, i32 %b, i32 %c) {
249; CHECK-LABEL: csneg_swap_var_uge:
250; CHECK:       @ %bb.0: @ %entry
251; CHECK-NEXT:    cmp r0, #44
252; CHECK-NEXT:    csneg r0, r2, r1, ls
253; CHECK-NEXT:    bx lr
254entry:
255  %cmp = icmp uge i32 %a, 45
256  %bneg = sub i32 0, %b
257  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
258  ret i32 %spec.select
259}
260
261define i32 @csneg_swap_var_ule(i32 %a, i32 %b, i32 %c) {
262; CHECK-LABEL: csneg_swap_var_ule:
263; CHECK:       @ %bb.0: @ %entry
264; CHECK-NEXT:    cmp r0, #46
265; CHECK-NEXT:    csneg r0, r2, r1, hs
266; CHECK-NEXT:    bx lr
267entry:
268  %cmp = icmp ule i32 %a, 45
269  %bneg = sub i32 0, %b
270  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
271  ret i32 %spec.select
272}
273
274define i32 @csneg_swap_var_ult(i32 %a, i32 %b, i32 %c) {
275; CHECK-LABEL: csneg_swap_var_ult:
276; CHECK:       @ %bb.0: @ %entry
277; CHECK-NEXT:    cmp r0, #45
278; CHECK-NEXT:    csneg r0, r2, r1, hs
279; CHECK-NEXT:    bx lr
280entry:
281  %cmp = icmp ult i32 %a, 45
282  %bneg = sub i32 0, %b
283  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
284  ret i32 %spec.select
285}
286
287define i32 @csneg_swap_var_ne(i32 %a, i32 %b, i32 %c) {
288; CHECK-LABEL: csneg_swap_var_ne:
289; CHECK:       @ %bb.0: @ %entry
290; CHECK-NEXT:    cmp r0, #45
291; CHECK-NEXT:    csneg r0, r2, r1, ne
292; CHECK-NEXT:    bx lr
293entry:
294  %cmp = icmp eq i32 %a, 45
295  %bneg = sub i32 0, %b
296  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
297  ret i32 %spec.select
298}
299
300define i32 @csneg_swap_var_eq(i32 %a, i32 %b, i32 %c) {
301; CHECK-LABEL: csneg_swap_var_eq:
302; CHECK:       @ %bb.0: @ %entry
303; CHECK-NEXT:    cmp r0, #45
304; CHECK-NEXT:    csneg r0, r2, r1, eq
305; CHECK-NEXT:    bx lr
306entry:
307  %cmp = icmp ne i32 %a, 45
308  %bneg = sub i32 0, %b
309  %spec.select = select i1 %cmp, i32 %bneg, i32 %c
310  ret i32 %spec.select
311}
312
313define i32 @csinc_inplace(i32 %a, i32 %b) {
314; CHECK-LABEL: csinc_inplace:
315; CHECK:       @ %bb.0: @ %entry
316; CHECK-NEXT:    cmp r1, #45
317; CHECK-NEXT:    cinc r0, r0, gt
318; CHECK-NEXT:    bx lr
319entry:
320  %cmp = icmp sgt i32 %b, 45
321  %inc = zext i1 %cmp to i32
322  %spec.select = add nsw i32 %inc, %a
323  ret i32 %spec.select
324}
325
326define i32 @csinv_inplace(i32 %a, i32 %b) {
327; CHECK-LABEL: csinv_inplace:
328; CHECK:       @ %bb.0: @ %entry
329; CHECK-NEXT:    cmp r1, #45
330; CHECK-NEXT:    cinv r0, r0, gt
331; CHECK-NEXT:    bx lr
332entry:
333  %cmp = icmp sgt i32 %b, 45
334  %sub = sext i1 %cmp to i32
335  %xor = xor i32 %sub, %a
336  ret i32 %xor
337}
338
339define i32 @csinc_to_csinv(i32 %a) {
340; CHECK-LABEL: csinc_to_csinv:
341; CHECK:       @ %bb.0: @ %entry
342; CHECK-NEXT:    cmp r0, #46
343; CHECK-NEXT:    csetm r0, lt
344; CHECK-NEXT:    bx lr
345entry:
346  %cmp = icmp sgt i32 %a, 45
347  %spec.select = select i1 %cmp, i32 0, i32 1
348  %s = sub i32 0, %spec.select
349  ret i32 %s
350}
351
352define i32 @csinc_to_csinv_multi(i32 %a) {
353; CHECK-LABEL: csinc_to_csinv_multi:
354; CHECK:       @ %bb.0: @ %entry
355; CHECK-NEXT:    cmp r0, #46
356; CHECK-NEXT:    cset r0, lt
357; CHECK-NEXT:    rsbs r1, r0, #0
358; CHECK-NEXT:    eors r0, r1
359; CHECK-NEXT:    bx lr
360entry:
361  %cmp = icmp sgt i32 %a, 45
362  %spec.select = select i1 %cmp, i32 0, i32 1
363  %s = sub i32 0, %spec.select
364  %t = xor i32 %s, %spec.select
365  ret i32 %t
366}
367