1 /* tc-i960.c - All the i80960-specific stuff
2    Copyright 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3    1999, 2000, 2001, 2002, 2003
4    Free Software Foundation, Inc.
5 
6    This file is part of GAS.
7 
8    GAS is free software; you can redistribute it and/or modify
9    it under the terms of the GNU General Public License as published by
10    the Free Software Foundation; either version 2, or (at your option)
11    any later version.
12 
13    GAS is distributed in the hope that it will be useful,
14    but WITHOUT ANY WARRANTY; without even the implied warranty of
15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16    GNU General Public License for more details.
17 
18    You should have received a copy of the GNU General Public License
19    along with GAS; see the file COPYING.  If not, write to the Free
20    Software Foundation, 59 Temple Place - Suite 330, Boston, MA
21    02111-1307, USA.  */
22 
23 /* See comment on md_parse_option for 80960-specific invocation options.  */
24 
25 /* There are 4 different lengths of (potentially) symbol-based displacements
26    in the 80960 instruction set, each of which could require address fix-ups
27    and (in the case of external symbols) emission of relocation directives:
28 
29    32-bit (MEMB)
30         This is a standard length for the base assembler and requires no
31         special action.
32 
33    13-bit (COBR)
34         This is a non-standard length, but the base assembler has a
35         hook for bit field address fixups: the fixS structure can
36         point to a descriptor of the field, in which case our
37         md_number_to_field() routine gets called to process it.
38 
39         I made the hook a little cleaner by having fix_new() (in the base
40         assembler) return a pointer to the fixS in question.  And I made it a
41         little simpler by storing the field size (in this case 13) instead of
42         of a pointer to another structure:  80960 displacements are ALWAYS
43         stored in the low-order bits of a 4-byte word.
44 
45         Since the target of a COBR cannot be external, no relocation
46         directives for this size displacement have to be generated.
47         But the base assembler had to be modified to issue error
48         messages if the symbol did turn out to be external.
49 
50    24-bit (CTRL)
51         Fixups are handled as for the 13-bit case (except that 24 is stored
52         in the fixS).
53 
54         The relocation directive generated is the same as that for the 32-bit
55         displacement, except that it's PC-relative (the 32-bit displacement
56         never is).   The i80960 version of the linker needs a mod to
57         distinguish and handle the 24-bit case.
58 
59    12-bit (MEMA)
60         MEMA formats are always promoted to MEMB (32-bit) if the displacement
61         is based on a symbol, because it could be relocated at link time.
62         The only time we use the 12-bit format is if an absolute value of
63         less than 4096 is specified, in which case we need neither a fixup nor
64         a relocation directive.  */
65 
66 #include <stdio.h>
67 
68 #include "as.h"
69 
70 #include "safe-ctype.h"
71 #include "obstack.h"
72 
73 #include "opcode/i960.h"
74 
75 #if defined (OBJ_AOUT) || defined (OBJ_BOUT)
76 
77 #define TC_S_IS_SYSPROC(s)	((1<=S_GET_OTHER(s)) && (S_GET_OTHER(s)<=32))
78 #define TC_S_IS_BALNAME(s)	(S_GET_OTHER(s) == N_BALNAME)
79 #define TC_S_IS_CALLNAME(s)	(S_GET_OTHER(s) == N_CALLNAME)
80 #define TC_S_IS_BADPROC(s)	((S_GET_OTHER(s) != 0) && !TC_S_IS_CALLNAME(s) && !TC_S_IS_BALNAME(s) && !TC_S_IS_SYSPROC(s))
81 
82 #define TC_S_SET_SYSPROC(s, p)	(S_SET_OTHER((s), (p)+1))
83 #define TC_S_GET_SYSPROC(s)	(S_GET_OTHER(s)-1)
84 
85 #define TC_S_FORCE_TO_BALNAME(s)	(S_SET_OTHER((s), N_BALNAME))
86 #define TC_S_FORCE_TO_CALLNAME(s)	(S_SET_OTHER((s), N_CALLNAME))
87 #define TC_S_FORCE_TO_SYSPROC(s)	{;}
88 
89 #else /* ! OBJ_A/BOUT */
90 #ifdef OBJ_COFF
91 
92 #define TC_S_IS_SYSPROC(s)	(S_GET_STORAGE_CLASS(s) == C_SCALL)
93 #define TC_S_IS_BALNAME(s)	(SF_GET_BALNAME(s))
94 #define TC_S_IS_CALLNAME(s)	(SF_GET_CALLNAME(s))
95 #define TC_S_IS_BADPROC(s)	(TC_S_IS_SYSPROC(s) && TC_S_GET_SYSPROC(s) < 0 && 31 < TC_S_GET_SYSPROC(s))
96 
97 #define TC_S_SET_SYSPROC(s, p)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx = (p))
98 #define TC_S_GET_SYSPROC(s)	((s)->sy_symbol.ost_auxent[1].x_sc.x_stindx)
99 
100 #define TC_S_FORCE_TO_BALNAME(s)	(SF_SET_BALNAME(s))
101 #define TC_S_FORCE_TO_CALLNAME(s)	(SF_SET_CALLNAME(s))
102 #define TC_S_FORCE_TO_SYSPROC(s)	(S_SET_STORAGE_CLASS((s), C_SCALL))
103 
104 #else /* ! OBJ_COFF */
105 #ifdef OBJ_ELF
106 #define TC_S_IS_SYSPROC(s)	0
107 
108 #define TC_S_IS_BALNAME(s)	0
109 #define TC_S_IS_CALLNAME(s)	0
110 #define TC_S_IS_BADPROC(s)	0
111 
112 #define TC_S_SET_SYSPROC(s, p)
113 #define TC_S_GET_SYSPROC(s) 0
114 
115 #define TC_S_FORCE_TO_BALNAME(s)
116 #define TC_S_FORCE_TO_CALLNAME(s)
117 #define TC_S_FORCE_TO_SYSPROC(s)
118 #else
119  #error COFF, a.out, b.out, and ELF are the only supported formats.
120 #endif /* ! OBJ_ELF */
121 #endif /* ! OBJ_COFF */
122 #endif /* ! OBJ_A/BOUT */
123 
124 extern char *input_line_pointer;
125 
126 #if !defined (BFD_ASSEMBLER) && !defined (BFD)
127 #ifdef OBJ_COFF
128 const int md_reloc_size = sizeof (struct reloc);
129 #else /* OBJ_COFF */
130 const int md_reloc_size = sizeof (struct relocation_info);
131 #endif /* OBJ_COFF */
132 #endif
133 
134 /* Local i80960 routines.  */
135 struct memS;
136 struct regop;
137 
138 /* Emit branch-prediction instrumentation code */
139 static void brcnt_emit PARAMS ((void));
140 /* Return next branch local label */
141 static char *brlab_next PARAMS ((void));
142 /* Generate COBR instruction */
143 static void cobr_fmt PARAMS ((char *[], long, struct i960_opcode *));
144 /* Generate CTRL instruction */
145 static void ctrl_fmt PARAMS ((char *, long, int));
146 /* Emit (internally) binary */
147 static char *emit PARAMS ((long));
148 /* Break arguments out of comma-separated list */
149 static int get_args PARAMS ((char *, char *[]));
150 /* Handle COBR or CTRL displacement */
151 static void get_cdisp PARAMS ((char *, char *, long, int, int, int));
152 /* Find index specification string */
153 static char *get_ispec PARAMS ((char *));
154 /* Translate text to register number */
155 static int get_regnum PARAMS ((char *));
156 /* Lexical scan of instruction source */
157 static int i_scan PARAMS ((char *, char *[]));
158 /* Generate MEMA or MEMB instruction */
159 static void mem_fmt PARAMS ((char *[], struct i960_opcode *, int));
160 /* Convert MEMA instruction to MEMB format */
161 static void mema_to_memb PARAMS ((char *));
162 /* Parse an expression */
163 static void parse_expr PARAMS ((char *, expressionS *));
164 /* Parse and replace a 'ldconst' pseudo-op */
165 static int parse_ldconst PARAMS ((char *[]));
166 /* Parse a memory operand */
167 static void parse_memop PARAMS ((struct memS *, char *, int));
168 /* Parse machine-dependent pseudo-op */
169 static void parse_po PARAMS ((int));
170 /* Parse a register operand */
171 static void parse_regop PARAMS ((struct regop *, char *, char));
172 /* Generate a REG format instruction */
173 static void reg_fmt PARAMS ((char *[], struct i960_opcode *));
174 /* "De-optimize" cobr into compare/branch */
175 static void relax_cobr PARAMS ((fragS *));
176 /* Process '.leafproc' pseudo-op */
177 static void s_leafproc PARAMS ((int, char *[]));
178 /* Process '.sysproc' pseudo-op */
179 static void s_sysproc PARAMS ((int, char *[]));
180 /* Will a 'shlo' substitute for a 'ldconst'? */
181 static int shift_ok PARAMS ((int));
182 /* Give syntax error */
183 static void syntax PARAMS ((void));
184 /* Target chip supports spec-func register? */
185 static int targ_has_sfr PARAMS ((int));
186 /* Target chip supports instruction set? */
187 static int targ_has_iclass PARAMS ((int));
188 
189 /* See md_parse_option() for meanings of these options */
190 static char norelax;		/* True if -norelax switch seen */
191 static char instrument_branches;	/* True if -b switch seen */
192 
193 /* Characters that always start a comment.
194    If the pre-processor is disabled, these aren't very useful.
195  */
196 const char comment_chars[] = "#";
197 
198 /* Characters that only start a comment at the beginning of
199    a line.  If the line seems to have the form '# 123 filename'
200    .line and .file directives will appear in the pre-processed output.
201 
202    Note that input_file.c hand checks for '#' at the beginning of the
203    first line of the input file.  This is because the compiler outputs
204    #NO_APP at the beginning of its output.
205  */
206 
207 /* Also note that comments started like this one will always work.  */
208 
209 const char line_comment_chars[] = "#";
210 
211 const char line_separator_chars[] = ";";
212 
213 /* Chars that can be used to separate mant from exp in floating point nums */
214 const char EXP_CHARS[] = "eE";
215 
216 /* Chars that mean this number is a floating point constant,
217    as in 0f12.456 or 0d1.2345e12
218  */
219 const char FLT_CHARS[] = "fFdDtT";
220 
221 /* Table used by base assembler to relax addresses based on varying length
222    instructions.  The fields are:
223      1) most positive reach of this state,
224      2) most negative reach of this state,
225      3) how many bytes this mode will add to the size of the current frag
226      4) which index into the table to try if we can't fit into this one.
227 
228    For i80960, the only application is the (de-)optimization of cobr
229    instructions into separate compare and branch instructions when a 13-bit
230    displacement won't hack it.
231  */
232 const relax_typeS md_relax_table[] =
233 {
234   {0, 0, 0, 0},			/* State 0 => no more relaxation possible */
235   {4088, -4096, 0, 2},		/* State 1: conditional branch (cobr) */
236   {0x800000 - 8, -0x800000, 4, 0},	/* State 2: compare (reg) & branch (ctrl) */
237 };
238 
239 static void s_endian PARAMS ((int));
240 
241 /* These are the machine dependent pseudo-ops.
242 
243    This table describes all the machine specific pseudo-ops the assembler
244    has to support.  The fields are:
245         pseudo-op name without dot
246         function to call to execute this pseudo-op
247         integer arg to pass to the function
248  */
249 #define S_LEAFPROC	1
250 #define S_SYSPROC	2
251 
252 const pseudo_typeS md_pseudo_table[] =
253 {
254   {"bss", s_lcomm, 1},
255   {"endian", s_endian, 0},
256   {"extended", float_cons, 't'},
257   {"leafproc", parse_po, S_LEAFPROC},
258   {"sysproc", parse_po, S_SYSPROC},
259 
260   {"word", cons, 4},
261   {"quad", cons, 16},
262 
263   {0, 0, 0}
264 };
265 
266 /* Macros to extract info from an 'expressionS' structure 'e' */
267 #define adds(e)	e.X_add_symbol
268 #define offs(e)	e.X_add_number
269 
270 /* Branch-prediction bits for CTRL/COBR format opcodes */
271 #define BP_MASK		0x00000002	/* Mask for branch-prediction bit */
272 #define BP_TAKEN	0x00000000	/* Value to OR in to predict branch */
273 #define BP_NOT_TAKEN	0x00000002	/* Value to OR in to predict no branch */
274 
275 /* Some instruction opcodes that we need explicitly */
276 #define BE	0x12000000
277 #define BG	0x11000000
278 #define BGE	0x13000000
279 #define BL	0x14000000
280 #define BLE	0x16000000
281 #define BNE	0x15000000
282 #define BNO	0x10000000
283 #define BO	0x17000000
284 #define CHKBIT	0x5a002700
285 #define CMPI	0x5a002080
286 #define CMPO	0x5a002000
287 
288 #define B	0x08000000
289 #define BAL	0x0b000000
290 #define CALL	0x09000000
291 #define CALLS	0x66003800
292 #define RET	0x0a000000
293 
294 /* These masks are used to build up a set of MEMB mode bits.  */
295 #define	A_BIT		0x0400
296 #define	I_BIT		0x0800
297 #define MEMB_BIT	0x1000
298 #define	D_BIT		0x2000
299 
300 /* Mask for the only mode bit in a MEMA instruction (if set, abase reg is
301    used).  */
302 #define MEMA_ABASE	0x2000
303 
304 /* Info from which a MEMA or MEMB format instruction can be generated */
305 typedef struct memS
306   {
307     /* (First) 32 bits of instruction */
308     long opcode;
309     /* 0-(none), 12- or, 32-bit displacement needed */
310     int disp;
311     /* The expression in the source instruction from which the
312        displacement should be determined.  */
313     char *e;
314   }
315 memS;
316 
317 /* The two pieces of info we need to generate a register operand */
318 struct regop
319   {
320     int mode;			/* 0 =>local/global/spec reg; 1=> literal or fp reg */
321     int special;		/* 0 =>not a sfr;  1=> is a sfr (not valid w/mode=0) */
322     int n;			/* Register number or literal value */
323   };
324 
325 /* Number and assembler mnemonic for all registers that can appear in
326    operands.  */
327 static const struct
328   {
329     char *reg_name;
330     int reg_num;
331   }
332 regnames[] =
333 {
334   { "pfp", 0 },
335   { "sp", 1 },
336   { "rip", 2 },
337   { "r3", 3 },
338   { "r4", 4 },
339   { "r5", 5 },
340   { "r6", 6 },
341   { "r7", 7 },
342   { "r8", 8 },
343   { "r9", 9 },
344   { "r10", 10 },
345   { "r11", 11 },
346   { "r12", 12 },
347   { "r13", 13 },
348   { "r14", 14 },
349   { "r15", 15 },
350   { "g0", 16 },
351   { "g1", 17 },
352   { "g2", 18 },
353   { "g3", 19 },
354   { "g4", 20 },
355   { "g5", 21 },
356   { "g6", 22 },
357   { "g7", 23 },
358   { "g8", 24 },
359   { "g9", 25 },
360   { "g10", 26 },
361   { "g11", 27 },
362   { "g12", 28 },
363   { "g13", 29 },
364   { "g14", 30 },
365   { "fp", 31 },
366 
367   /* Numbers for special-function registers are for assembler internal
368      use only: they are scaled back to range [0-31] for binary output.  */
369 #define SF0	32
370 
371   { "sf0", 32 },
372   { "sf1", 33 },
373   { "sf2", 34 },
374   { "sf3", 35 },
375   { "sf4", 36 },
376   { "sf5", 37 },
377   { "sf6", 38 },
378   { "sf7", 39 },
379   { "sf8", 40 },
380   { "sf9", 41 },
381   { "sf10", 42 },
382   { "sf11", 43 },
383   { "sf12", 44 },
384   { "sf13", 45 },
385   { "sf14", 46 },
386   { "sf15", 47 },
387   { "sf16", 48 },
388   { "sf17", 49 },
389   { "sf18", 50 },
390   { "sf19", 51 },
391   { "sf20", 52 },
392   { "sf21", 53 },
393   { "sf22", 54 },
394   { "sf23", 55 },
395   { "sf24", 56 },
396   { "sf25", 57 },
397   { "sf26", 58 },
398   { "sf27", 59 },
399   { "sf28", 60 },
400   { "sf29", 61 },
401   { "sf30", 62 },
402   { "sf31", 63 },
403 
404   /* Numbers for floating point registers are for assembler internal
405      use only: they are scaled back to [0-3] for binary output.  */
406 #define FP0	64
407 
408   { "fp0", 64 },
409   { "fp1", 65 },
410   { "fp2", 66 },
411   { "fp3", 67 },
412 
413   { NULL, 0 },				/* END OF LIST */
414 };
415 
416 #define	IS_RG_REG(n)	((0 <= (n)) && ((n) < SF0))
417 #define	IS_SF_REG(n)	((SF0 <= (n)) && ((n) < FP0))
418 #define	IS_FP_REG(n)	((n) >= FP0)
419 
420 /* Number and assembler mnemonic for all registers that can appear as
421    'abase' (indirect addressing) registers.  */
422 static const struct
423   {
424     char *areg_name;
425     int areg_num;
426   }
427 aregs[] =
428 {
429   { "(pfp)", 0 },
430   { "(sp)", 1 },
431   { "(rip)", 2 },
432   { "(r3)", 3 },
433   { "(r4)", 4 },
434   { "(r5)", 5 },
435   { "(r6)", 6 },
436   { "(r7)", 7 },
437   { "(r8)", 8 },
438   { "(r9)", 9 },
439   { "(r10)", 10 },
440   { "(r11)", 11 },
441   { "(r12)", 12 },
442   { "(r13)", 13 },
443   { "(r14)", 14 },
444   { "(r15)", 15 },
445   { "(g0)", 16 },
446   { "(g1)", 17 },
447   { "(g2)", 18 },
448   { "(g3)", 19 },
449   { "(g4)", 20 },
450   { "(g5)", 21 },
451   { "(g6)", 22 },
452   { "(g7)", 23 },
453   { "(g8)", 24 },
454   { "(g9)", 25 },
455   { "(g10)", 26 },
456   { "(g11)", 27 },
457   { "(g12)", 28 },
458   { "(g13)", 29 },
459   { "(g14)", 30 },
460   { "(fp)", 31 },
461 
462 #define IPREL	32
463   /* For assembler internal use only: this number never appears in binary
464      output.  */
465   { "(ip)", IPREL },
466 
467   { NULL, 0 },				/* END OF LIST */
468 };
469 
470 /* Hash tables */
471 static struct hash_control *op_hash;	/* Opcode mnemonics */
472 static struct hash_control *reg_hash;	/* Register name hash table */
473 static struct hash_control *areg_hash;	/* Abase register hash table */
474 
475 /* Architecture for which we are assembling */
476 #define ARCH_ANY	0	/* Default: no architecture checking done */
477 #define ARCH_KA		1
478 #define ARCH_KB		2
479 #define ARCH_MC		3
480 #define ARCH_CA		4
481 #define ARCH_JX		5
482 #define ARCH_HX		6
483 int architecture = ARCH_ANY;	/* Architecture requested on invocation line */
484 int iclasses_seen;		/* OR of instruction classes (I_* constants)
485 				 *    for which we've actually assembled
486 				 *      instructions.
487 				 */
488 
489 /* BRANCH-PREDICTION INSTRUMENTATION
490 
491         The following supports generation of branch-prediction instrumentation
492         (turned on by -b switch).  The instrumentation collects counts
493         of branches taken/not-taken for later input to a utility that will
494         set the branch prediction bits of the instructions in accordance with
495         the behavior observed.  (Note that the KX series does not have
496         brach-prediction.)
497 
498         The instrumentation consists of:
499 
500         (1) before and after each conditional branch, a call to an external
501             routine that increments and steps over an inline counter.  The
502             counter itself, initialized to 0, immediately follows the call
503             instruction.  For each branch, the counter following the branch
504             is the number of times the branch was not taken, and the difference
505             between the counters is the number of times it was taken.  An
506             example of an instrumented conditional branch:
507 
508                                 call    BR_CNT_FUNC
509                                 .word   0
510                 LBRANCH23:      be      label
511                                 call    BR_CNT_FUNC
512                                 .word   0
513 
514         (2) a table of pointers to the instrumented branches, so that an
515             external postprocessing routine can locate all of the counters.
516             the table begins with a 2-word header: a pointer to the next in
517             a linked list of such tables (initialized to 0);  and a count
518             of the number of entries in the table (exclusive of the header.
519 
520             Note that input source code is expected to already contain calls
521             an external routine that will link the branch local table into a
522             list of such tables.
523  */
524 
525 /* Number of branches instrumented so far.  Also used to generate
526    unique local labels for each instrumented branch.  */
527 static int br_cnt;
528 
529 #define BR_LABEL_BASE	"LBRANCH"
530 /* Basename of local labels on instrumented branches, to avoid
531    conflict with compiler- generated local labels.  */
532 
533 #define BR_CNT_FUNC	"__inc_branch"
534 /* Name of the external routine that will increment (and step over) an
535    inline counter.  */
536 
537 #define BR_TAB_NAME	"__BRANCH_TABLE__"
538 /* Name of the table of pointers to branches.  A local (i.e.,
539    non-external) symbol.  */
540 
541 /*****************************************************************************
542    md_begin:  One-time initialization.
543 
544   	Set up hash tables.
545 
546   *************************************************************************** */
547 void
md_begin()548 md_begin ()
549 {
550   int i;			/* Loop counter */
551   const struct i960_opcode *oP;	/* Pointer into opcode table */
552   const char *retval;		/* Value returned by hash functions */
553 
554   op_hash = hash_new ();
555   reg_hash = hash_new ();
556   areg_hash = hash_new ();
557 
558   /* For some reason, the base assembler uses an empty string for "no
559      error message", instead of a NULL pointer.  */
560   retval = 0;
561 
562   for (oP = i960_opcodes; oP->name && !retval; oP++)
563     retval = hash_insert (op_hash, oP->name, (PTR) oP);
564 
565   for (i = 0; regnames[i].reg_name && !retval; i++)
566     retval = hash_insert (reg_hash, regnames[i].reg_name,
567 			  (char *) &regnames[i].reg_num);
568 
569   for (i = 0; aregs[i].areg_name && !retval; i++)
570     retval = hash_insert (areg_hash, aregs[i].areg_name,
571 			  (char *) &aregs[i].areg_num);
572 
573   if (retval)
574     as_fatal (_("Hashing returned \"%s\"."), retval);
575 }
576 
577 /*****************************************************************************
578    md_assemble:  Assemble an instruction
579 
580    Assumptions about the passed-in text:
581   	- all comments, labels removed
582   	- text is an instruction
583   	- all white space compressed to single blanks
584   	- all character constants have been replaced with decimal
585 
586   *************************************************************************** */
587 void
md_assemble(textP)588 md_assemble (textP)
589      char *textP;		/* Source text of instruction */
590 {
591   /* Parsed instruction text, containing NO whitespace: arg[0]->opcode
592      mnemonic arg[1-3]->operands, with char constants replaced by
593      decimal numbers.  */
594   char *args[4];
595 
596   int n_ops;			/* Number of instruction operands */
597   /* Pointer to instruction description */
598   struct i960_opcode *oP;
599   /* TRUE iff opcode mnemonic included branch-prediction suffix (".f"
600      or ".t").  */
601   int branch_predict;
602   /* Setting of branch-prediction bit(s) to be OR'd into instruction
603      opcode of CTRL/COBR format instructions.  */
604   long bp_bits;
605 
606   int n;			/* Offset of last character in opcode mnemonic */
607 
608   const char *bp_error_msg = _("branch prediction invalid on this opcode");
609 
610   /* Parse instruction into opcode and operands */
611   memset (args, '\0', sizeof (args));
612   n_ops = i_scan (textP, args);
613   if (n_ops == -1)
614     {
615       return;			/* Error message already issued */
616     }
617 
618   /* Do "macro substitution" (sort of) on 'ldconst' pseudo-instruction */
619   if (!strcmp (args[0], "ldconst"))
620     {
621       n_ops = parse_ldconst (args);
622       if (n_ops == -1)
623 	{
624 	  return;
625 	}
626     }
627 
628   /* Check for branch-prediction suffix on opcode mnemonic, strip it off */
629   n = strlen (args[0]) - 1;
630   branch_predict = 0;
631   bp_bits = 0;
632   if (args[0][n - 1] == '.' && (args[0][n] == 't' || args[0][n] == 'f'))
633     {
634       /* We could check here to see if the target architecture
635 	 supports branch prediction, but why bother?  The bit will
636 	 just be ignored by processors that don't use it.  */
637       branch_predict = 1;
638       bp_bits = (args[0][n] == 't') ? BP_TAKEN : BP_NOT_TAKEN;
639       args[0][n - 1] = '\0';	/* Strip suffix from opcode mnemonic */
640     }
641 
642   /* Look up opcode mnemonic in table and check number of operands.
643      Check that opcode is legal for the target architecture.  If all
644      looks good, assemble instruction.  */
645   oP = (struct i960_opcode *) hash_find (op_hash, args[0]);
646   if (!oP || !targ_has_iclass (oP->iclass))
647     {
648       as_bad (_("invalid opcode, \"%s\"."), args[0]);
649 
650     }
651   else if (n_ops != oP->num_ops)
652     {
653       as_bad (_("improper number of operands.  expecting %d, got %d"),
654 	      oP->num_ops, n_ops);
655     }
656   else
657     {
658       switch (oP->format)
659 	{
660 	case FBRA:
661 	case CTRL:
662 	  ctrl_fmt (args[1], oP->opcode | bp_bits, oP->num_ops);
663 	  if (oP->format == FBRA)
664 	    {
665 	      /* Now generate a 'bno' to same arg */
666 	      ctrl_fmt (args[1], BNO | bp_bits, 1);
667 	    }
668 	  break;
669 	case COBR:
670 	case COJ:
671 	  cobr_fmt (args, oP->opcode | bp_bits, oP);
672 	  break;
673 	case REG:
674 	  if (branch_predict)
675 	    {
676 	      as_warn (bp_error_msg);
677 	    }
678 	  reg_fmt (args, oP);
679 	  break;
680 	case MEM1:
681 	  if (args[0][0] == 'c' && args[0][1] == 'a')
682 	    {
683 	      if (branch_predict)
684 		{
685 		  as_warn (bp_error_msg);
686 		}
687 	      mem_fmt (args, oP, 1);
688 	      break;
689 	    }
690 	case MEM2:
691 	case MEM4:
692 	case MEM8:
693 	case MEM12:
694 	case MEM16:
695 	  if (branch_predict)
696 	    {
697 	      as_warn (bp_error_msg);
698 	    }
699 	  mem_fmt (args, oP, 0);
700 	  break;
701 	case CALLJ:
702 	  if (branch_predict)
703 	    {
704 	      as_warn (bp_error_msg);
705 	    }
706 	  /* Output opcode & set up "fixup" (relocation); flag
707 	     relocation as 'callj' type.  */
708 	  know (oP->num_ops == 1);
709 	  get_cdisp (args[1], "CTRL", oP->opcode, 24, 0, 1);
710 	  break;
711 	default:
712 	  BAD_CASE (oP->format);
713 	  break;
714 	}
715     }
716 }				/* md_assemble() */
717 
718 /*****************************************************************************
719    md_number_to_chars:  convert a number to target byte order
720 
721   *************************************************************************** */
722 void
md_number_to_chars(buf,value,n)723 md_number_to_chars (buf, value, n)
724      char *buf;
725      valueT value;
726      int n;
727 {
728   number_to_chars_littleendian (buf, value, n);
729 }
730 
731 /*****************************************************************************
732    md_chars_to_number:  convert from target byte order to host byte order.
733 
734   *************************************************************************** */
735 static int md_chars_to_number PARAMS ((unsigned char *, int));
736 
737 static int
md_chars_to_number(val,n)738 md_chars_to_number (val, n)
739      unsigned char *val;	/* Value in target byte order */
740      int n;			/* Number of bytes in the input */
741 {
742   int retval;
743 
744   for (retval = 0; n--;)
745     {
746       retval <<= 8;
747       retval |= val[n];
748     }
749   return retval;
750 }
751 
752 #define MAX_LITTLENUMS	6
753 #define LNUM_SIZE	sizeof (LITTLENUM_TYPE)
754 
755 /*****************************************************************************
756    md_atof:	convert ascii to floating point
757 
758    Turn a string at input_line_pointer into a floating point constant of type
759    'type', and store the appropriate bytes at *litP.  The number of LITTLENUMS
760    emitted is returned at 'sizeP'.  An error message is returned, or a pointer
761    to an empty message if OK.
762 
763    Note we call the i386 floating point routine, rather than complicating
764    things with more files or symbolic links.
765 
766   *************************************************************************** */
767 char *
md_atof(type,litP,sizeP)768 md_atof (type, litP, sizeP)
769      int type;
770      char *litP;
771      int *sizeP;
772 {
773   LITTLENUM_TYPE words[MAX_LITTLENUMS];
774   LITTLENUM_TYPE *wordP;
775   int prec;
776   char *t;
777 
778   switch (type)
779     {
780     case 'f':
781     case 'F':
782       prec = 2;
783       break;
784 
785     case 'd':
786     case 'D':
787       prec = 4;
788       break;
789 
790     case 't':
791     case 'T':
792       prec = 5;
793       type = 'x';		/* That's what atof_ieee() understands */
794       break;
795 
796     default:
797       *sizeP = 0;
798       return _("Bad call to md_atof()");
799     }
800 
801   t = atof_ieee (input_line_pointer, type, words);
802   if (t)
803     {
804       input_line_pointer = t;
805     }
806 
807   *sizeP = prec * LNUM_SIZE;
808 
809   /* Output the LITTLENUMs in REVERSE order in accord with i80960
810      word-order.  (Dunno why atof_ieee doesn't do it in the right
811      order in the first place -- probably because it's a hack of
812      atof_m68k.)  */
813 
814   for (wordP = words + prec - 1; prec--;)
815     {
816       md_number_to_chars (litP, (long) (*wordP--), LNUM_SIZE);
817       litP += sizeof (LITTLENUM_TYPE);
818     }
819 
820   return 0;
821 }
822 
823 /*****************************************************************************
824    md_number_to_imm
825 
826   *************************************************************************** */
827 static void md_number_to_imm PARAMS ((char *, long, int));
828 
829 static void
md_number_to_imm(buf,val,n)830 md_number_to_imm (buf, val, n)
831      char *buf;
832      long val;
833      int n;
834 {
835   md_number_to_chars (buf, val, n);
836 }
837 
838 /*****************************************************************************
839    md_number_to_field:
840 
841   	Stick a value (an address fixup) into a bit field of
842   	previously-generated instruction.
843 
844   *************************************************************************** */
845 static void md_number_to_field PARAMS ((char *, long, bit_fixS *));
846 
847 static void
md_number_to_field(instrP,val,bfixP)848 md_number_to_field (instrP, val, bfixP)
849      char *instrP;		/* Pointer to instruction to be fixed */
850      long val;			/* Address fixup value */
851      bit_fixS *bfixP;		/* Description of bit field to be fixed up */
852 {
853   int numbits;			/* Length of bit field to be fixed */
854   long instr;			/* 32-bit instruction to be fixed-up */
855   long sign;			/* 0 or -1, according to sign bit of 'val' */
856 
857   /* Convert instruction back to host byte order.  */
858   instr = md_chars_to_number (instrP, 4);
859 
860   /* Surprise! -- we stored the number of bits to be modified rather
861      than a pointer to a structure.  */
862   numbits = (int) bfixP;
863   if (numbits == 1)
864     {
865       /* This is a no-op, stuck here by reloc_callj() */
866       return;
867     }
868 
869   know ((numbits == 13) || (numbits == 24));
870 
871   /* Propagate sign bit of 'val' for the given number of bits.  Result
872      should be all 0 or all 1.  */
873   sign = val >> ((int) numbits - 1);
874   if (((val < 0) && (sign != -1))
875       || ((val > 0) && (sign != 0)))
876     {
877       as_bad (_("Fixup of %ld too large for field width of %d"),
878 	      val, numbits);
879     }
880   else
881     {
882       /* Put bit field into instruction and write back in target
883          * byte order.
884        */
885       val &= ~(-1 << (int) numbits);	/* Clear unused sign bits */
886       instr |= val;
887       md_number_to_chars (instrP, instr, 4);
888     }
889 }				/* md_number_to_field() */
890 
891 
892 /*****************************************************************************
893    md_parse_option
894   	Invocation line includes a switch not recognized by the base assembler.
895   	See if it's a processor-specific option.  For the 960, these are:
896 
897   	-norelax:
898   		Conditional branch instructions that require displacements
899   		greater than 13 bits (or that have external targets) should
900   		generate errors.  The default is to replace each such
901   		instruction with the corresponding compare (or chkbit) and
902   		branch instructions.  Note that the Intel "j" cobr directives
903   		are ALWAYS "de-optimized" in this way when necessary,
904   		regardless of the setting of this option.
905 
906   	-b:
907   		Add code to collect information about branches taken, for
908   		later optimization of branch prediction bits by a separate
909   		tool.  COBR and CNTL format instructions have branch
910   		prediction bits (in the CX architecture);  if "BR" represents
911   		an instruction in one of these classes, the following rep-
912   		resents the code generated by the assembler:
913 
914   			call	<increment routine>
915   			.word	0	# pre-counter
916   		Label:  BR
917   			call	<increment routine>
918   			.word	0	# post-counter
919 
920   		A table of all such "Labels" is also generated.
921 
922   	-AKA, -AKB, -AKC, -ASA, -ASB, -AMC, -ACA:
923   		Select the 80960 architecture.  Instructions or features not
924   		supported by the selected architecture cause fatal errors.
925   		The default is to generate code for any instruction or feature
926   		that is supported by SOME version of the 960 (even if this
927   		means mixing architectures!).
928 
929   ****************************************************************************/
930 
931 const char *md_shortopts = "A:b";
932 struct option md_longopts[] =
933 {
934 #define OPTION_LINKRELAX (OPTION_MD_BASE)
935   {"linkrelax", no_argument, NULL, OPTION_LINKRELAX},
936   {"link-relax", no_argument, NULL, OPTION_LINKRELAX},
937 #define OPTION_NORELAX (OPTION_MD_BASE + 1)
938   {"norelax", no_argument, NULL, OPTION_NORELAX},
939   {"no-relax", no_argument, NULL, OPTION_NORELAX},
940   {NULL, no_argument, NULL, 0}
941 };
942 size_t md_longopts_size = sizeof (md_longopts);
943 
944 struct tabentry
945   {
946     char *flag;
947     int arch;
948   };
949 static const struct tabentry arch_tab[] =
950 {
951   {"KA", ARCH_KA},
952   {"KB", ARCH_KB},
953   {"SA", ARCH_KA},		/* Synonym for KA */
954   {"SB", ARCH_KB},		/* Synonym for KB */
955   {"KC", ARCH_MC},		/* Synonym for MC */
956   {"MC", ARCH_MC},
957   {"CA", ARCH_CA},
958   {"JX", ARCH_JX},
959   {"HX", ARCH_HX},
960   {NULL, 0}
961 };
962 
963 int
md_parse_option(c,arg)964 md_parse_option (c, arg)
965      int c;
966      char *arg;
967 {
968   switch (c)
969     {
970     case OPTION_LINKRELAX:
971       linkrelax = 1;
972       flag_keep_locals = 1;
973       break;
974 
975     case OPTION_NORELAX:
976       norelax = 1;
977       break;
978 
979     case 'b':
980       instrument_branches = 1;
981       break;
982 
983     case 'A':
984       {
985 	const struct tabentry *tp;
986 	char *p = arg;
987 
988 	for (tp = arch_tab; tp->flag != NULL; tp++)
989 	  if (!strcmp (p, tp->flag))
990 	    break;
991 
992 	if (tp->flag == NULL)
993 	  {
994 	    as_bad (_("invalid architecture %s"), p);
995 	    return 0;
996 	  }
997 	else
998 	  architecture = tp->arch;
999       }
1000       break;
1001 
1002     default:
1003       return 0;
1004     }
1005 
1006   return 1;
1007 }
1008 
1009 void
md_show_usage(stream)1010 md_show_usage (stream)
1011      FILE *stream;
1012 {
1013   int i;
1014   fprintf (stream, _("I960 options:\n"));
1015   for (i = 0; arch_tab[i].flag; i++)
1016     fprintf (stream, "%s-A%s", i ? " | " : "", arch_tab[i].flag);
1017   fprintf (stream, _("\n\
1018 			specify variant of 960 architecture\n\
1019 -b			add code to collect statistics about branches taken\n\
1020 -link-relax		preserve individual alignment directives so linker\n\
1021 			can do relaxing (b.out format only)\n\
1022 -no-relax		don't alter compare-and-branch instructions for\n\
1023 			long displacements\n"));
1024 }
1025 
1026 
1027 /*****************************************************************************
1028    md_convert_frag:
1029   	Called by base assembler after address relaxation is finished:  modify
1030   	variable fragments according to how much relaxation was done.
1031 
1032   	If the fragment substate is still 1, a 13-bit displacement was enough
1033   	to reach the symbol in question.  Set up an address fixup, but otherwise
1034   	leave the cobr instruction alone.
1035 
1036   	If the fragment substate is 2, a 13-bit displacement was not enough.
1037   	Replace the cobr with a two instructions (a compare and a branch).
1038 
1039   *************************************************************************** */
1040 #ifndef BFD_ASSEMBLER
1041 void
md_convert_frag(headers,seg,fragP)1042 md_convert_frag (headers, seg, fragP)
1043      object_headers *headers ATTRIBUTE_UNUSED;
1044      segT seg ATTRIBUTE_UNUSED;
1045      fragS *fragP;
1046 #else
1047 void
1048 md_convert_frag (abfd, sec, fragP)
1049      bfd *abfd ATTRIBUTE_UNUSED;
1050      segT sec ATTRIBUTE_UNUSED;
1051      fragS *fragP;
1052 #endif
1053 {
1054   fixS *fixP;			/* Structure describing needed address fix */
1055 
1056   switch (fragP->fr_subtype)
1057     {
1058     case 1:
1059       /* LEAVE SINGLE COBR INSTRUCTION */
1060       fixP = fix_new (fragP,
1061 		      fragP->fr_opcode - fragP->fr_literal,
1062 		      4,
1063 		      fragP->fr_symbol,
1064 		      fragP->fr_offset,
1065 		      1,
1066 		      NO_RELOC);
1067 
1068       fixP->fx_bit_fixP = (bit_fixS *) 13;	/* size of bit field */
1069       break;
1070     case 2:
1071       /* REPLACE COBR WITH COMPARE/BRANCH INSTRUCTIONS */
1072       relax_cobr (fragP);
1073       break;
1074     default:
1075       BAD_CASE (fragP->fr_subtype);
1076       break;
1077     }
1078 }
1079 
1080 /*****************************************************************************
1081    md_estimate_size_before_relax:  How much does it look like *fragP will grow?
1082 
1083   	Called by base assembler just before address relaxation.
1084   	Return the amount by which the fragment will grow.
1085 
1086   	Any symbol that is now undefined will not become defined; cobr's
1087   	based on undefined symbols will have to be replaced with a compare
1088   	instruction and a branch instruction, and the code fragment will grow
1089   	by 4 bytes.
1090 
1091   *************************************************************************** */
1092 int
md_estimate_size_before_relax(fragP,segment_type)1093 md_estimate_size_before_relax (fragP, segment_type)
1094      register fragS *fragP;
1095      register segT segment_type;
1096 {
1097   /* If symbol is undefined in this segment, go to "relaxed" state
1098      (compare and branch instructions instead of cobr) right now.  */
1099   if (S_GET_SEGMENT (fragP->fr_symbol) != segment_type)
1100     {
1101       relax_cobr (fragP);
1102       return 4;
1103     }
1104 
1105   return md_relax_table[fragP->fr_subtype].rlx_length;
1106 }				/* md_estimate_size_before_relax() */
1107 
1108 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
1109 
1110 /*****************************************************************************
1111    md_ri_to_chars:
1112   	This routine exists in order to overcome machine byte-order problems
1113   	when dealing with bit-field entries in the relocation_info struct.
1114 
1115   	But relocation info will be used on the host machine only (only
1116   	executable code is actually downloaded to the i80960).  Therefore,
1117   	we leave it in host byte order.
1118 
1119   	The above comment is no longer true.  This routine now really
1120   	does do the reordering (Ian Taylor 28 Aug 92).
1121 
1122   *************************************************************************** */
1123 static void md_ri_to_chars PARAMS ((char *, struct relocation_info *));
1124 
1125 static void
md_ri_to_chars(where,ri)1126 md_ri_to_chars (where, ri)
1127      char *where;
1128      struct relocation_info *ri;
1129 {
1130   md_number_to_chars (where, ri->r_address,
1131 		      sizeof (ri->r_address));
1132   where[4] = ri->r_index & 0x0ff;
1133   where[5] = (ri->r_index >> 8) & 0x0ff;
1134   where[6] = (ri->r_index >> 16) & 0x0ff;
1135   where[7] = ((ri->r_pcrel << 0)
1136 	      | (ri->r_length << 1)
1137 	      | (ri->r_extern << 3)
1138 	      | (ri->r_bsr << 4)
1139 	      | (ri->r_disp << 5)
1140 	      | (ri->r_callj << 6));
1141 }
1142 
1143 #endif /* defined(OBJ_AOUT) | defined(OBJ_BOUT) */
1144 
1145 
1146 /* FOLLOWING ARE THE LOCAL ROUTINES, IN ALPHABETICAL ORDER  */
1147 
1148 /*****************************************************************************
1149    brcnt_emit:	Emit code to increment inline branch counter.
1150 
1151   	See the comments above the declaration of 'br_cnt' for details on
1152   	branch-prediction instrumentation.
1153   *************************************************************************** */
1154 static void
brcnt_emit()1155 brcnt_emit ()
1156 {
1157   ctrl_fmt (BR_CNT_FUNC, CALL, 1);	/* Emit call to "increment" routine */
1158   emit (0);			/* Emit inline counter to be incremented */
1159 }
1160 
1161 /*****************************************************************************
1162    brlab_next:	generate the next branch local label
1163 
1164   	See the comments above the declaration of 'br_cnt' for details on
1165   	branch-prediction instrumentation.
1166   *************************************************************************** */
1167 static char *
brlab_next()1168 brlab_next ()
1169 {
1170   static char buf[20];
1171 
1172   sprintf (buf, "%s%d", BR_LABEL_BASE, br_cnt++);
1173   return buf;
1174 }
1175 
1176 /*****************************************************************************
1177    brtab_emit:	generate the fetch-prediction branch table.
1178 
1179   	See the comments above the declaration of 'br_cnt' for details on
1180   	branch-prediction instrumentation.
1181 
1182   	The code emitted here would be functionally equivalent to the following
1183   	example assembler source.
1184 
1185   			.data
1186   			.align	2
1187   	   BR_TAB_NAME:
1188   			.word	0		# link to next table
1189   			.word	3		# length of table
1190   			.word	LBRANCH0	# 1st entry in table proper
1191   			.word	LBRANCH1
1192   			.word	LBRANCH2
1193   **************************************************************************** */
1194 void
brtab_emit()1195 brtab_emit ()
1196 {
1197   int i;
1198   char buf[20];
1199   char *p;			/* Where the binary was output to */
1200   /* Pointer to description of deferred address fixup.  */
1201   fixS *fixP;
1202 
1203   if (!instrument_branches)
1204     {
1205       return;
1206     }
1207 
1208   subseg_set (data_section, 0);	/*      .data */
1209   frag_align (2, 0, 0);		/*      .align 2 */
1210   record_alignment (now_seg, 2);
1211   colon (BR_TAB_NAME);		/* BR_TAB_NAME: */
1212   emit (0);			/*      .word 0 #link to next table */
1213   emit (br_cnt);		/*      .word n #length of table */
1214 
1215   for (i = 0; i < br_cnt; i++)
1216     {
1217       sprintf (buf, "%s%d", BR_LABEL_BASE, i);
1218       p = emit (0);
1219       fixP = fix_new (frag_now,
1220 		      p - frag_now->fr_literal,
1221 		      4,
1222 		      symbol_find (buf),
1223 		      0,
1224 		      0,
1225 		      NO_RELOC);
1226     }
1227 }
1228 
1229 /*****************************************************************************
1230    cobr_fmt:	generate a COBR-format instruction
1231 
1232   *************************************************************************** */
1233 static void
cobr_fmt(arg,opcode,oP)1234 cobr_fmt (arg, opcode, oP)
1235      /* arg[0]->opcode mnemonic, arg[1-3]->operands (ascii) */
1236      char *arg[];
1237      /* Opcode, with branch-prediction bits already set if necessary.  */
1238      long opcode;
1239      /* Pointer to description of instruction.  */
1240      struct i960_opcode *oP;
1241 {
1242   long instr;			/* 32-bit instruction */
1243   struct regop regop;		/* Description of register operand */
1244   int n;			/* Number of operands */
1245   int var_frag;			/* 1 if varying length code fragment should
1246 				 *    be emitted;  0 if an address fix
1247 				 *      should be emitted.
1248 				 */
1249 
1250   instr = opcode;
1251   n = oP->num_ops;
1252 
1253   if (n >= 1)
1254     {
1255       /* First operand (if any) of a COBR is always a register
1256 	 operand.  Parse it.  */
1257       parse_regop (&regop, arg[1], oP->operand[0]);
1258       instr |= (regop.n << 19) | (regop.mode << 13);
1259     }
1260   if (n >= 2)
1261     {
1262       /* Second operand (if any) of a COBR is always a register
1263 	 operand.  Parse it.  */
1264     parse_regop (&regop, arg[2], oP->operand[1]);
1265       instr |= (regop.n << 14) | regop.special;
1266     }
1267 
1268   if (n < 3)
1269     {
1270       emit (instr);
1271 
1272     }
1273   else
1274     {
1275       if (instrument_branches)
1276 	{
1277 	  brcnt_emit ();
1278 	  colon (brlab_next ());
1279 	}
1280 
1281       /* A third operand to a COBR is always a displacement.  Parse
1282          it; if it's relaxable (a cobr "j" directive, or any cobr
1283          other than bbs/bbc when the "-norelax" option is not in use)
1284          set up a variable code fragment; otherwise set up an address
1285          fix.  */
1286       var_frag = !norelax || (oP->format == COJ);	/* TRUE or FALSE */
1287       get_cdisp (arg[3], "COBR", instr, 13, var_frag, 0);
1288 
1289       if (instrument_branches)
1290 	{
1291 	  brcnt_emit ();
1292 	}
1293     }
1294 }				/* cobr_fmt() */
1295 
1296 /*****************************************************************************
1297    ctrl_fmt:	generate a CTRL-format instruction
1298 
1299   *************************************************************************** */
1300 static void
ctrl_fmt(targP,opcode,num_ops)1301 ctrl_fmt (targP, opcode, num_ops)
1302      char *targP;		/* Pointer to text of lone operand (if any) */
1303      long opcode;		/* Template of instruction */
1304      int num_ops;		/* Number of operands */
1305 {
1306   int instrument;		/* TRUE iff we should add instrumentation to track
1307 				   * how often the branch is taken
1308 				 */
1309 
1310   if (num_ops == 0)
1311     {
1312       emit (opcode);		/* Output opcode */
1313     }
1314   else
1315     {
1316 
1317       instrument = instrument_branches && (opcode != CALL)
1318 	&& (opcode != B) && (opcode != RET) && (opcode != BAL);
1319 
1320       if (instrument)
1321 	{
1322 	  brcnt_emit ();
1323 	  colon (brlab_next ());
1324 	}
1325 
1326       /* The operand MUST be an ip-relative displacement. Parse it
1327          * and set up address fix for the instruction we just output.
1328        */
1329       get_cdisp (targP, "CTRL", opcode, 24, 0, 0);
1330 
1331       if (instrument)
1332 	{
1333 	  brcnt_emit ();
1334 	}
1335     }
1336 
1337 }
1338 
1339 /*****************************************************************************
1340    emit:	output instruction binary
1341 
1342   	Output instruction binary, in target byte order, 4 bytes at a time.
1343   	Return pointer to where it was placed.
1344 
1345   *************************************************************************** */
1346 static char *
emit(instr)1347 emit (instr)
1348      long instr;		/* Word to be output, host byte order */
1349 {
1350   char *toP;			/* Where to output it */
1351 
1352   toP = frag_more (4);		/* Allocate storage */
1353   md_number_to_chars (toP, instr, 4);	/* Convert to target byte order */
1354   return toP;
1355 }
1356 
1357 /*****************************************************************************
1358    get_args:	break individual arguments out of comma-separated list
1359 
1360    Input assumptions:
1361   	- all comments and labels have been removed
1362   	- all strings of whitespace have been collapsed to a single blank.
1363   	- all character constants ('x') have been replaced with decimal
1364 
1365    Output:
1366   	args[0] is untouched. args[1] points to first operand, etc. All args:
1367   	- are NULL-terminated
1368   	- contain no whitespace
1369 
1370    Return value:
1371   	Number of operands (0,1,2, or 3) or -1 on error.
1372 
1373   *************************************************************************** */
1374 static int
get_args(p,args)1375 get_args (p, args)
1376      /* Pointer to comma-separated operands; MUCKED BY US */
1377      register char *p;
1378      /* Output arg: pointers to operands placed in args[1-3].  MUST
1379         ACCOMMODATE 4 ENTRIES (args[0-3]).  */
1380      char *args[];
1381 {
1382   register int n;		/* Number of operands */
1383   register char *to;
1384 
1385   /* Skip lead white space */
1386   while (*p == ' ')
1387     {
1388       p++;
1389     }
1390 
1391   if (*p == '\0')
1392     {
1393       return 0;
1394     }
1395 
1396   n = 1;
1397   args[1] = p;
1398 
1399   /* Squeze blanks out by moving non-blanks toward start of string.
1400      * Isolate operands, whenever comma is found.
1401    */
1402   to = p;
1403   while (*p != '\0')
1404     {
1405 
1406       if (*p == ' '
1407 	  && (! ISALNUM (p[1])
1408 	      || ! ISALNUM (p[-1])))
1409 	{
1410 	  p++;
1411 
1412 	}
1413       else if (*p == ',')
1414 	{
1415 
1416 	  /* Start of operand */
1417 	  if (n == 3)
1418 	    {
1419 	      as_bad (_("too many operands"));
1420 	      return -1;
1421 	    }
1422 	  *to++ = '\0';		/* Terminate argument */
1423 	  args[++n] = to;	/* Start next argument */
1424 	  p++;
1425 
1426 	}
1427       else
1428 	{
1429 	  *to++ = *p++;
1430 	}
1431     }
1432   *to = '\0';
1433   return n;
1434 }
1435 
1436 /*****************************************************************************
1437    get_cdisp:	handle displacement for a COBR or CTRL instruction.
1438 
1439   	Parse displacement for a COBR or CTRL instruction.
1440 
1441   	If successful, output the instruction opcode and set up for it,
1442   	depending on the arg 'var_frag', either:
1443   	    o an address fixup to be done when all symbol values are known, or
1444   	    o a varying length code fragment, with address fixup info.  This
1445   		will be done for cobr instructions that may have to be relaxed
1446   		in to compare/branch instructions (8 bytes) if the final
1447   		address displacement is greater than 13 bits.
1448 
1449   ****************************************************************************/
1450 static void
get_cdisp(dispP,ifmtP,instr,numbits,var_frag,callj)1451 get_cdisp (dispP, ifmtP, instr, numbits, var_frag, callj)
1452      /* displacement as specified in source instruction */
1453      char *dispP;
1454      /* "COBR" or "CTRL" (for use in error message) */
1455      char *ifmtP;
1456      /* Instruction needing the displacement */
1457      long instr;
1458      /* # bits of displacement (13 for COBR, 24 for CTRL) */
1459      int numbits;
1460      /* 1 if varying length code fragment should be emitted;
1461       *       0 if an address fix should be emitted.
1462       */
1463      int var_frag;
1464      /* 1 if callj relocation should be done; else 0 */
1465      int callj;
1466 {
1467   expressionS e;		/* Parsed expression */
1468   fixS *fixP;			/* Structure describing needed address fix */
1469   char *outP;			/* Where instruction binary is output to */
1470 
1471   fixP = NULL;
1472 
1473   parse_expr (dispP, &e);
1474   switch (e.X_op)
1475     {
1476     case O_illegal:
1477       as_bad (_("expression syntax error"));
1478 
1479     case O_symbol:
1480       if (S_GET_SEGMENT (e.X_add_symbol) == now_seg
1481 	  || S_GET_SEGMENT (e.X_add_symbol) == undefined_section)
1482 	{
1483 	  if (var_frag)
1484 	    {
1485 	      outP = frag_more (8);	/* Allocate worst-case storage */
1486 	      md_number_to_chars (outP, instr, 4);
1487 	      frag_variant (rs_machine_dependent, 4, 4, 1,
1488 			    adds (e), offs (e), outP);
1489 	    }
1490 	  else
1491 	    {
1492 	      /* Set up a new fix structure, so address can be updated
1493 	       * when all symbol values are known.
1494 	       */
1495 	      outP = emit (instr);
1496 	      fixP = fix_new (frag_now,
1497 			      outP - frag_now->fr_literal,
1498 			      4,
1499 			      adds (e),
1500 			      offs (e),
1501 			      1,
1502 			      NO_RELOC);
1503 
1504 	      fixP->fx_tcbit = callj;
1505 
1506 	      /* We want to modify a bit field when the address is
1507 	       * known.  But we don't need all the garbage in the
1508 	       * bit_fix structure.  So we're going to lie and store
1509 	       * the number of bits affected instead of a pointer.
1510 	       */
1511 	      fixP->fx_bit_fixP = (bit_fixS *) numbits;
1512 	    }
1513 	}
1514       else
1515 	as_bad (_("attempt to branch into different segment"));
1516       break;
1517 
1518     default:
1519       as_bad (_("target of %s instruction must be a label"), ifmtP);
1520       break;
1521     }
1522 }
1523 
1524 /*****************************************************************************
1525    get_ispec:	parse a memory operand for an index specification
1526 
1527   	Here, an "index specification" is taken to be anything surrounded
1528   	by square brackets and NOT followed by anything else.
1529 
1530   	If it's found, detach it from the input string, remove the surrounding
1531   	square brackets, and return a pointer to it.  Otherwise, return NULL.
1532 
1533   *************************************************************************** */
1534 static char *
get_ispec(textP)1535 get_ispec (textP)
1536      /* Pointer to memory operand from source instruction, no white space.  */
1537      char *textP;
1538 {
1539   /* Points to start of index specification.  */
1540   char *start;
1541   /* Points to end of index specification.  */
1542   char *end;
1543 
1544   /* Find opening square bracket, if any.  */
1545   start = strchr (textP, '[');
1546 
1547   if (start != NULL)
1548     {
1549 
1550       /* Eliminate '[', detach from rest of operand */
1551       *start++ = '\0';
1552 
1553       end = strchr (start, ']');
1554 
1555       if (end == NULL)
1556 	{
1557 	  as_bad (_("unmatched '['"));
1558 
1559 	}
1560       else
1561 	{
1562 	  /* Eliminate ']' and make sure it was the last thing
1563 	     * in the string.
1564 	   */
1565 	  *end = '\0';
1566 	  if (*(end + 1) != '\0')
1567 	    {
1568 	      as_bad (_("garbage after index spec ignored"));
1569 	    }
1570 	}
1571     }
1572   return start;
1573 }
1574 
1575 /*****************************************************************************
1576    get_regnum:
1577 
1578   	Look up a (suspected) register name in the register table and return the
1579   	associated register number (or -1 if not found).
1580 
1581   *************************************************************************** */
1582 static int
get_regnum(regname)1583 get_regnum (regname)
1584      char *regname;		/* Suspected register name */
1585 {
1586   int *rP;
1587 
1588   rP = (int *) hash_find (reg_hash, regname);
1589   return (rP == NULL) ? -1 : *rP;
1590 }
1591 
1592 /*****************************************************************************
1593    i_scan:	perform lexical scan of ascii assembler instruction.
1594 
1595    Input assumptions:
1596   	- input string is an i80960 instruction (not a pseudo-op)
1597   	- all comments and labels have been removed
1598   	- all strings of whitespace have been collapsed to a single blank.
1599 
1600    Output:
1601   	args[0] points to opcode, other entries point to operands. All strings:
1602   	- are NULL-terminated
1603   	- contain no whitespace
1604   	- have character constants ('x') replaced with a decimal number
1605 
1606    Return value:
1607   	Number of operands (0,1,2, or 3) or -1 on error.
1608 
1609   *************************************************************************** */
1610 static int
i_scan(iP,args)1611 i_scan (iP, args)
1612      /* Pointer to ascii instruction;  MUCKED BY US.  */
1613      register char *iP;
1614      /* Output arg: pointers to opcode and operands placed here.  MUST
1615 	ACCOMMODATE 4 ENTRIES.  */
1616      char *args[];
1617 {
1618 
1619   /* Isolate opcode */
1620   if (*(iP) == ' ')
1621     {
1622       iP++;
1623     }				/* Skip lead space, if any */
1624   args[0] = iP;
1625   for (; *iP != ' '; iP++)
1626     {
1627       if (*iP == '\0')
1628 	{
1629 	  /* There are no operands */
1630 	  if (args[0] == iP)
1631 	    {
1632 	      /* We never moved: there was no opcode either! */
1633 	      as_bad (_("missing opcode"));
1634 	      return -1;
1635 	    }
1636 	  return 0;
1637 	}
1638     }
1639   *iP++ = '\0';			/* Terminate opcode */
1640   return (get_args (iP, args));
1641 }				/* i_scan() */
1642 
1643 /*****************************************************************************
1644    mem_fmt:	generate a MEMA- or MEMB-format instruction
1645 
1646   *************************************************************************** */
1647 static void
mem_fmt(args,oP,callx)1648 mem_fmt (args, oP, callx)
1649      char *args[];		/* args[0]->opcode mnemonic, args[1-3]->operands */
1650      struct i960_opcode *oP;	/* Pointer to description of instruction */
1651      int callx;			/* Is this a callx opcode */
1652 {
1653   int i;			/* Loop counter */
1654   struct regop regop;		/* Description of register operand */
1655   char opdesc;			/* Operand descriptor byte */
1656   memS instr;			/* Description of binary to be output */
1657   char *outP;			/* Where the binary was output to */
1658   expressionS expr;		/* Parsed expression */
1659   /* ->description of deferred address fixup */
1660   fixS *fixP;
1661 
1662 #ifdef OBJ_COFF
1663   /* COFF support isn't in place yet for callx relaxing.  */
1664   callx = 0;
1665 #endif
1666 
1667   memset (&instr, '\0', sizeof (memS));
1668   instr.opcode = oP->opcode;
1669 
1670   /* Process operands.  */
1671   for (i = 1; i <= oP->num_ops; i++)
1672     {
1673       opdesc = oP->operand[i - 1];
1674 
1675       if (MEMOP (opdesc))
1676 	{
1677 	  parse_memop (&instr, args[i], oP->format);
1678 	}
1679       else
1680 	{
1681 	  parse_regop (&regop, args[i], opdesc);
1682 	  instr.opcode |= regop.n << 19;
1683 	}
1684     }
1685 
1686   /* Parse the displacement; this must be done before emitting the
1687      opcode, in case it is an expression using `.'.  */
1688   parse_expr (instr.e, &expr);
1689 
1690   /* Output opcode */
1691   outP = emit (instr.opcode);
1692 
1693   if (instr.disp == 0)
1694     {
1695       return;
1696     }
1697 
1698   /* Process the displacement */
1699   switch (expr.X_op)
1700     {
1701     case O_illegal:
1702       as_bad (_("expression syntax error"));
1703       break;
1704 
1705     case O_constant:
1706       if (instr.disp == 32)
1707 	{
1708 	  (void) emit (offs (expr));	/* Output displacement */
1709 	}
1710       else
1711 	{
1712 	  /* 12-bit displacement */
1713 	  if (offs (expr) & ~0xfff)
1714 	    {
1715 	      /* Won't fit in 12 bits: convert already-output
1716 	       * instruction to MEMB format, output
1717 	       * displacement.
1718 	       */
1719 	      mema_to_memb (outP);
1720 	      (void) emit (offs (expr));
1721 	    }
1722 	  else
1723 	    {
1724 	      /* WILL fit in 12 bits:  OR into opcode and
1725 	       * overwrite the binary we already put out
1726 	       */
1727 	      instr.opcode |= offs (expr);
1728 	      md_number_to_chars (outP, instr.opcode, 4);
1729 	    }
1730 	}
1731       break;
1732 
1733     default:
1734       if (instr.disp == 12)
1735 	{
1736 	  /* Displacement is dependent on a symbol, whose value
1737 	   * may change at link time.  We HAVE to reserve 32 bits.
1738 	   * Convert already-output opcode to MEMB format.
1739 	   */
1740 	  mema_to_memb (outP);
1741 	}
1742 
1743       /* Output 0 displacement and set up address fixup for when
1744        * this symbol's value becomes known.
1745        */
1746       outP = emit ((long) 0);
1747       fixP = fix_new_exp (frag_now,
1748 			  outP - frag_now->fr_literal,
1749 			  4,
1750 			  &expr,
1751 			  0,
1752 			  NO_RELOC);
1753       /* Steve's linker relaxing hack.  Mark this 32-bit relocation as
1754          being in the instruction stream, specifically as part of a callx
1755          instruction.  */
1756       fixP->fx_bsr = callx;
1757       break;
1758     }
1759 }				/* memfmt() */
1760 
1761 /*****************************************************************************
1762    mema_to_memb:	convert a MEMA-format opcode to a MEMB-format opcode.
1763 
1764    There are 2 possible MEMA formats:
1765   	- displacement only
1766   	- displacement + abase
1767 
1768    They are distinguished by the setting of the MEMA_ABASE bit.
1769 
1770   *************************************************************************** */
1771 static void
mema_to_memb(opcodeP)1772 mema_to_memb (opcodeP)
1773      char *opcodeP;		/* Where to find the opcode, in target byte order */
1774 {
1775   long opcode;			/* Opcode in host byte order */
1776   long mode;			/* Mode bits for MEMB instruction */
1777 
1778   opcode = md_chars_to_number (opcodeP, 4);
1779   know (!(opcode & MEMB_BIT));
1780 
1781   mode = MEMB_BIT | D_BIT;
1782   if (opcode & MEMA_ABASE)
1783     {
1784       mode |= A_BIT;
1785     }
1786 
1787   opcode &= 0xffffc000;		/* Clear MEMA offset and mode bits */
1788   opcode |= mode;		/* Set MEMB mode bits */
1789 
1790   md_number_to_chars (opcodeP, opcode, 4);
1791 }				/* mema_to_memb() */
1792 
1793 /*****************************************************************************
1794    parse_expr:		parse an expression
1795 
1796   	Use base assembler's expression parser to parse an expression.
1797   	It, unfortunately, runs off a global which we have to save/restore
1798   	in order to make it work for us.
1799 
1800   	An empty expression string is treated as an absolute 0.
1801 
1802   	Sets O_illegal regardless of expression evaluation if entire input
1803   	string is not consumed in the evaluation -- tolerate no dangling junk!
1804 
1805   *************************************************************************** */
1806 static void
parse_expr(textP,expP)1807 parse_expr (textP, expP)
1808      char *textP;		/* Text of expression to be parsed */
1809      expressionS *expP;		/* Where to put the results of parsing */
1810 {
1811   char *save_in;		/* Save global here */
1812   symbolS *symP;
1813 
1814   know (textP);
1815 
1816   if (*textP == '\0')
1817     {
1818       /* Treat empty string as absolute 0 */
1819       expP->X_add_symbol = expP->X_op_symbol = NULL;
1820       expP->X_add_number = 0;
1821       expP->X_op = O_constant;
1822     }
1823   else
1824     {
1825       save_in = input_line_pointer;	/* Save global */
1826       input_line_pointer = textP;	/* Make parser work for us */
1827 
1828       (void) expression (expP);
1829       if ((size_t) (input_line_pointer - textP) != strlen (textP))
1830 	{
1831 	  /* Did not consume all of the input */
1832 	  expP->X_op = O_illegal;
1833 	}
1834       symP = expP->X_add_symbol;
1835       if (symP && (hash_find (reg_hash, S_GET_NAME (symP))))
1836 	{
1837 	  /* Register name in an expression */
1838 	  /* FIXME: this isn't much of a check any more.  */
1839 	  expP->X_op = O_illegal;
1840 	}
1841 
1842       input_line_pointer = save_in;	/* Restore global */
1843     }
1844 }
1845 
1846 /*****************************************************************************
1847    parse_ldcont:
1848   	Parse and replace a 'ldconst' pseudo-instruction with an appropriate
1849   	i80960 instruction.
1850 
1851   	Assumes the input consists of:
1852   		arg[0]	opcode mnemonic ('ldconst')
1853   		arg[1]  first operand (constant)
1854   		arg[2]	name of register to be loaded
1855 
1856   	Replaces opcode and/or operands as appropriate.
1857 
1858   	Returns the new number of arguments, or -1 on failure.
1859 
1860   *************************************************************************** */
1861 static int
parse_ldconst(arg)1862 parse_ldconst (arg)
1863      char *arg[];		/* See above */
1864 {
1865   int n;			/* Constant to be loaded */
1866   int shift;			/* Shift count for "shlo" instruction */
1867   static char buf[5];		/* Literal for first operand */
1868   static char buf2[5];		/* Literal for second operand */
1869   expressionS e;		/* Parsed expression */
1870 
1871   arg[3] = NULL;		/* So we can tell at the end if it got used or not */
1872 
1873   parse_expr (arg[1], &e);
1874   switch (e.X_op)
1875     {
1876     default:
1877       /* We're dependent on one or more symbols -- use "lda" */
1878       arg[0] = "lda";
1879       break;
1880 
1881     case O_constant:
1882       /* Try the following mappings:
1883        *      ldconst 0,<reg>  ->mov  0,<reg>
1884        *        ldconst 31,<reg> ->mov  31,<reg>
1885        *        ldconst 32,<reg> ->addo 1,31,<reg>
1886        *        ldconst 62,<reg> ->addo 31,31,<reg>
1887        *        ldconst 64,<reg> ->shlo 8,3,<reg>
1888        *        ldconst -1,<reg> ->subo 1,0,<reg>
1889        *        ldconst -31,<reg>->subo 31,0,<reg>
1890        *
1891        * anything else becomes:
1892        *        lda xxx,<reg>
1893        */
1894       n = offs (e);
1895       if ((0 <= n) && (n <= 31))
1896 	{
1897 	  arg[0] = "mov";
1898 
1899 	}
1900       else if ((-31 <= n) && (n <= -1))
1901 	{
1902 	  arg[0] = "subo";
1903 	  arg[3] = arg[2];
1904 	  sprintf (buf, "%d", -n);
1905 	  arg[1] = buf;
1906 	  arg[2] = "0";
1907 
1908 	}
1909       else if ((32 <= n) && (n <= 62))
1910 	{
1911 	  arg[0] = "addo";
1912 	  arg[3] = arg[2];
1913 	  arg[1] = "31";
1914 	  sprintf (buf, "%d", n - 31);
1915 	  arg[2] = buf;
1916 
1917 	}
1918       else if ((shift = shift_ok (n)) != 0)
1919 	{
1920 	  arg[0] = "shlo";
1921 	  arg[3] = arg[2];
1922 	  sprintf (buf, "%d", shift);
1923 	  arg[1] = buf;
1924 	  sprintf (buf2, "%d", n >> shift);
1925 	  arg[2] = buf2;
1926 
1927 	}
1928       else
1929 	{
1930 	  arg[0] = "lda";
1931 	}
1932       break;
1933 
1934     case O_illegal:
1935       as_bad (_("invalid constant"));
1936       return -1;
1937       break;
1938     }
1939   return (arg[3] == 0) ? 2 : 3;
1940 }
1941 
1942 /*****************************************************************************
1943    parse_memop:	parse a memory operand
1944 
1945   	This routine is based on the observation that the 4 mode bits of the
1946   	MEMB format, taken individually, have fairly consistent meaning:
1947 
1948   		 M3 (bit 13): 1 if displacement is present (D_BIT)
1949   		 M2 (bit 12): 1 for MEMB instructions (MEMB_BIT)
1950   		 M1 (bit 11): 1 if index is present (I_BIT)
1951   		 M0 (bit 10): 1 if abase is present (A_BIT)
1952 
1953   	So we parse the memory operand and set bits in the mode as we find
1954   	things.  Then at the end, if we go to MEMB format, we need only set
1955   	the MEMB bit (M2) and our mode is built for us.
1956 
1957   	Unfortunately, I said "fairly consistent".  The exceptions:
1958 
1959   		 DBIA
1960   		 0100	Would seem illegal, but means "abase-only".
1961 
1962   		 0101	Would seem to mean "abase-only" -- it means IP-relative.
1963   			Must be converted to 0100.
1964 
1965   		 0110	Would seem to mean "index-only", but is reserved.
1966   			We turn on the D bit and provide a 0 displacement.
1967 
1968   	The other thing to observe is that we parse from the right, peeling
1969   	things * off as we go:  first any index spec, then any abase, then
1970   	the displacement.
1971 
1972   *************************************************************************** */
1973 static void
parse_memop(memP,argP,optype)1974 parse_memop (memP, argP, optype)
1975      memS *memP;		/* Where to put the results */
1976      char *argP;		/* Text of the operand to be parsed */
1977      int optype;		/* MEM1, MEM2, MEM4, MEM8, MEM12, or MEM16 */
1978 {
1979   char *indexP;			/* Pointer to index specification with "[]" removed */
1980   char *p;			/* Temp char pointer */
1981   char iprel_flag;		/* True if this is an IP-relative operand */
1982   int regnum;			/* Register number */
1983   /* Scale factor: 1,2,4,8, or 16.  Later converted to internal format
1984      (0,1,2,3,4 respectively).  */
1985   int scale;
1986   int mode;			/* MEMB mode bits */
1987   int *intP;			/* Pointer to register number */
1988 
1989   /* The following table contains the default scale factors for each
1990      type of memory instruction.  It is accessed using (optype-MEM1)
1991      as an index -- thus it assumes the 'optype' constants are
1992      assigned consecutive values, in the order they appear in this
1993      table.  */
1994   static const int def_scale[] =
1995   {
1996     1,				/* MEM1 */
1997     2,				/* MEM2 */
1998     4,				/* MEM4 */
1999     8,				/* MEM8 */
2000     -1,				/* MEM12 -- no valid default */
2001     16				/* MEM16 */
2002   };
2003 
2004   iprel_flag = mode = 0;
2005 
2006   /* Any index present? */
2007   indexP = get_ispec (argP);
2008   if (indexP)
2009     {
2010       p = strchr (indexP, '*');
2011       if (p == NULL)
2012 	{
2013 	  /* No explicit scale -- use default for this instruction
2014 	     type and assembler mode.  */
2015 	  if (flag_mri)
2016 	    scale = 1;
2017 	  else
2018 	    /* GNU960 compatibility */
2019 	    scale = def_scale[optype - MEM1];
2020 	}
2021       else
2022 	{
2023 	  *p++ = '\0';		/* Eliminate '*' */
2024 
2025 	  /* Now indexP->a '\0'-terminated register name,
2026 	     * and p->a scale factor.
2027 	   */
2028 
2029 	  if (!strcmp (p, "16"))
2030 	    {
2031 	      scale = 16;
2032 	    }
2033 	  else if (strchr ("1248", *p) && (p[1] == '\0'))
2034 	    {
2035 	      scale = *p - '0';
2036 	    }
2037 	  else
2038 	    {
2039 	      scale = -1;
2040 	    }
2041 	}
2042 
2043       regnum = get_regnum (indexP);	/* Get index reg. # */
2044       if (!IS_RG_REG (regnum))
2045 	{
2046 	  as_bad (_("invalid index register"));
2047 	  return;
2048 	}
2049 
2050       /* Convert scale to its binary encoding */
2051       switch (scale)
2052 	{
2053 	case 1:
2054 	  scale = 0 << 7;
2055 	  break;
2056 	case 2:
2057 	  scale = 1 << 7;
2058 	  break;
2059 	case 4:
2060 	  scale = 2 << 7;
2061 	  break;
2062 	case 8:
2063 	  scale = 3 << 7;
2064 	  break;
2065 	case 16:
2066 	  scale = 4 << 7;
2067 	  break;
2068 	default:
2069 	  as_bad (_("invalid scale factor"));
2070 	  return;
2071 	};
2072 
2073       memP->opcode |= scale | regnum;	/* Set index bits in opcode */
2074       mode |= I_BIT;		/* Found a valid index spec */
2075     }
2076 
2077   /* Any abase (Register Indirect) specification present? */
2078   if ((p = strrchr (argP, '(')) != NULL)
2079     {
2080       /* "(" is there -- does it start a legal abase spec?  If not, it
2081          could be part of a displacement expression.  */
2082       intP = (int *) hash_find (areg_hash, p);
2083       if (intP != NULL)
2084 	{
2085 	  /* Got an abase here */
2086 	  regnum = *intP;
2087 	  *p = '\0';		/* discard register spec */
2088 	  if (regnum == IPREL)
2089 	    {
2090 	      /* We have to specialcase ip-rel mode */
2091 	      iprel_flag = 1;
2092 	    }
2093 	  else
2094 	    {
2095 	      memP->opcode |= regnum << 14;
2096 	      mode |= A_BIT;
2097 	    }
2098 	}
2099     }
2100 
2101   /* Any expression present? */
2102   memP->e = argP;
2103   if (*argP != '\0')
2104     {
2105       mode |= D_BIT;
2106     }
2107 
2108   /* Special-case ip-relative addressing */
2109   if (iprel_flag)
2110     {
2111       if (mode & I_BIT)
2112 	{
2113 	  syntax ();
2114 	}
2115       else
2116 	{
2117 	  memP->opcode |= 5 << 10;	/* IP-relative mode */
2118 	  memP->disp = 32;
2119 	}
2120       return;
2121     }
2122 
2123   /* Handle all other modes */
2124   switch (mode)
2125     {
2126     case D_BIT | A_BIT:
2127       /* Go with MEMA instruction format for now (grow to MEMB later
2128          if 12 bits is not enough for the displacement).  MEMA format
2129          has a single mode bit: set it to indicate that abase is
2130          present.  */
2131       memP->opcode |= MEMA_ABASE;
2132       memP->disp = 12;
2133       break;
2134 
2135     case D_BIT:
2136       /* Go with MEMA instruction format for now (grow to MEMB later
2137          if 12 bits is not enough for the displacement).  */
2138       memP->disp = 12;
2139       break;
2140 
2141     case A_BIT:
2142       /* For some reason, the bit string for this mode is not
2143          consistent: it should be 0 (exclusive of the MEMB bit), so we
2144          set it "by hand" here.  */
2145       memP->opcode |= MEMB_BIT;
2146       break;
2147 
2148     case A_BIT | I_BIT:
2149       /* set MEMB bit in mode, and OR in mode bits */
2150       memP->opcode |= mode | MEMB_BIT;
2151       break;
2152 
2153     case I_BIT:
2154       /* Treat missing displacement as displacement of 0.  */
2155       mode |= D_BIT;
2156       /* Fall into next case.  */
2157     case D_BIT | A_BIT | I_BIT:
2158     case D_BIT | I_BIT:
2159       /* set MEMB bit in mode, and OR in mode bits */
2160       memP->opcode |= mode | MEMB_BIT;
2161       memP->disp = 32;
2162       break;
2163 
2164     default:
2165       syntax ();
2166       break;
2167     }
2168 }
2169 
2170 /*****************************************************************************
2171    parse_po:	parse machine-dependent pseudo-op
2172 
2173   	This is a top-level routine for machine-dependent pseudo-ops.  It slurps
2174   	up the rest of the input line, breaks out the individual arguments,
2175   	and dispatches them to the correct handler.
2176   *************************************************************************** */
2177 static void
parse_po(po_num)2178 parse_po (po_num)
2179      int po_num;		/* Pseudo-op number:  currently S_LEAFPROC or S_SYSPROC */
2180 {
2181   /* Pointers operands, with no embedded whitespace.
2182      arg[0] unused, arg[1-3]->operands */
2183   char *args[4];
2184   int n_ops;			/* Number of operands */
2185   char *p;			/* Pointer to beginning of unparsed argument string */
2186   char eol;			/* Character that indicated end of line */
2187 
2188   extern char is_end_of_line[];
2189 
2190   /* Advance input pointer to end of line.  */
2191   p = input_line_pointer;
2192   while (!is_end_of_line[(unsigned char) *input_line_pointer])
2193     {
2194       input_line_pointer++;
2195     }
2196   eol = *input_line_pointer;	/* Save end-of-line char */
2197   *input_line_pointer = '\0';	/* Terminate argument list */
2198 
2199   /* Parse out operands */
2200   n_ops = get_args (p, args);
2201   if (n_ops == -1)
2202     {
2203       return;
2204     }
2205 
2206   /* Dispatch to correct handler */
2207   switch (po_num)
2208     {
2209     case S_SYSPROC:
2210       s_sysproc (n_ops, args);
2211       break;
2212     case S_LEAFPROC:
2213       s_leafproc (n_ops, args);
2214       break;
2215     default:
2216       BAD_CASE (po_num);
2217       break;
2218     }
2219 
2220   /* Restore eol, so line numbers get updated correctly.  Base
2221      assembler assumes we leave input pointer pointing at char
2222      following the eol.  */
2223   *input_line_pointer++ = eol;
2224 }
2225 
2226 /*****************************************************************************
2227    parse_regop: parse a register operand.
2228 
2229   	In case of illegal operand, issue a message and return some valid
2230   	information so instruction processing can continue.
2231   *************************************************************************** */
2232 static void
parse_regop(regopP,optext,opdesc)2233 parse_regop (regopP, optext, opdesc)
2234      struct regop *regopP;	/* Where to put description of register operand */
2235      char *optext;		/* Text of operand */
2236      char opdesc;		/* Descriptor byte:  what's legal for this operand */
2237 {
2238   int n;			/* Register number */
2239   expressionS e;		/* Parsed expression */
2240 
2241   /* See if operand is a register */
2242   n = get_regnum (optext);
2243   if (n >= 0)
2244     {
2245       if (IS_RG_REG (n))
2246 	{
2247 	  /* global or local register */
2248 	  if (!REG_ALIGN (opdesc, n))
2249 	    {
2250 	      as_bad (_("unaligned register"));
2251 	    }
2252 	  regopP->n = n;
2253 	  regopP->mode = 0;
2254 	  regopP->special = 0;
2255 	  return;
2256 	}
2257       else if (IS_FP_REG (n) && FP_OK (opdesc))
2258 	{
2259 	  /* Floating point register, and it's allowed */
2260 	  regopP->n = n - FP0;
2261 	  regopP->mode = 1;
2262 	  regopP->special = 0;
2263 	  return;
2264 	}
2265       else if (IS_SF_REG (n) && SFR_OK (opdesc))
2266 	{
2267 	  /* Special-function register, and it's allowed */
2268 	  regopP->n = n - SF0;
2269 	  regopP->mode = 0;
2270 	  regopP->special = 1;
2271 	  if (!targ_has_sfr (regopP->n))
2272 	    {
2273 	      as_bad (_("no such sfr in this architecture"));
2274 	    }
2275 	  return;
2276 	}
2277     }
2278   else if (LIT_OK (opdesc))
2279     {
2280       /* How about a literal?  */
2281       regopP->mode = 1;
2282       regopP->special = 0;
2283       if (FP_OK (opdesc))
2284 	{			/* floating point literal acceptable */
2285 	  /* Skip over 0f, 0d, or 0e prefix */
2286 	  if ((optext[0] == '0')
2287 	      && (optext[1] >= 'd')
2288 	      && (optext[1] <= 'f'))
2289 	    {
2290 	      optext += 2;
2291 	    }
2292 
2293 	  if (!strcmp (optext, "0.0") || !strcmp (optext, "0"))
2294 	    {
2295 	      regopP->n = 0x10;
2296 	      return;
2297 	    }
2298 	  if (!strcmp (optext, "1.0") || !strcmp (optext, "1"))
2299 	    {
2300 	      regopP->n = 0x16;
2301 	      return;
2302 	    }
2303 
2304 	}
2305       else
2306 	{			/* fixed point literal acceptable */
2307 	  parse_expr (optext, &e);
2308 	  if (e.X_op != O_constant
2309 	      || (offs (e) < 0) || (offs (e) > 31))
2310 	    {
2311 	      as_bad (_("illegal literal"));
2312 	      offs (e) = 0;
2313 	    }
2314 	  regopP->n = offs (e);
2315 	  return;
2316 	}
2317     }
2318 
2319   /* Nothing worked */
2320   syntax ();
2321   regopP->mode = 0;		/* Register r0 is always a good one */
2322   regopP->n = 0;
2323   regopP->special = 0;
2324 }				/* parse_regop() */
2325 
2326 /*****************************************************************************
2327    reg_fmt:	generate a REG-format instruction
2328 
2329   *************************************************************************** */
2330 static void
reg_fmt(args,oP)2331 reg_fmt (args, oP)
2332      char *args[];		/* args[0]->opcode mnemonic, args[1-3]->operands */
2333      struct i960_opcode *oP;	/* Pointer to description of instruction */
2334 {
2335   long instr;			/* Binary to be output */
2336   struct regop regop;		/* Description of register operand */
2337   int n_ops;			/* Number of operands */
2338 
2339   instr = oP->opcode;
2340   n_ops = oP->num_ops;
2341 
2342   if (n_ops >= 1)
2343     {
2344       parse_regop (&regop, args[1], oP->operand[0]);
2345 
2346       if ((n_ops == 1) && !(instr & M3))
2347 	{
2348 	  /* 1-operand instruction in which the dst field should
2349 	     * be used (instead of src1).
2350 	   */
2351 	  regop.n <<= 19;
2352 	  if (regop.special)
2353 	    {
2354 	      regop.mode = regop.special;
2355 	    }
2356 	  regop.mode <<= 13;
2357 	  regop.special = 0;
2358 	}
2359       else
2360 	{
2361 	  /* regop.n goes in bit 0, needs no shifting */
2362 	  regop.mode <<= 11;
2363 	  regop.special <<= 5;
2364 	}
2365       instr |= regop.n | regop.mode | regop.special;
2366     }
2367 
2368   if (n_ops >= 2)
2369     {
2370       parse_regop (&regop, args[2], oP->operand[1]);
2371 
2372       if ((n_ops == 2) && !(instr & M3))
2373 	{
2374 	  /* 2-operand instruction in which the dst field should
2375 	     * be used instead of src2).
2376 	   */
2377 	  regop.n <<= 19;
2378 	  if (regop.special)
2379 	    {
2380 	      regop.mode = regop.special;
2381 	    }
2382 	  regop.mode <<= 13;
2383 	  regop.special = 0;
2384 	}
2385       else
2386 	{
2387 	  regop.n <<= 14;
2388 	  regop.mode <<= 12;
2389 	  regop.special <<= 6;
2390 	}
2391       instr |= regop.n | regop.mode | regop.special;
2392     }
2393   if (n_ops == 3)
2394     {
2395       parse_regop (&regop, args[3], oP->operand[2]);
2396       if (regop.special)
2397 	{
2398 	  regop.mode = regop.special;
2399 	}
2400       instr |= (regop.n <<= 19) | (regop.mode <<= 13);
2401     }
2402   emit (instr);
2403 }
2404 
2405 /*****************************************************************************
2406    relax_cobr:
2407   	Replace cobr instruction in a code fragment with equivalent branch and
2408   	compare instructions, so it can reach beyond a 13-bit displacement.
2409   	Set up an address fix/relocation for the new branch instruction.
2410 
2411   *************************************************************************** */
2412 
2413 /* This "conditional jump" table maps cobr instructions into
2414    equivalent compare and branch opcodes.  */
2415 static const
2416 struct
2417 {
2418   long compare;
2419   long branch;
2420 }
2421 
2422 coj[] =
2423 {				/* COBR OPCODE: */
2424   { CHKBIT, BNO },		/*      0x30 - bbc */
2425   { CMPO, BG },			/*      0x31 - cmpobg */
2426   { CMPO, BE },			/*      0x32 - cmpobe */
2427   { CMPO, BGE },		/*      0x33 - cmpobge */
2428   { CMPO, BL },			/*      0x34 - cmpobl */
2429   { CMPO, BNE },		/*      0x35 - cmpobne */
2430   { CMPO, BLE },		/*      0x36 - cmpoble */
2431   { CHKBIT, BO },		/*      0x37 - bbs */
2432   { CMPI, BNO },		/*      0x38 - cmpibno */
2433   { CMPI, BG },			/*      0x39 - cmpibg */
2434   { CMPI, BE },			/*      0x3a - cmpibe */
2435   { CMPI, BGE },		/*      0x3b - cmpibge */
2436   { CMPI, BL },			/*      0x3c - cmpibl */
2437   { CMPI, BNE },		/*      0x3d - cmpibne */
2438   { CMPI, BLE },		/*      0x3e - cmpible */
2439   { CMPI, BO },			/*      0x3f - cmpibo */
2440 };
2441 
2442 static void
relax_cobr(fragP)2443 relax_cobr (fragP)
2444      register fragS *fragP;	/* fragP->fr_opcode is assumed to point to
2445 				 * the cobr instruction, which comes at the
2446 				 * end of the code fragment.
2447 				 */
2448 {
2449   int opcode, src1, src2, m1, s2;
2450   /* Bit fields from cobr instruction */
2451   long bp_bits;			/* Branch prediction bits from cobr instruction */
2452   long instr;			/* A single i960 instruction */
2453   /* ->instruction to be replaced */
2454   char *iP;
2455   fixS *fixP;			/* Relocation that can be done at assembly time */
2456 
2457   /* PICK UP & PARSE COBR INSTRUCTION */
2458   iP = fragP->fr_opcode;
2459   instr = md_chars_to_number (iP, 4);
2460   opcode = ((instr >> 24) & 0xff) - 0x30;	/* "-0x30" for table index */
2461   src1 = (instr >> 19) & 0x1f;
2462   m1 = (instr >> 13) & 1;
2463   s2 = instr & 1;
2464   src2 = (instr >> 14) & 0x1f;
2465   bp_bits = instr & BP_MASK;
2466 
2467   /* GENERATE AND OUTPUT COMPARE INSTRUCTION */
2468   instr = coj[opcode].compare
2469     | src1 | (m1 << 11) | (s2 << 6) | (src2 << 14);
2470   md_number_to_chars (iP, instr, 4);
2471 
2472   /* OUTPUT BRANCH INSTRUCTION */
2473   md_number_to_chars (iP + 4, coj[opcode].branch | bp_bits, 4);
2474 
2475   /* SET UP ADDRESS FIXUP/RELOCATION */
2476   fixP = fix_new (fragP,
2477 		  iP + 4 - fragP->fr_literal,
2478 		  4,
2479 		  fragP->fr_symbol,
2480 		  fragP->fr_offset,
2481 		  1,
2482 		  NO_RELOC);
2483 
2484   fixP->fx_bit_fixP = (bit_fixS *) 24;	/* Store size of bit field */
2485 
2486   fragP->fr_fix += 4;
2487   frag_wane (fragP);
2488 }
2489 
2490 /*****************************************************************************
2491    reloc_callj:	Relocate a 'callj' instruction
2492 
2493   	This is a "non-(GNU)-standard" machine-dependent hook.  The base
2494   	assembler calls it when it decides it can relocate an address at
2495   	assembly time instead of emitting a relocation directive.
2496 
2497   	Check to see if the relocation involves a 'callj' instruction to a:
2498   	    sysproc:	Replace the default 'call' instruction with a 'calls'
2499   	    leafproc:	Replace the default 'call' instruction with a 'bal'.
2500   	    other proc:	Do nothing.
2501 
2502   	See b.out.h for details on the 'n_other' field in a symbol structure.
2503 
2504    IMPORTANT!:
2505   	Assumes the caller has already figured out, in the case of a leafproc,
2506   	to use the 'bal' entry point, and has substituted that symbol into the
2507   	passed fixup structure.
2508 
2509   *************************************************************************** */
2510 int
reloc_callj(fixP)2511 reloc_callj (fixP)
2512      /* Relocation that can be done at assembly time */
2513      fixS *fixP;
2514 {
2515   /* Points to the binary for the instruction being relocated.  */
2516   char *where;
2517 
2518   if (!fixP->fx_tcbit)
2519     {
2520       /* This wasn't a callj instruction in the first place */
2521       return 0;
2522     }
2523 
2524   where = fixP->fx_frag->fr_literal + fixP->fx_where;
2525 
2526   if (TC_S_IS_SYSPROC (fixP->fx_addsy))
2527     {
2528       /* Symbol is a .sysproc: replace 'call' with 'calls'.  System
2529          procedure number is (other-1).  */
2530       md_number_to_chars (where, CALLS | TC_S_GET_SYSPROC (fixP->fx_addsy), 4);
2531 
2532       /* Nothing else needs to be done for this instruction.  Make
2533          sure 'md_number_to_field()' will perform a no-op.  */
2534       fixP->fx_bit_fixP = (bit_fixS *) 1;
2535     }
2536   else if (TC_S_IS_CALLNAME (fixP->fx_addsy))
2537     {
2538       /* Should not happen: see block comment above */
2539       as_fatal (_("Trying to 'bal' to %s"), S_GET_NAME (fixP->fx_addsy));
2540     }
2541   else if (TC_S_IS_BALNAME (fixP->fx_addsy))
2542     {
2543       /* Replace 'call' with 'bal'; both instructions have the same
2544          format, so calling code should complete relocation as if
2545          nothing happened here.  */
2546       md_number_to_chars (where, BAL, 4);
2547     }
2548   else if (TC_S_IS_BADPROC (fixP->fx_addsy))
2549     {
2550       as_bad (_("Looks like a proc, but can't tell what kind.\n"));
2551     }				/* switch on proc type */
2552 
2553   /* else Symbol is neither a sysproc nor a leafproc */
2554   return 0;
2555 }
2556 
2557 /*****************************************************************************
2558    s_leafproc:	process .leafproc pseudo-op
2559 
2560   	.leafproc takes two arguments, the second one is optional:
2561   		arg[1]: name of 'call' entry point to leaf procedure
2562   		arg[2]: name of 'bal' entry point to leaf procedure
2563 
2564   	If the two arguments are identical, or if the second one is missing,
2565   	the first argument is taken to be the 'bal' entry point.
2566 
2567   	If there are 2 distinct arguments, we must make sure that the 'bal'
2568   	entry point immediately follows the 'call' entry point in the linked
2569   	list of symbols.
2570 
2571   *************************************************************************** */
2572 static void
s_leafproc(n_ops,args)2573 s_leafproc (n_ops, args)
2574      int n_ops;			/* Number of operands */
2575      char *args[];		/* args[1]->1st operand, args[2]->2nd operand */
2576 {
2577   symbolS *callP;		/* Pointer to leafproc 'call' entry point symbol */
2578   symbolS *balP;		/* Pointer to leafproc 'bal' entry point symbol */
2579 
2580   if ((n_ops != 1) && (n_ops != 2))
2581     {
2582       as_bad (_("should have 1 or 2 operands"));
2583       return;
2584     }				/* Check number of arguments */
2585 
2586   /* Find or create symbol for 'call' entry point.  */
2587   callP = symbol_find_or_make (args[1]);
2588 
2589   if (TC_S_IS_CALLNAME (callP))
2590     {
2591       as_warn (_("Redefining leafproc %s"), S_GET_NAME (callP));
2592     }				/* is leafproc */
2593 
2594   /* If that was the only argument, use it as the 'bal' entry point.
2595      * Otherwise, mark it as the 'call' entry point and find or create
2596      * another symbol for the 'bal' entry point.
2597    */
2598   if ((n_ops == 1) || !strcmp (args[1], args[2]))
2599     {
2600       TC_S_FORCE_TO_BALNAME (callP);
2601 
2602     }
2603   else
2604     {
2605       TC_S_FORCE_TO_CALLNAME (callP);
2606 
2607       balP = symbol_find_or_make (args[2]);
2608       if (TC_S_IS_CALLNAME (balP))
2609 	{
2610 	  as_warn (_("Redefining leafproc %s"), S_GET_NAME (balP));
2611 	}
2612       TC_S_FORCE_TO_BALNAME (balP);
2613 
2614 #ifndef OBJ_ELF
2615       tc_set_bal_of_call (callP, balP);
2616 #endif
2617     }				/* if only one arg, or the args are the same */
2618 }
2619 
2620 /*
2621    s_sysproc: process .sysproc pseudo-op
2622 
2623         .sysproc takes two arguments:
2624                 arg[1]: name of entry point to system procedure
2625                 arg[2]: 'entry_num' (index) of system procedure in the range
2626                         [0,31] inclusive.
2627 
2628         For [ab].out, we store the 'entrynum' in the 'n_other' field of
2629         the symbol.  Since that entry is normally 0, we bias 'entrynum'
2630         by adding 1 to it.  It must be unbiased before it is used.  */
2631 static void
s_sysproc(n_ops,args)2632 s_sysproc (n_ops, args)
2633      int n_ops;			/* Number of operands */
2634      char *args[];		/* args[1]->1st operand, args[2]->2nd operand */
2635 {
2636   expressionS exp;
2637   symbolS *symP;
2638 
2639   if (n_ops != 2)
2640     {
2641       as_bad (_("should have two operands"));
2642       return;
2643     }				/* bad arg count */
2644 
2645   /* Parse "entry_num" argument and check it for validity.  */
2646   parse_expr (args[2], &exp);
2647   if (exp.X_op != O_constant
2648       || (offs (exp) < 0)
2649       || (offs (exp) > 31))
2650     {
2651       as_bad (_("'entry_num' must be absolute number in [0,31]"));
2652       return;
2653     }
2654 
2655   /* Find/make symbol and stick entry number (biased by +1) into it */
2656   symP = symbol_find_or_make (args[1]);
2657 
2658   if (TC_S_IS_SYSPROC (symP))
2659     {
2660       as_warn (_("Redefining entrynum for sysproc %s"), S_GET_NAME (symP));
2661     }				/* redefining */
2662 
2663   TC_S_SET_SYSPROC (symP, offs (exp));	/* encode entry number */
2664   TC_S_FORCE_TO_SYSPROC (symP);
2665 }
2666 
2667 /*****************************************************************************
2668    shift_ok:
2669   	Determine if a "shlo" instruction can be used to implement a "ldconst".
2670   	This means that some number X < 32 can be shifted left to produce the
2671   	constant of interest.
2672 
2673   	Return the shift count, or 0 if we can't do it.
2674   	Caller calculates X by shifting original constant right 'shift' places.
2675 
2676   *************************************************************************** */
2677 static int
shift_ok(n)2678 shift_ok (n)
2679      int n;			/* The constant of interest */
2680 {
2681   int shift;			/* The shift count */
2682 
2683   if (n <= 0)
2684     {
2685       /* Can't do it for negative numbers */
2686       return 0;
2687     }
2688 
2689   /* Shift 'n' right until a 1 is about to be lost */
2690   for (shift = 0; (n & 1) == 0; shift++)
2691     {
2692       n >>= 1;
2693     }
2694 
2695   if (n >= 32)
2696     {
2697       return 0;
2698     }
2699   return shift;
2700 }
2701 
2702 /* syntax: issue syntax error */
2703 
2704 static void
syntax()2705 syntax ()
2706 {
2707   as_bad (_("syntax error"));
2708 }				/* syntax() */
2709 
2710 /* targ_has_sfr:
2711 
2712    Return TRUE iff the target architecture supports the specified
2713    special-function register (sfr).  */
2714 
2715 static int
targ_has_sfr(n)2716 targ_has_sfr (n)
2717      int n;			/* Number (0-31) of sfr */
2718 {
2719   switch (architecture)
2720     {
2721     case ARCH_KA:
2722     case ARCH_KB:
2723     case ARCH_MC:
2724     case ARCH_JX:
2725       return 0;
2726     case ARCH_HX:
2727       return ((0 <= n) && (n <= 4));
2728     case ARCH_CA:
2729     default:
2730       return ((0 <= n) && (n <= 2));
2731     }
2732 }
2733 
2734 /* targ_has_iclass:
2735 
2736    Return TRUE iff the target architecture supports the indicated
2737    class of instructions.  */
2738 static int
targ_has_iclass(ic)2739 targ_has_iclass (ic)
2740      /* Instruction class;  one of:
2741         I_BASE, I_CX, I_DEC, I_KX, I_FP, I_MIL, I_CASIM, I_CX2, I_HX, I_HX2
2742       */
2743      int ic;
2744 {
2745   iclasses_seen |= ic;
2746   switch (architecture)
2747     {
2748     case ARCH_KA:
2749       return ic & (I_BASE | I_KX);
2750     case ARCH_KB:
2751       return ic & (I_BASE | I_KX | I_FP | I_DEC);
2752     case ARCH_MC:
2753       return ic & (I_BASE | I_KX | I_FP | I_DEC | I_MIL);
2754     case ARCH_CA:
2755       return ic & (I_BASE | I_CX | I_CX2 | I_CASIM);
2756     case ARCH_JX:
2757       return ic & (I_BASE | I_CX2 | I_JX);
2758     case ARCH_HX:
2759       return ic & (I_BASE | I_CX2 | I_JX | I_HX);
2760     default:
2761       if ((iclasses_seen & (I_KX | I_FP | I_DEC | I_MIL))
2762 	  && (iclasses_seen & (I_CX | I_CX2)))
2763 	{
2764 	  as_warn (_("architecture of opcode conflicts with that of earlier instruction(s)"));
2765 	  iclasses_seen &= ~ic;
2766 	}
2767       return 1;
2768     }
2769 }
2770 
2771 /* Handle the MRI .endian pseudo-op.  */
2772 
2773 static void
s_endian(ignore)2774 s_endian (ignore)
2775      int ignore ATTRIBUTE_UNUSED;
2776 {
2777   char *name;
2778   char c;
2779 
2780   name = input_line_pointer;
2781   c = get_symbol_end ();
2782   if (strcasecmp (name, "little") == 0)
2783     ;
2784   else if (strcasecmp (name, "big") == 0)
2785     as_bad (_("big endian mode is not supported"));
2786   else
2787     as_warn (_("ignoring unrecognized .endian type `%s'"), name);
2788 
2789   *input_line_pointer = c;
2790 
2791   demand_empty_rest_of_line ();
2792 }
2793 
2794 /* We have no need to default values of symbols.  */
2795 
2796 symbolS *
md_undefined_symbol(name)2797 md_undefined_symbol (name)
2798      char *name ATTRIBUTE_UNUSED;
2799 {
2800   return 0;
2801 }
2802 
2803 /* Exactly what point is a PC-relative offset relative TO?
2804    On the i960, they're relative to the address of the instruction,
2805    which we have set up as the address of the fixup too.  */
2806 long
md_pcrel_from(fixP)2807 md_pcrel_from (fixP)
2808      fixS *fixP;
2809 {
2810   return fixP->fx_where + fixP->fx_frag->fr_address;
2811 }
2812 
2813 void
md_apply_fix3(fixP,valP,seg)2814 md_apply_fix3 (fixP, valP, seg)
2815      fixS *fixP;
2816      valueT *valP;
2817      segT seg ATTRIBUTE_UNUSED;
2818 {
2819   long val = *valP;
2820   char *place = fixP->fx_where + fixP->fx_frag->fr_literal;
2821 
2822   if (!fixP->fx_bit_fixP)
2823     {
2824 #ifndef BFD_ASSEMBLER
2825       /* For callx, we always want to write out zero, and emit a
2826 	 symbolic relocation.  */
2827       if (fixP->fx_bsr)
2828 	val = 0;
2829 
2830       fixP->fx_addnumber = val;
2831 #endif
2832 
2833       md_number_to_imm (place, val, fixP->fx_size);
2834     }
2835   else if ((int) fixP->fx_bit_fixP == 13
2836 	   && fixP->fx_addsy != NULL
2837 	   && S_GET_SEGMENT (fixP->fx_addsy) == undefined_section)
2838     {
2839       /* This is a COBR instruction.  They have only a
2840 	 13-bit displacement and are only to be used
2841 	 for local branches: flag as error, don't generate
2842 	 relocation.  */
2843       as_bad_where (fixP->fx_file, fixP->fx_line,
2844 		    _("can't use COBR format with external label"));
2845       fixP->fx_addsy = NULL;
2846     }
2847   else
2848     md_number_to_field (place, val, fixP->fx_bit_fixP);
2849 
2850   if (fixP->fx_addsy == NULL)
2851     fixP->fx_done = 1;
2852 }
2853 
2854 #if defined(OBJ_AOUT) | defined(OBJ_BOUT)
2855 void
tc_bout_fix_to_chars(where,fixP,segment_address_in_file)2856 tc_bout_fix_to_chars (where, fixP, segment_address_in_file)
2857      char *where;
2858      fixS *fixP;
2859      relax_addressT segment_address_in_file;
2860 {
2861   static const unsigned char nbytes_r_length[] = {42, 0, 1, 42, 2};
2862   struct relocation_info ri;
2863   symbolS *symbolP;
2864 
2865   memset ((char *) &ri, '\0', sizeof (ri));
2866   symbolP = fixP->fx_addsy;
2867   know (symbolP != 0 || fixP->fx_r_type != NO_RELOC);
2868   ri.r_bsr = fixP->fx_bsr;	/*SAC LD RELAX HACK */
2869   /* These two 'cuz of NS32K */
2870   ri.r_callj = fixP->fx_tcbit;
2871   if (fixP->fx_bit_fixP)
2872     ri.r_length = 2;
2873   else
2874     ri.r_length = nbytes_r_length[fixP->fx_size];
2875   ri.r_pcrel = fixP->fx_pcrel;
2876   ri.r_address = fixP->fx_frag->fr_address + fixP->fx_where - segment_address_in_file;
2877 
2878   if (fixP->fx_r_type != NO_RELOC)
2879     {
2880       switch (fixP->fx_r_type)
2881 	{
2882 	case rs_align:
2883 	  ri.r_index = -2;
2884 	  ri.r_pcrel = 1;
2885 	  ri.r_length = fixP->fx_size - 1;
2886 	  break;
2887 	case rs_org:
2888 	  ri.r_index = -2;
2889 	  ri.r_pcrel = 0;
2890 	  break;
2891 	case rs_fill:
2892 	  ri.r_index = -1;
2893 	  break;
2894 	default:
2895 	  abort ();
2896 	}
2897       ri.r_extern = 0;
2898     }
2899   else if (linkrelax || !S_IS_DEFINED (symbolP) || fixP->fx_bsr)
2900     {
2901       ri.r_extern = 1;
2902       ri.r_index = symbolP->sy_number;
2903     }
2904   else
2905     {
2906       ri.r_extern = 0;
2907       ri.r_index = S_GET_TYPE (symbolP);
2908     }
2909 
2910   /* Output the relocation information in machine-dependent form.  */
2911   md_ri_to_chars (where, &ri);
2912 }
2913 
2914 #endif /* OBJ_AOUT or OBJ_BOUT */
2915 
2916 #if defined (OBJ_COFF) && defined (BFD)
2917 short
tc_coff_fix2rtype(fixP)2918 tc_coff_fix2rtype (fixP)
2919      fixS *fixP;
2920 {
2921   if (fixP->fx_bsr)
2922     abort ();
2923 
2924   if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
2925     return R_RELLONG;
2926 
2927   if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
2928     return R_IPRMED;
2929 
2930   abort ();
2931   return 0;
2932 }
2933 
2934 int
tc_coff_sizemachdep(frag)2935 tc_coff_sizemachdep (frag)
2936      fragS *frag;
2937 {
2938   if (frag->fr_next)
2939     return frag->fr_next->fr_address - frag->fr_address;
2940   else
2941     return 0;
2942 }
2943 #endif
2944 
2945 /* Align an address by rounding it up to the specified boundary.  */
2946 valueT
md_section_align(seg,addr)2947 md_section_align (seg, addr)
2948      segT seg;
2949      valueT addr;		/* Address to be rounded up */
2950 {
2951   int align;
2952 #ifdef BFD_ASSEMBLER
2953   align = bfd_get_section_alignment (stdoutput, seg);
2954 #else
2955   align = section_alignment[(int) seg];
2956 #endif
2957   return (addr + (1 << align) - 1) & (-1 << align);
2958 }
2959 
2960 extern int coff_flags;
2961 
2962 #ifdef OBJ_COFF
2963 void
tc_headers_hook(headers)2964 tc_headers_hook (headers)
2965      object_headers *headers;
2966 {
2967   switch (architecture)
2968     {
2969     case ARCH_KA:
2970       coff_flags |= F_I960KA;
2971       break;
2972 
2973     case ARCH_KB:
2974       coff_flags |= F_I960KB;
2975       break;
2976 
2977     case ARCH_MC:
2978       coff_flags |= F_I960MC;
2979       break;
2980 
2981     case ARCH_CA:
2982       coff_flags |= F_I960CA;
2983       break;
2984 
2985     case ARCH_JX:
2986       coff_flags |= F_I960JX;
2987       break;
2988 
2989     case ARCH_HX:
2990       coff_flags |= F_I960HX;
2991       break;
2992 
2993     default:
2994       if (iclasses_seen == I_BASE)
2995 	coff_flags |= F_I960CORE;
2996       else if (iclasses_seen & I_CX)
2997 	coff_flags |= F_I960CA;
2998       else if (iclasses_seen & I_HX)
2999 	coff_flags |= F_I960HX;
3000       else if (iclasses_seen & I_JX)
3001 	coff_flags |= F_I960JX;
3002       else if (iclasses_seen & I_CX2)
3003 	coff_flags |= F_I960CA;
3004       else if (iclasses_seen & I_MIL)
3005 	coff_flags |= F_I960MC;
3006       else if (iclasses_seen & (I_DEC | I_FP))
3007 	coff_flags |= F_I960KB;
3008       else
3009 	coff_flags |= F_I960KA;
3010       break;
3011     }
3012 
3013   if (flag_readonly_data_in_text)
3014     {
3015       headers->filehdr.f_magic = I960RWMAGIC;
3016       headers->aouthdr.magic = OMAGIC;
3017     }
3018   else
3019     {
3020       headers->filehdr.f_magic = I960ROMAGIC;
3021       headers->aouthdr.magic = NMAGIC;
3022     }				/* set magic numbers */
3023 }
3024 
3025 #endif /* OBJ_COFF */
3026 
3027 #ifndef BFD_ASSEMBLER
3028 
3029 /* Things going on here:
3030 
3031    For bout, We need to assure a couple of simplifying
3032    assumptions about leafprocs for the linker: the leafproc
3033    entry symbols will be defined in the same assembly in
3034    which they're declared with the '.leafproc' directive;
3035    and if a leafproc has both 'call' and 'bal' entry points
3036    they are both global or both local.
3037 
3038    For coff, the call symbol has a second aux entry that
3039    contains the bal entry point.  The bal symbol becomes a
3040    label.
3041 
3042    For coff representation, the call symbol has a second aux entry that
3043    contains the bal entry point.  The bal symbol becomes a label.  */
3044 
3045 void
tc_crawl_symbol_chain(headers)3046 tc_crawl_symbol_chain (headers)
3047      object_headers *headers ATTRIBUTE_UNUSED;
3048 {
3049   symbolS *symbolP;
3050 
3051   for (symbolP = symbol_rootP; symbolP; symbolP = symbol_next (symbolP))
3052     {
3053 #ifdef OBJ_COFF
3054       if (TC_S_IS_SYSPROC (symbolP))
3055 	{
3056 	  /* second aux entry already contains the sysproc number */
3057 	  S_SET_NUMBER_AUXILIARY (symbolP, 2);
3058 	  S_SET_STORAGE_CLASS (symbolP, C_SCALL);
3059 	  S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3060 	  continue;
3061 	}			/* rewrite sysproc */
3062 #endif /* OBJ_COFF */
3063 
3064       if (!TC_S_IS_BALNAME (symbolP) && !TC_S_IS_CALLNAME (symbolP))
3065 	{
3066 	  continue;
3067 	}			/* Not a leafproc symbol */
3068 
3069       if (!S_IS_DEFINED (symbolP))
3070 	{
3071 	  as_bad (_("leafproc symbol '%s' undefined"), S_GET_NAME (symbolP));
3072 	}			/* undefined leaf */
3073 
3074       if (TC_S_IS_CALLNAME (symbolP))
3075 	{
3076 	  symbolS *balP = tc_get_bal_of_call (symbolP);
3077 	  if (S_IS_EXTERNAL (symbolP) != S_IS_EXTERNAL (balP))
3078 	    {
3079 	      S_SET_EXTERNAL (symbolP);
3080 	      S_SET_EXTERNAL (balP);
3081 	      as_warn (_("Warning: making leafproc entries %s and %s both global\n"),
3082 		       S_GET_NAME (symbolP), S_GET_NAME (balP));
3083 	    }			/* externality mismatch */
3084 	}			/* if callname */
3085     }				/* walk the symbol chain */
3086 }
3087 
3088 #endif /* ! BFD_ASSEMBLER */
3089 
3090 /* For aout or bout, the bal immediately follows the call.
3091 
3092    For coff, we cheat and store a pointer to the bal symbol in the
3093    second aux entry of the call.  */
3094 
3095 #undef OBJ_ABOUT
3096 #ifdef OBJ_AOUT
3097 #define OBJ_ABOUT
3098 #endif
3099 #ifdef OBJ_BOUT
3100 #define OBJ_ABOUT
3101 #endif
3102 
3103 void
tc_set_bal_of_call(callP,balP)3104 tc_set_bal_of_call (callP, balP)
3105      symbolS *callP ATTRIBUTE_UNUSED;
3106      symbolS *balP ATTRIBUTE_UNUSED;
3107 {
3108   know (TC_S_IS_CALLNAME (callP));
3109   know (TC_S_IS_BALNAME (balP));
3110 
3111 #ifdef OBJ_COFF
3112 
3113   callP->sy_tc = balP;
3114   S_SET_NUMBER_AUXILIARY (callP, 2);
3115 
3116 #else /* ! OBJ_COFF */
3117 #ifdef OBJ_ABOUT
3118 
3119   /* If the 'bal' entry doesn't immediately follow the 'call'
3120      * symbol, unlink it from the symbol list and re-insert it.
3121    */
3122   if (symbol_next (callP) != balP)
3123     {
3124       symbol_remove (balP, &symbol_rootP, &symbol_lastP);
3125       symbol_append (balP, callP, &symbol_rootP, &symbol_lastP);
3126     }				/* if not in order */
3127 
3128 #else /* ! OBJ_ABOUT */
3129   as_fatal ("Only supported for a.out, b.out, or COFF");
3130 #endif /* ! OBJ_ABOUT */
3131 #endif /* ! OBJ_COFF */
3132 }
3133 
3134 symbolS *
tc_get_bal_of_call(callP)3135 tc_get_bal_of_call (callP)
3136      symbolS *callP ATTRIBUTE_UNUSED;
3137 {
3138   symbolS *retval;
3139 
3140   know (TC_S_IS_CALLNAME (callP));
3141 
3142 #ifdef OBJ_COFF
3143   retval = callP->sy_tc;
3144 #else
3145 #ifdef OBJ_ABOUT
3146   retval = symbol_next (callP);
3147 #else
3148   as_fatal ("Only supported for a.out, b.out, or COFF");
3149 #endif /* ! OBJ_ABOUT */
3150 #endif /* ! OBJ_COFF */
3151 
3152   know (TC_S_IS_BALNAME (retval));
3153   return retval;
3154 }				/* _tc_get_bal_of_call() */
3155 
3156 #ifdef OBJ_COFF
3157 void
tc_coff_symbol_emit_hook(symbolP)3158 tc_coff_symbol_emit_hook (symbolP)
3159      symbolS *symbolP ATTRIBUTE_UNUSED;
3160 {
3161   if (TC_S_IS_CALLNAME (symbolP))
3162     {
3163       symbolS *balP = tc_get_bal_of_call (symbolP);
3164 
3165 #if 0
3166       /* second aux entry contains the bal entry point */
3167       S_SET_NUMBER_AUXILIARY (symbolP, 2);
3168 #endif
3169       symbolP->sy_symbol.ost_auxent[1].x_bal.x_balntry = S_GET_VALUE (balP);
3170       if (S_GET_STORAGE_CLASS (symbolP) == C_EXT)
3171 	S_SET_STORAGE_CLASS (symbolP, C_LEAFEXT);
3172       else
3173 	S_SET_STORAGE_CLASS (symbolP, C_LEAFSTAT);
3174       S_SET_DATA_TYPE (symbolP, S_GET_DATA_TYPE (symbolP) | (DT_FCN << N_BTSHFT));
3175       /* fix up the bal symbol */
3176       S_SET_STORAGE_CLASS (balP, C_LABEL);
3177     }				/* only on calls */
3178 }
3179 #endif /* OBJ_COFF */
3180 
3181 void
i960_handle_align(fragp)3182 i960_handle_align (fragp)
3183      fragS *fragp ATTRIBUTE_UNUSED;
3184 {
3185   if (!linkrelax)
3186     return;
3187 
3188 #ifndef OBJ_BOUT
3189 
3190   as_bad (_("option --link-relax is only supported in b.out format"));
3191   linkrelax = 0;
3192   return;
3193 
3194 #else
3195 
3196   /* The text section "ends" with another alignment reloc, to which we
3197      aren't adding padding.  */
3198   if (fragp->fr_next == text_last_frag
3199       || fragp->fr_next == data_last_frag)
3200     return;
3201 
3202   /* alignment directive */
3203   fix_new (fragp, fragp->fr_fix, fragp->fr_offset, 0, 0, 0,
3204 	   (int) fragp->fr_type);
3205 #endif /* OBJ_BOUT */
3206 }
3207 
3208 int
i960_validate_fix(fixP,this_segment_type)3209 i960_validate_fix (fixP, this_segment_type)
3210      fixS *fixP;
3211      segT this_segment_type ATTRIBUTE_UNUSED;
3212 {
3213   if (fixP->fx_tcbit && TC_S_IS_CALLNAME (fixP->fx_addsy))
3214     {
3215       /* Relocation should be done via the associated 'bal'
3216          entry point symbol.  */
3217 
3218       if (!TC_S_IS_BALNAME (tc_get_bal_of_call (fixP->fx_addsy)))
3219 	{
3220 	  as_bad_where (fixP->fx_file, fixP->fx_line,
3221 			_("No 'bal' entry point for leafproc %s"),
3222 			S_GET_NAME (fixP->fx_addsy));
3223 	  return 0;
3224 	}
3225       fixP->fx_addsy = tc_get_bal_of_call (fixP->fx_addsy);
3226     }
3227 
3228   return 1;
3229 }
3230 
3231 #ifdef BFD_ASSEMBLER
3232 
3233 /* From cgen.c:  */
3234 
3235 static short tc_bfd_fix2rtype PARAMS ((fixS *));
3236 
3237 static short
tc_bfd_fix2rtype(fixP)3238 tc_bfd_fix2rtype (fixP)
3239      fixS *fixP;
3240 {
3241 #if 0
3242   if (fixP->fx_bsr)
3243     abort ();
3244 #endif
3245 
3246   if (fixP->fx_pcrel == 0 && fixP->fx_size == 4)
3247     return BFD_RELOC_32;
3248 
3249   if (fixP->fx_pcrel != 0 && fixP->fx_size == 4)
3250     return BFD_RELOC_24_PCREL;
3251 
3252   abort ();
3253   return 0;
3254 }
3255 
3256 /* Translate internal representation of relocation info to BFD target
3257    format.
3258 
3259    FIXME: To what extent can we get all relevant targets to use this?  */
3260 
3261 arelent *
tc_gen_reloc(section,fixP)3262 tc_gen_reloc (section, fixP)
3263      asection *section ATTRIBUTE_UNUSED;
3264      fixS *fixP;
3265 {
3266   arelent * reloc;
3267 
3268   reloc = (arelent *) xmalloc (sizeof (arelent));
3269 
3270   /* HACK: Is this right? */
3271   fixP->fx_r_type = tc_bfd_fix2rtype (fixP);
3272 
3273   reloc->howto = bfd_reloc_type_lookup (stdoutput, fixP->fx_r_type);
3274   if (reloc->howto == (reloc_howto_type *) NULL)
3275     {
3276       as_bad_where (fixP->fx_file, fixP->fx_line,
3277 		    "internal error: can't export reloc type %d (`%s')",
3278 		    fixP->fx_r_type,
3279 		    bfd_get_reloc_code_name (fixP->fx_r_type));
3280       return NULL;
3281     }
3282 
3283   assert (!fixP->fx_pcrel == !reloc->howto->pc_relative);
3284 
3285   reloc->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
3286   *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixP->fx_addsy);
3287   reloc->address = fixP->fx_frag->fr_address + fixP->fx_where;
3288   reloc->addend = fixP->fx_addnumber;
3289 
3290   return reloc;
3291 }
3292 
3293 /* end from cgen.c */
3294 
3295 #endif /* BFD_ASSEMBLER */
3296 
3297 /* end of tc-i960.c */
3298