1 /* CPU data header for iq2000.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23 */
24
25 #ifndef IQ2000_CPU_H
26 #define IQ2000_CPU_H
27
28 #define CGEN_ARCH iq2000
29
30 /* Given symbol S, return iq2000_cgen_<S>. */
31 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
32 #define CGEN_SYM(s) iq2000##_cgen_##s
33 #else
34 #define CGEN_SYM(s) iq2000/**/_cgen_/**/s
35 #endif
36
37
38 /* Selected cpu families. */
39 #define HAVE_CPU_IQ2000BF
40 #define HAVE_CPU_IQ10BF
41
42 #define CGEN_INSN_LSB0_P 1
43
44 /* Minimum size of any insn (in bytes). */
45 #define CGEN_MIN_INSN_SIZE 3
46
47 /* Maximum size of any insn (in bytes). */
48 #define CGEN_MAX_INSN_SIZE 4
49
50 #define CGEN_INT_INSN_P 1
51
52 /* Maximum number of syntax elements in an instruction. */
53 #define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 19
54
55 /* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
56 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
57 we can't hash on everything up to the space. */
58 #define CGEN_MNEMONIC_OPERANDS
59
60 /* Maximum number of fields in an instruction. */
61 #define CGEN_ACTUAL_MAX_IFMT_OPERANDS 8
62
63 /* Enums. */
64
65 /* Enum declaration for . */
66 typedef enum gr_names {
67 H_GR_R0 = 0, H_GR__0 = 0, H_GR_R1 = 1, H_GR__1 = 1
68 , H_GR_R2 = 2, H_GR__2 = 2, H_GR_R3 = 3, H_GR__3 = 3
69 , H_GR_R4 = 4, H_GR__4 = 4, H_GR_R5 = 5, H_GR__5 = 5
70 , H_GR_R6 = 6, H_GR__6 = 6, H_GR_R7 = 7, H_GR__7 = 7
71 , H_GR_R8 = 8, H_GR__8 = 8, H_GR_R9 = 9, H_GR__9 = 9
72 , H_GR_R10 = 10, H_GR__10 = 10, H_GR_R11 = 11, H_GR__11 = 11
73 , H_GR_R12 = 12, H_GR__12 = 12, H_GR_R13 = 13, H_GR__13 = 13
74 , H_GR_R14 = 14, H_GR__14 = 14, H_GR_R15 = 15, H_GR__15 = 15
75 , H_GR_R16 = 16, H_GR__16 = 16, H_GR_R17 = 17, H_GR__17 = 17
76 , H_GR_R18 = 18, H_GR__18 = 18, H_GR_R19 = 19, H_GR__19 = 19
print_fr(cd,dis_info,value,attrs,pc,length)77 , H_GR_R20 = 20, H_GR__20 = 20, H_GR_R21 = 21, H_GR__21 = 21
78 , H_GR_R22 = 22, H_GR__22 = 22, H_GR_R23 = 23, H_GR__23 = 23
79 , H_GR_R24 = 24, H_GR__24 = 24, H_GR_R25 = 25, H_GR__25 = 25
80 , H_GR_R26 = 26, H_GR__26 = 26, H_GR_R27 = 27, H_GR__27 = 27
81 , H_GR_R28 = 28, H_GR__28 = 28, H_GR_R29 = 29, H_GR__29 = 29
82 , H_GR_R30 = 30, H_GR__30 = 30, H_GR_R31 = 31, H_GR__31 = 31
83 } GR_NAMES;
84
85 /* Enum declaration for primary opcodes. */
86 typedef enum opcodes {
87 OP_SPECIAL = 0, OP_REGIMM = 1, OP_J = 2, OP_JAL = 3
88 , OP_BEQ = 4, OP_BNE = 5, OP_BLEZ = 6, OP_BGTZ = 7
89 , OP_ADDI = 8, OP_ADDIU = 9, OP_SLTI = 10, OP_SLTIU = 11
90 , OP_ANDI = 12, OP_ORI = 13, OP_XORI = 14, OP_LUI = 15
91 , OP_COP0 = 16, OP_COP1 = 17, OP_COP2 = 18, OP_COP3 = 19
92 , OP_BEQL = 20, OP_BNEL = 21, OP_BLEZL = 22, OP_BGTZL = 23
93 , OP_BMB0 = 24, OP_BMB1 = 25, OP_BMB2 = 26, OP_BMB3 = 27
94 , OP_BBI = 28, OP_BBV = 29, OP_BBIN = 30, OP_BBVN = 31
95 , OP_LB = 32, OP_LH = 33, OP_LW = 35, OP_LBU = 36
96 , OP_LHU = 37, OP_RAM = 39, OP_SB = 40, OP_SH = 41
97 , OP_SW = 43, OP_ANDOI = 44, OP_BMB = 45, OP_ORUI = 47
98 , OP_LDW = 48, OP_SDW = 56, OP_ANDOUI = 63
99 } OPCODES;
100
101 /* Enum declaration for iq10-only primary opcodes. */
102 typedef enum q10_opcodes {
103 OP10_BMB = 6, OP10_ORUI = 15, OP10_BMBL = 22, OP10_ANDOUI = 47
104 , OP10_BBIL = 60, OP10_BBVL = 61, OP10_BBINL = 62, OP10_BBVNL = 63
105 } Q10_OPCODES;
106
107 /* Enum declaration for branch sub-opcodes. */
108 typedef enum regimm_functions {
109 FUNC_BLTZ = 0, FUNC_BGEZ = 1, FUNC_BLTZL = 2, FUNC_BGEZL = 3
110 , FUNC_BLEZ = 4, FUNC_BGTZ = 5, FUNC_BLEZL = 6, FUNC_BGTZL = 7
111 , FUNC_BRI = 8, FUNC_BRV = 9, FUNC_BCTX = 12, FUNC_BLTZAL = 16
112 , FUNC_BGEZAL = 17, FUNC_BLTZALL = 18, FUNC_BGEZALL = 19, FUNC_BLEZAL = 20
113 , FUNC_BGTZAL = 21, FUNC_BLEZALL = 22, FUNC_BGTZALL = 23
114 } REGIMM_FUNCTIONS;
115
116 /* Enum declaration for function sub-opcodes. */
117 typedef enum functions {
118 FUNC_SLL = 0, FUNC_SLMV = 1, FUNC_SRL = 2, FUNC_SRA = 3
119 , FUNC_SLLV = 4, FUNC_SRMV = 5, FUNC_SRLV = 6, FUNC_SRAV = 7
120 , FUNC_JR = 8, FUNC_JALR = 9, FUNC_JCR = 10, FUNC_SYSCALL = 12
121 , FUNC_BREAK = 13, FUNC_SLEEP = 14, FUNC_ADD = 32, FUNC_ADDU = 33
122 , FUNC_SUB = 34, FUNC_SUBU = 35, FUNC_AND = 36, FUNC_OR = 37
123 , FUNC_XOR = 38, FUNC_NOR = 39, FUNC_ADO16 = 41, FUNC_SLT = 42
124 , FUNC_SLTU = 43, FUNC_MRGB = 45
125 } FUNCTIONS;
126
127 /* Enum declaration for iq10-only special function sub-opcodes. */
128 typedef enum q10s_functions {
129 FUNC10_YIELD = 14, FUNC10_CNT1S = 46
130 } Q10S_FUNCTIONS;
131
132 /* Enum declaration for iq10 function sub-opcodes. */
print_dollarhex(cd,dis_info,value,attrs,pc,length)133 typedef enum cop_functions {
134 FUNC10_CFC = 0, FUNC10_LOCK = 1, FUNC10_CTC = 2, FUNC10_UNLK = 3
135 , FUNC10_SWRD = 4, FUNC10_SWRDL = 5, FUNC10_SWWR = 6, FUNC10_SWWRU = 7
136 , FUNC10_RBA = 8, FUNC10_RBAL = 9, FUNC10_RBAR = 10, FUNC10_DWRD = 12
137 , FUNC10_DWRDL = 13, FUNC10_WBA = 16, FUNC10_WBAU = 17, FUNC10_WBAC = 18
138 , FUNC10_CRC32 = 20, FUNC10_CRC32B = 21, FUNC10_MCID = 32, FUNC10_DBD = 33
139 , FUNC10_DBA = 34, FUNC10_DPWT = 35, FUNC10_AVAIL = 36, FUNC10_FREE = 37
140 , FUNC10_CHKHDR = 38, FUNC10_TSTOD = 39, FUNC10_PKRLA = 40, FUNC10_PKRLAU = 41
141 , FUNC10_PKRLAH = 42, FUNC10_PKRLAC = 43, FUNC10_CMPHDR = 44, FUNC10_CM64RS = 0
142 , FUNC10_CM64RD = 1, FUNC10_CM64RI = 4, FUNC10_CM64CLR = 5, FUNC10_CM64SS = 8
143 , FUNC10_CM64SD = 9, FUNC10_CM64SI = 12, FUNC10_CM64RA = 16, FUNC10_CM64RIA2 = 20
144 , FUNC10_CM128RIA2 = 21, FUNC10_CM64SA = 24, FUNC10_CM64SIA2 = 28, FUNC10_CM128SIA2 = 29
145 , FUNC10_CM32RS = 32, FUNC10_CM32RD = 33, FUNC10_CM32XOR = 34, FUNC10_CM32ANDN = 35
146 , FUNC10_CM32RI = 36, FUNC10_CM128VSA = 38, FUNC10_CM32SS = 40, FUNC10_CM32SD = 41
147 , FUNC10_CM32OR = 42, FUNC10_CM32AND = 43, FUNC10_CM32SI = 44, FUNC10_CM32RA = 48
148 , FUNC10_CM32SA = 56
149 } COP_FUNCTIONS;
150
151 /* Enum declaration for iq10 function sub-opcodes. */
152 typedef enum cop_cm128_4functions {
153 FUNC10_CM128RIA3 = 4, FUNC10_CM128SIA3 = 6
154 } COP_CM128_4FUNCTIONS;
155
156 /* Enum declaration for iq10 function sub-opcodes. */
157 typedef enum cop_cm128_3functions {
158 FUNC10_CM128RIA4 = 6, FUNC10_CM128SIA4 = 7
159 } COP_CM128_3FUNCTIONS;
160
print_dollarhex16(cd,dis_info,value,attrs,pc,length)161 /* Enum declaration for iq10 coprocessor sub-opcodes. */
162 typedef enum cop2_functions {
163 FUNC10_PKRLI = 0, FUNC10_PKRLIU = 1, FUNC10_PKRLIH = 2, FUNC10_PKRLIC = 3
164 , FUNC10_RBIR = 1, FUNC10_RBI = 2, FUNC10_RBIL = 3, FUNC10_WBIC = 5
165 , FUNC10_WBI = 6, FUNC10_WBIU = 7
166 } COP2_FUNCTIONS;
167
168 /* Enum declaration for iq10 coprocessor cam sub-opcodes. */
169 typedef enum cop3_cam_functions {
170 FUNC10_CAM36 = 16, FUNC10_CAM72 = 17, FUNC10_CAM144 = 18, FUNC10_CAM288 = 19
171 } COP3_CAM_FUNCTIONS;
172
173 /* Attributes. */
174
print_dollarhex_addr16h(cd,dis_info,value,attrs,pc,length)175 /* Enum declaration for machine type selection. */
176 typedef enum mach_attr {
177 MACH_BASE, MACH_IQ2000, MACH_IQ10, MACH_MAX
178 } MACH_ATTR;
179
180 /* Enum declaration for instruction set selection. */
181 typedef enum isa_attr {
182 ISA_IQ2000, ISA_MAX
183 } ISA_ATTR;
184
185 /* Number of architecture variants. */
186 #define MAX_ISAS 1
187 #define MAX_MACHS ((int) MACH_MAX)
188
189 /* Ifield support. */
190
191 extern const struct cgen_ifld iq2000_cgen_ifld_table[];
192
print_dollarhex_addr16l(cd,dis_info,value,attrs,pc,length)193 /* Ifield attribute indices. */
194
195 /* Enum declaration for cgen_ifld attrs. */
196 typedef enum cgen_ifld_attr {
197 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
198 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_END_BOOLS, CGEN_IFLD_START_NBOOLS = 31
199 , CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
200 } CGEN_IFLD_ATTR;
201
202 /* Number of non-boolean elements in cgen_ifld_attr. */
203 #define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
204
205 /* Enum declaration for iq2000 ifield types. */
206 typedef enum ifield_type {
print_dollarhex_p(cd,dis_info,value,attrs,pc,length)207 IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS
208 , IQ2000_F_RT, IQ2000_F_RD, IQ2000_F_SHAMT, IQ2000_F_CP_OP
209 , IQ2000_F_CP_OP_10, IQ2000_F_CP_GRP, IQ2000_F_FUNC, IQ2000_F_IMM
210 , IQ2000_F_RD_RS, IQ2000_F_RD_RT, IQ2000_F_RT_RS, IQ2000_F_JTARG
211 , IQ2000_F_JTARGQ10, IQ2000_F_OFFSET, IQ2000_F_COUNT, IQ2000_F_BYTECOUNT
212 , IQ2000_F_INDEX, IQ2000_F_MASK, IQ2000_F_MASKQ10, IQ2000_F_MASKL
213 , IQ2000_F_EXCODE, IQ2000_F_RSRVD, IQ2000_F_10_11, IQ2000_F_24_19
214 , IQ2000_F_5, IQ2000_F_10, IQ2000_F_25, IQ2000_F_CAM_Z
215 , IQ2000_F_CAM_Y, IQ2000_F_CM_3FUNC, IQ2000_F_CM_4FUNC, IQ2000_F_CM_3Z
216 , IQ2000_F_CM_4Z, IQ2000_F_MAX
217 } IFIELD_TYPE;
218
219 #define MAX_IFLD ((int) IQ2000_F_MAX)
220
221 /* Hardware attribute indices. */
222
print_dollarhex_cj(cd,dis_info,value,attrs,pc,length)223 /* Enum declaration for cgen_hw attrs. */
224 typedef enum cgen_hw_attr {
225 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
226 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
227 } CGEN_HW_ATTR;
228
229 /* Number of non-boolean elements in cgen_hw_attr. */
230 #define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
231
232 /* Enum declaration for iq2000 hardware types. */
233 typedef enum cgen_hw_type {
234 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
235 , HW_H_IADDR, HW_H_PC, HW_H_GR, HW_MAX
236 } CGEN_HW_TYPE;
237
238 #define MAX_HW ((int) HW_MAX)
print_decimal(cd,dis_info,value,attrs,pc,length)239
240 /* Operand attribute indices. */
241
242 /* Enum declaration for cgen_operand attrs. */
243 typedef enum cgen_operand_attr {
244 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
245 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
246 , CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
247 } CGEN_OPERAND_ATTR;
248
249 /* Number of non-boolean elements in cgen_operand_attr. */
250 #define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
251
252 /* Enum declaration for iq2000 operand types. */
253 typedef enum cgen_operand_type {
254 IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD
255 , IQ2000_OPERAND_RD_RS, IQ2000_OPERAND_RD_RT, IQ2000_OPERAND_RT_RS, IQ2000_OPERAND_SHAMT
256 , IQ2000_OPERAND_IMM, IQ2000_OPERAND_OFFSET, IQ2000_OPERAND_BASEOFF, IQ2000_OPERAND_JMPTARG
257 , IQ2000_OPERAND_MASK, IQ2000_OPERAND_MASKQ10, IQ2000_OPERAND_MASKL, IQ2000_OPERAND_COUNT
258 , IQ2000_OPERAND_F_INDEX, IQ2000_OPERAND_EXECODE, IQ2000_OPERAND_BYTECOUNT, IQ2000_OPERAND_CAM_Y
259 , IQ2000_OPERAND_CAM_Z, IQ2000_OPERAND_CM_3FUNC, IQ2000_OPERAND_CM_4FUNC, IQ2000_OPERAND_CM_3Z
260 , IQ2000_OPERAND_CM_4Z, IQ2000_OPERAND_BASE, IQ2000_OPERAND_MASKR, IQ2000_OPERAND_BITNUM
261 , IQ2000_OPERAND_HI16, IQ2000_OPERAND_LO16, IQ2000_OPERAND_MLO16, IQ2000_OPERAND_JMPTARGQ10
262 , IQ2000_OPERAND_MAX
263 } CGEN_OPERAND_TYPE;
264
265 /* Number of operands types. */
266 #define MAX_OPERANDS 32
267
268 /* Maximum number of operands referenced by any insn. */
269 #define MAX_OPERAND_INSTANCES 8
270
271 /* Insn attribute indices. */
272
273 /* Enum declaration for cgen_insn attrs. */
274 typedef enum cgen_insn_attr {
275 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
ip2k_cgen_print_operand(cd,opindex,xinfo,fields,attrs,pc,length)276 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
277 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_YIELD_INSN, CGEN_INSN_LOAD_DELAY
278 , CGEN_INSN_EVEN_REG_NUM, CGEN_INSN_UNSUPPORTED, CGEN_INSN_USES_RD, CGEN_INSN_USES_RS
279 , CGEN_INSN_USES_RT, CGEN_INSN_USES_R31, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31
280 , CGEN_INSN_MACH, CGEN_INSN_END_NBOOLS
281 } CGEN_INSN_ATTR;
282
283 /* Number of non-boolean elements in cgen_insn_attr. */
284 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
285
286 /* cgen.h uses things we just defined. */
287 #include "opcode/cgen.h"
288
289 /* Attributes. */
290 extern const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[];
291 extern const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[];
292 extern const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[];
293 extern const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[];
294
295 /* Hardware decls. */
296
297 extern CGEN_KEYWORD iq2000_cgen_opval_gr_names;
298
299
300
301
302 #endif /* IQ2000_CPU_H */
303