1 /* Definitions of target machine for GNU compiler. NS32000 version. 2 Copyright (C) 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002 Free Software Foundation, Inc. 4 Contributed by Michael Tiemann (tiemann@cygnus.com) 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING. If not, write to 20 the Free Software Foundation, 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23 24 #define TARGET_CPU_CPP_BUILTINS() \ 25 do \ 26 { \ 27 builtin_define ("__ns32000__"); \ 28 \ 29 /* CPU type */ \ 30 if (TARGET_32532) \ 31 builtin_define ("__ns32532__"); \ 32 else if (TARGET_32332) \ 33 builtin_define ("__ns32332__"); \ 34 else \ 35 builtin_define ("__ns32032__"); \ 36 \ 37 /* FPU type */ \ 38 if (TARGET_32381) \ 39 builtin_define ("__ns32381__"); \ 40 else if (TARGET_32081) \ 41 builtin_define ("__ns32081__"); \ 42 \ 43 /* Misc. */ \ 44 if (TARGET_RTD) \ 45 builtin_define ("__RTD__"); \ 46 \ 47 builtin_assert ("cpu=ns32k"); \ 48 builtin_assert ("machine=ns32k"); \ 49 } \ 50 while (0) 51 52 /* Print subsidiary information on the compiler version in use. */ 53 #define TARGET_VERSION fprintf (stderr, " (32000, GAS syntax)"); 54 55 56 /* ABSOLUTE PREFIX, IMMEDIATE_PREFIX and EXTERNAL_PREFIX can be defined 57 to cover most NS32k addressing syntax variations. This way we don't 58 need to redefine long macros in all the tm.h files for just slight 59 variations in assembler syntax. */ 60 61 #ifndef ABSOLUTE_PREFIX 62 #define ABSOLUTE_PREFIX '@' 63 #endif 64 65 #if defined(IMMEDIATE_PREFIX) && IMMEDIATE_PREFIX 66 #define PUT_IMMEDIATE_PREFIX(FILE) putc(IMMEDIATE_PREFIX, FILE) 67 #else 68 #define PUT_IMMEDIATE_PREFIX(FILE) 69 #endif 70 #if defined(ABSOLUTE_PREFIX) && ABSOLUTE_PREFIX 71 #define PUT_ABSOLUTE_PREFIX(FILE) putc(ABSOLUTE_PREFIX, FILE) 72 #else 73 #define PUT_ABSOLUTE_PREFIX(FILE) 74 #endif 75 #if defined(EXTERNAL_PREFIX) && EXTERNAL_PREFIX 76 #define PUT_EXTERNAL_PREFIX(FILE) putc(EXTERNAL_PREFIX, FILE) 77 #else 78 #define PUT_EXTERNAL_PREFIX(FILE) 79 #endif 80 81 /* Run-time compilation parameters selecting different hardware subsets. */ 82 83 extern int target_flags; 84 85 /* Masks for target_flags */ 86 #define MASK_32081 1 87 #define MASK_RTD 2 88 #define MASK_REGPARM 4 89 #define MASK_32532 8 90 #define MASK_32332 16 91 #define MASK_NO_SB 32 92 #define MASK_NO_BITFIELD 64 93 #define MASK_HIMEM 128 94 #define MASK_32381 256 95 #define MASK_MULT_ADD 512 96 #define MASK_SRC 1024 97 #define MASK_IEEE_COMPARE 2048 98 99 /* Macros used in the machine description to test the flags. */ 100 101 /* Compile 32081 insns for floating point (not library calls). */ 102 #define TARGET_32081 (target_flags & MASK_32081) 103 #define TARGET_32381 (target_flags & MASK_32381) 104 105 /* The use of multiply-add instructions is optional because there may 106 * be cases where it produces worse code. 107 */ 108 109 #define TARGET_MULT_ADD (target_flags & MASK_MULT_ADD) 110 111 /* Compile using rtd insn calling sequence. 112 This will not work unless you use prototypes at least 113 for all functions that can take varying numbers of args. */ 114 #define TARGET_RTD (target_flags & MASK_RTD) 115 116 /* Compile passing first two args in regs 0 and 1. */ 117 #define TARGET_REGPARM (target_flags & MASK_REGPARM) 118 119 /* Options to select type of CPU, for better optimization. 120 The output is correct for any kind of 32000 regardless of these options. */ 121 #define TARGET_32532 (target_flags & MASK_32532) 122 #define TARGET_32332 (target_flags & MASK_32332) 123 124 /* Ok to use the static base register (and presume it's 0) */ 125 #define TARGET_SB ((target_flags & MASK_NO_SB) == 0) 126 127 #define TARGET_HIMEM (target_flags & MASK_HIMEM) 128 129 /* Compile using bit-field insns. */ 130 #define TARGET_BITFIELD ((target_flags & MASK_NO_BITFIELD) == 0) 131 132 #define TARGET_IEEE_COMPARE (target_flags & MASK_IEEE_COMPARE) 133 134 /* Macro to define tables used to set the flags. 135 This is a list in braces of pairs in braces, 136 each pair being { "NAME", VALUE } 137 where VALUE is the bits to set or minus the bits to clear. 138 An empty string NAME is used to identify the default VALUE. */ 139 #define TARGET_SWITCHES \ 140 { { "32081", MASK_32081, N_("Use hardware fp")}, \ 141 { "soft-float", -(MASK_32081|MASK_32381), \ 142 N_("Don't use hardware fp")}, \ 143 { "rtd", MASK_RTD, N_("Alternative calling convention")}, \ 144 { "nortd", -MASK_RTD, N_("Use normal calling convention")}, \ 145 { "regparm", MASK_REGPARM, N_("Pass some arguments in registers")}, \ 146 { "noregparm", -MASK_REGPARM, N_("Pass all arguments on stack")}, \ 147 { "32532", MASK_32532|MASK_32332, N_("Optimize for 32532 cpu")}, \ 148 { "32332", MASK_32332, N_("Optimize for 32332 cpu")}, \ 149 { "32332", -MASK_32532, 0}, \ 150 { "32032", -(MASK_32532|MASK_32332), N_("Optimize for 32032")}, \ 151 { "sb", -MASK_NO_SB, \ 152 N_("Register sb is zero. Use for absolute addressing")}, \ 153 { "nosb", MASK_NO_SB, N_("Do not use register sb")}, \ 154 { "bitfield", -MASK_NO_BITFIELD, \ 155 N_("Use bit-field instructions")}, \ 156 { "nobitfield", MASK_NO_BITFIELD, \ 157 N_("Do not use bit-field instructions")}, \ 158 { "himem", MASK_HIMEM, N_("Generate code for high memory")}, \ 159 { "nohimem", -MASK_HIMEM, N_("Generate code for low memory")}, \ 160 { "32381", MASK_32381, N_("32381 fpu")}, \ 161 { "mult-add", MASK_MULT_ADD, \ 162 N_("Use multiply-accumulate fp instructions")}, \ 163 { "nomult-add", -MASK_MULT_ADD, \ 164 N_("Do not use multiply-accumulate fp instructions") }, \ 165 { "src", MASK_SRC, N_("\"Small register classes\" kludge")}, \ 166 { "nosrc", -MASK_SRC, N_("No \"Small register classes\" kludge")}, \ 167 { "ieee-compare", MASK_IEEE_COMPARE, N_("Use IEEE math for fp comparisons")}, \ 168 { "noieee-compare", -MASK_IEEE_COMPARE, \ 169 N_("Do not use IEEE math for fp comparisons")}, \ 170 { "", TARGET_DEFAULT, 0}} 171 172 /* TARGET_DEFAULT is defined in encore.h, pc532.h, etc. */ 173 174 /* When we are generating PIC, the sb is used as a pointer 175 to the GOT. 32381 is a superset of 32081 */ 176 177 #define OVERRIDE_OPTIONS \ 178 { \ 179 if (target_flags & MASK_32532) \ 180 target_flags |= MASK_32332; \ 181 if (flag_pic || TARGET_HIMEM) \ 182 target_flags |= MASK_NO_SB; \ 183 if (TARGET_32381) \ 184 target_flags |= MASK_32081; \ 185 else \ 186 target_flags &= ~MASK_MULT_ADD; \ 187 if (flag_unsafe_math_optimizations) \ 188 target_flags &= ~MASK_IEEE_COMPARE; \ 189 } 190 191 /* Zero or more C statements that may conditionally modify two 192 variables `fixed_regs' and `call_used_regs' (both of type `char 193 []') after they have been initialized from the two preceding 194 macros. 195 196 This is necessary in case the fixed or call-clobbered registers 197 depend on target flags. 198 199 You need not define this macro if it has no work to do. 200 201 If the usage of an entire class of registers depends on the target 202 flags, you may indicate this to GCC by using this macro to modify 203 `fixed_regs' and `call_used_regs' to 1 for each of the registers in 204 the classes which should not be used by GCC. Also define the macro 205 `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a 206 letter for a class that shouldn't be used. 207 208 (However, if this class is not included in `GENERAL_REGS' and all 209 of the insn patterns whose constraints permit this class are 210 controlled by target switches, then GCC will automatically avoid 211 using these registers when the target switches are opposed to 212 them.) */ 213 214 #define CONDITIONAL_REGISTER_USAGE \ 215 do \ 216 { \ 217 if (!TARGET_32081) \ 218 { \ 219 int regno; \ 220 \ 221 for (regno = F0_REGNUM; regno <= F0_REGNUM + 8; regno++) \ 222 fixed_regs[regno] = call_used_regs[regno] = 1; \ 223 } \ 224 if (!TARGET_32381) \ 225 { \ 226 int regno; \ 227 \ 228 for (regno = L1_REGNUM; regno <= L1_REGNUM + 8; regno++) \ 229 fixed_regs[regno] = call_used_regs[regno] = 1; \ 230 } \ 231 } \ 232 while (0) 233 234 235 /* target machine storage layout */ 236 237 /* Define this if most significant bit is lowest numbered 238 in instructions that operate on numbered bit-fields. 239 This is not true on the ns32k. */ 240 #define BITS_BIG_ENDIAN 0 241 242 /* Define this if most significant byte of a word is the lowest numbered. */ 243 /* That is not true on the ns32k. */ 244 #define BYTES_BIG_ENDIAN 0 245 246 /* Define this if most significant word of a multiword number is lowest 247 numbered. This is not true on the ns32k. */ 248 #define WORDS_BIG_ENDIAN 0 249 250 /* Width of a word, in units (bytes). */ 251 #define UNITS_PER_WORD 4 252 253 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 254 #define PARM_BOUNDARY 32 255 256 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 257 #define STACK_BOUNDARY 32 258 259 /* Allocation boundary (in *bits*) for the code of a function. */ 260 #define FUNCTION_BOUNDARY 16 261 262 /* Alignment of field after `int : 0' in a structure. */ 263 #define EMPTY_FIELD_BOUNDARY 32 264 265 /* Every structure's size must be a multiple of this. */ 266 #define STRUCTURE_SIZE_BOUNDARY 8 267 268 /* No data type wants to be aligned rounder than this. */ 269 #define BIGGEST_ALIGNMENT 32 270 271 /* Set this nonzero if move instructions will actually fail to work 272 when given unaligned data. National claims that the NS32032 273 works without strict alignment, but rumor has it that operands 274 crossing a page boundary cause unpredictable results. */ 275 #define STRICT_ALIGNMENT 1 276 277 /* If bit field type is int, don't let it cross an int, 278 and give entire struct the alignment of an int. */ 279 /* Required on the 386 since it doesn't have a full set of bit-field insns. 280 (There is no signed extv insn.) */ 281 #define PCC_BITFIELD_TYPE_MATTERS 1 282 283 /* Standard register usage. */ 284 285 /* Number of actual hardware registers. 286 The hardware registers are assigned numbers for the compiler 287 from 0 to just below FIRST_PSEUDO_REGISTER. 288 All registers that the compiler knows about must be given numbers, 289 even those that are not normally considered general registers. */ 290 #define FIRST_PSEUDO_REGISTER 26 291 292 /* 1 for registers that have pervasive standard uses 293 and are not available for the register allocator. 294 On the ns32k, these are the FP, SP, (SB and PC are not included here). */ 295 #define FIXED_REGISTERS {0, 0, 0, 0, 0, 0, 0, 0, \ 296 0, 0, 0, 0, 0, 0, 0, 0, \ 297 0, 0, 0, 0, 0, 0, 0, 0, \ 298 1, 1} 299 300 /* 1 for registers not available across function calls. 301 These must include the FIXED_REGISTERS and also any 302 registers that can be used without being saved. 303 The latter must include the registers where values are returned 304 and the register where structure-value addresses are passed. 305 Aside from that, you can include as many other registers as you like. */ 306 #define CALL_USED_REGISTERS {1, 1, 1, 0, 0, 0, 0, 0, \ 307 1, 1, 1, 1, 0, 0, 0, 0, \ 308 1, 1, 0, 0, 0, 0, 0, 0, \ 309 1, 1} 310 311 /* How to refer to registers in assembler output. 312 This sequence is indexed by compiler's hard-register-number (see above). */ 313 314 #define REGISTER_NAMES \ 315 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 316 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 317 "l1", "l1h","l3", "l3h","l5", "l5h","l7", "l7h", \ 318 "fp", "sp"} 319 320 321 #define ADDITIONAL_REGISTER_NAMES \ 322 {{"l0", 8}, {"l2", 10}, {"l4", 12}, {"l6", 14}} 323 324 /* l0-7 are not recognized by the assembler. These are the names to use, 325 * but we don't want ambiguous names in REGISTER_NAMES 326 */ 327 #define OUTPUT_REGISTER_NAMES \ 328 {"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 329 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 330 "f1", "l1h","f3", "l3h","f5", "l5h","f7", "f7h", \ 331 "fp", "sp"} 332 333 #define REG_ALLOC_ORDER \ 334 {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 10, 11, 18, 12, 13, 20, 14, 15, 22, 24, 25, 17, 19, 23} 335 336 /* How to renumber registers for dbx and gdb. 337 NS32000 may need more change in the numeration. XXX */ 338 339 #define DBX_REGISTER_NUMBER(REGNO) \ 340 ((REGNO) < L1_REGNUM? (REGNO) \ 341 : (REGNO) < FRAME_POINTER_REGNUM? (REGNO) - L1_REGNUM + 22 \ 342 : (REGNO) == FRAME_POINTER_REGNUM? 17 \ 343 : 16) 344 345 /* dwarf2out.c can't understand the funny DBX register numbering. 346 * We use dwarf2out.c for exception handling even though we use DBX 347 * for debugging 348 */ 349 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) 350 351 352 353 #define R0_REGNUM 0 354 #define F0_REGNUM 8 355 #define L1_REGNUM 16 356 357 /* Specify the registers used for certain standard purposes. 358 The values of these macros are register numbers. */ 359 360 /* NS32000 pc is not overloaded on a register. */ 361 /* #define PC_REGNUM */ 362 363 /* Register to use for pushing function arguments. */ 364 #define STACK_POINTER_REGNUM 25 365 366 /* Base register for access to local variables of the function. */ 367 #define FRAME_POINTER_REGNUM 24 368 369 370 /* Return number of consecutive hard regs needed starting at reg REGNO 371 to hold something of mode MODE. 372 This is ordinarily the length in words of a value of mode MODE 373 but can be less for certain modes in special long registers. 374 On the ns32k, all registers are 32 bits long except for the 32381 "long" 375 registers but we treat those as pairs */ 376 #define LONG_FP_REGS_P(REGNO) ((REGNO) >= L1_REGNUM && (REGNO) < L1_REGNUM + 8) 377 #define HARD_REGNO_NREGS(REGNO, MODE) \ 378 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 379 380 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 381 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok (REGNO, MODE) 382 383 /* Value is 1 if it is a good idea to tie two pseudo registers 384 when one has mode MODE1 and one has mode MODE2. 385 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 386 for any hard reg, then this must be 0 for correct output. */ 387 388 #define MODES_TIEABLE_P(MODE1, MODE2) \ 389 ((FLOAT_MODE_P(MODE1) && FLOAT_MODE_P(MODE2) \ 390 && (GET_MODE_UNIT_SIZE(MODE1) == GET_MODE_UNIT_SIZE(MODE2))) \ 391 || (!FLOAT_MODE_P(MODE1) && !FLOAT_MODE_P(MODE2))) 392 393 /* Value should be nonzero if functions must have frame pointers. 394 Zero means the frame pointer need not be set up (and parms 395 may be accessed via the stack pointer) in functions that seem suitable. 396 This is computed in `reload', in reload1.c. */ 397 #define FRAME_POINTER_REQUIRED 0 398 399 /* Base register for access to arguments of the function. */ 400 #define ARG_POINTER_REGNUM 24 401 402 /* Register in which static-chain is passed to a function. */ 403 #define STATIC_CHAIN_REGNUM 1 404 405 /* Register in which address to store a structure value 406 is passed to a function. */ 407 #define STRUCT_VALUE_REGNUM 2 408 409 /* Define the classes of registers for register constraints in the 410 machine description. Also define ranges of constants. 411 412 One of the classes must always be named ALL_REGS and include all hard regs. 413 If there is more than one class, another class must be named NO_REGS 414 and contain no registers. 415 416 The name GENERAL_REGS must be the name of a class (or an alias for 417 another name such as ALL_REGS). This is the class of registers 418 that is allowed by "g" or "r" in a register constraint. 419 Also, registers outside this class are allocated only when 420 instructions express preferences for them. 421 422 The classes must be numbered in nondecreasing order; that is, 423 a larger-numbered class must never be contained completely 424 in a smaller-numbered class. 425 426 For any two classes, it is very desirable that there be another 427 class that represents their union. */ 428 429 enum reg_class 430 { NO_REGS, GENERAL_REGS, FLOAT_REG0, LONG_FLOAT_REG0, FLOAT_REGS, 431 LONG_REGS, FP_REGS, GEN_AND_FP_REGS, FRAME_POINTER_REG, 432 STACK_POINTER_REG, GEN_AND_MEM_REGS, ALL_REGS, LIM_REG_CLASSES }; 433 434 #define N_REG_CLASSES (int) LIM_REG_CLASSES 435 436 /* Give names of register classes as strings for dump file. */ 437 438 #define REG_CLASS_NAMES \ 439 {"NO_REGS", "GENERAL_REGS", "FLOAT_REG0", "LONG_FLOAT_REG0", "FLOAT_REGS", \ 440 "LONG_REGS", "FP_REGS", "GEN_AND_FP_REGS", "FRAME_POINTER_REG", \ 441 "STACK_POINTER_REG", "GEN_AND_MEM_REGS", "ALL_REGS" } 442 443 /* Define which registers fit in which classes. 444 This is an initializer for a vector of HARD_REG_SET 445 of length N_REG_CLASSES. */ 446 447 #define REG_CLASS_CONTENTS \ 448 {{0}, /* NO_REGS */ \ 449 {0x00ff}, /* GENERAL_REGS */ \ 450 {0x100}, /* FLOAT_REG0 */ \ 451 {0x300}, /* LONG_FLOAT_REG0 */ \ 452 {0xff00}, /* FLOAT_REGS */ \ 453 {0xff0000}, /* LONG_REGS */ \ 454 {0xffff00}, /* FP_REGS */ \ 455 {0xffffff}, /* GEN_AND_FP_REGS */ \ 456 {0x1000000}, /* FRAME_POINTER_REG */ \ 457 {0x2000000}, /* STACK_POINTER_REG */ \ 458 {0x30000ff}, /* GEN_AND_MEM_REGS */ \ 459 {0x3ffffff} /* ALL_REGS */ \ 460 } 461 462 #define SUBSET_P(CLASS1, CLASS2) \ 463 ((ns32k_reg_class_contents[CLASS1][0] \ 464 & ~ns32k_reg_class_contents[CLASS2][0]) == 0) 465 466 467 /* LONG_REGS are registers which can only hold double precision floats 468 * and can only be accessible by long float instructions. 469 */ 470 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 471 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 472 ? reg_classes_intersect_p (LONG_REGS, CLASS) : 0) 473 474 /* The same information, inverted: 475 Return the class number of the smallest class containing 476 reg number REGNO. This could be a conditional expression 477 or could index an array. */ 478 479 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 480 481 /* The class value for index registers, and the one for base regs. */ 482 483 #define INDEX_REG_CLASS GENERAL_REGS 484 #define BASE_REG_CLASS GEN_AND_MEM_REGS 485 486 /* Get reg_class from a letter such as appears in the machine description. */ 487 488 #define REG_CLASS_FROM_LETTER(C) \ 489 ((C) == 'u' ? FLOAT_REG0 \ 490 : (C) == 'v' ? LONG_FLOAT_REG0 \ 491 : (C) == 'f' ? FLOAT_REGS \ 492 : (C) == 'l' ? FP_REGS \ 493 : (C) == 'x' ? FRAME_POINTER_REG \ 494 : (C) == 'y' ? STACK_POINTER_REG \ 495 : NO_REGS) 496 497 /* The letters I, J, K, L and M in a register constraint string 498 can be used to stand for particular ranges of immediate operands. 499 This macro defines what the ranges are. 500 C is the letter, and VALUE is a constant value. 501 Return 1 if VALUE is in the range specified by C. 502 503 On the ns32k, these letters are used as follows: 504 505 I : Matches integers which are valid shift amounts for scaled indexing. 506 These are 0, 1, 2, 3 for byte, word, double, and quadword. 507 Used for matching arithmetic shifts only on 32032 & 32332. 508 J : Matches integers which fit a "quick" operand. 509 K : Matches integers 0 to 7 (for inss and exts instructions). 510 */ 511 512 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 513 ((VALUE) < 8 && (VALUE) + 8 >= 0 ? \ 514 ((C) == 'I' ? (!TARGET_32532 && 0 <= (VALUE) && (VALUE) <= 3) : \ 515 (C) == 'J' ? (VALUE) <= 7 : \ 516 (C) == 'K' ? 0 <= (VALUE) : 0) : 0) 517 518 /* Similar, but for floating constants, and defining letters G and H. 519 Here VALUE is the CONST_DOUBLE rtx itself. */ 520 521 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) 1 522 523 /* Given an rtx X being reloaded into a reg required to be 524 in class CLASS, return the class of reg to actually use. 525 In general this is just CLASS; but on some machines 526 in some cases it is preferable to use a more restrictive class. */ 527 528 /* We return GENERAL_REGS instead of GEN_AND_MEM_REGS. 529 The latter offers no real additional possibilities 530 and can cause spurious secondary reloading. */ 531 532 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 533 ((CLASS) == GEN_AND_MEM_REGS ? GENERAL_REGS : (CLASS)) 534 535 /* Return the maximum number of consecutive registers 536 needed to represent mode MODE in a register of class CLASS. */ 537 /* On the 32000, this is the size of MODE in words */ 538 539 #define CLASS_MAX_NREGS(CLASS, MODE) \ 540 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 541 542 /* Stack layout; function entry, exit and calling. */ 543 544 /* Define this if pushing a word on the stack 545 makes the stack pointer a smaller address. */ 546 #define STACK_GROWS_DOWNWARD 547 548 /* Define this if the nominal address of the stack frame 549 is at the high-address end of the local variables; 550 that is, each additional local variable allocated 551 goes at a more negative offset in the frame. */ 552 #define FRAME_GROWS_DOWNWARD 553 554 /* Offset within stack frame to start allocating local variables at. 555 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 556 first local allocated. Otherwise, it is the offset to the BEGINNING 557 of the first local allocated. */ 558 #define STARTING_FRAME_OFFSET 0 559 560 /* A C expression whose value is RTL representing the location of the 561 incoming return address at the beginning of any function, before 562 the prologue. This RTL is either a `REG', indicating that the 563 return value is saved in `REG', or a `MEM' representing a location 564 in the stack. 565 566 You only need to define this macro if you want to support call 567 frame debugging information like that provided by DWARF 2. 568 569 Before the prologue, RA is at 0(sp). */ 570 571 #define INCOMING_RETURN_ADDR_RTX \ 572 gen_rtx (MEM, VOIDmode, gen_rtx (REG, VOIDmode, STACK_POINTER_REGNUM)) 573 574 /* A C expression whose value is RTL representing the value of the 575 return address for the frame COUNT steps up from the current frame, 576 after the prologue. FRAMEADDR is the frame pointer of the COUNT 577 frame, or the frame pointer of the COUNT - 1 frame if 578 `RETURN_ADDR_IN_PREVIOUS_FRAME' is defined. 579 580 After the prologue, RA is at 4(fp) in the current frame. */ 581 582 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 583 ((COUNT> 0 && flag_omit_frame_pointer)? NULL_RTX \ 584 : gen_rtx (MEM, Pmode, gen_rtx (PLUS, Pmode, (FRAME), GEN_INT(4)))) 585 586 /* A C expression whose value is an integer giving the offset, in 587 bytes, from the value of the stack pointer register to the top of 588 the stack frame at the beginning of any function, before the 589 prologue. The top of the frame is defined to be the value of the 590 stack pointer in the previous frame, just before the call 591 instruction. 592 593 You only need to define this macro if you want to support call 594 frame debugging information like that provided by DWARF 2. */ 595 596 #define INCOMING_FRAME_SP_OFFSET 4 597 598 /* If we generate an insn to push BYTES bytes, 599 this says how many the stack pointer really advances by. 600 On the 32000, sp@- in a byte insn really pushes a BYTE. */ 601 #define PUSH_ROUNDING(BYTES) (BYTES) 602 603 /* Offset of first parameter from the argument pointer register value. */ 604 #define FIRST_PARM_OFFSET(FNDECL) 8 605 606 /* Value is the number of byte of arguments automatically 607 popped when returning from a subroutine call. 608 FUNDECL is the declaration node of the function (as a tree), 609 FUNTYPE is the data type of the function (as a tree), 610 or for a library call it is an identifier node for the subroutine name. 611 SIZE is the number of bytes of arguments passed on the stack. 612 613 On the 32000, the RET insn may be used to pop them if the number 614 of args is fixed, but if the number is variable then the caller 615 must pop them all. RET can't be used for library calls now 616 because the library is compiled with the Unix compiler. 617 Use of RET is a selectable option, since it is incompatible with 618 standard Unix calling sequences. If the option is not selected, 619 the caller must always pop the args. 620 621 The attribute stdcall is equivalent to RTD on a per module basis. */ 622 623 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ 624 (ns32k_return_pops_args (FUNDECL, FUNTYPE, SIZE)) 625 626 /* Define how to find the value returned by a function. 627 VALTYPE is the data type of the value (as a tree). 628 If the precise function being called is known, FUNC is its FUNCTION_DECL; 629 otherwise, FUNC is 0. */ 630 631 /* On the 32000 the return value is in R0, 632 or perhaps in F0 if there is fp support. */ 633 634 #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE(TYPE_MODE (VALTYPE)) 635 636 /* Define how to find the value returned by a library function 637 assuming the value has mode MODE. */ 638 639 /* On the 32000 the return value is in R0, 640 or perhaps F0 is there is fp support. */ 641 642 #define LIBCALL_VALUE(MODE) \ 643 gen_rtx_REG (MODE, \ 644 FLOAT_MODE_P(MODE) && TARGET_32081 ? F0_REGNUM: R0_REGNUM) 645 646 /* Define this if PCC uses the nonreentrant convention for returning 647 structure and union values. */ 648 649 #define PCC_STATIC_STRUCT_RETURN 650 651 /* 1 if N is a possible register number for a function value. 652 On the 32000, R0 and F0 are the only registers thus used. */ 653 654 #define FUNCTION_VALUE_REGNO_P(N) (((N) & ~8) == 0) 655 656 /* 1 if N is a possible register number for function argument passing. 657 On the 32000, no registers are used in this way. */ 658 659 #define FUNCTION_ARG_REGNO_P(N) 0 660 661 /* Define a data type for recording info about an argument list 662 during the scan of that argument list. This data type should 663 hold all necessary information about the function itself 664 and about the args processed so far, enough to enable macros 665 such as FUNCTION_ARG to determine where the next arg should go. 666 667 On the ns32k, this is a single integer, which is a number of bytes 668 of arguments scanned so far. */ 669 670 #define CUMULATIVE_ARGS int 671 672 /* Initialize a variable CUM of type CUMULATIVE_ARGS 673 for a call to a function whose data type is FNTYPE. 674 For a library call, FNTYPE is 0. 675 676 On the ns32k, the offset starts at 0. */ 677 678 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 679 ((CUM) = 0) 680 681 /* Update the data in CUM to advance over an argument 682 of mode MODE and data type TYPE. 683 (TYPE is null for libcalls where that information may not be available.) */ 684 685 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 686 ((CUM) += ((MODE) != BLKmode \ 687 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 688 : (int_size_in_bytes (TYPE) + 3) & ~3)) 689 690 /* Define where to put the arguments to a function. 691 Value is zero to push the argument on the stack, 692 or a hard register in which to store the argument. 693 694 MODE is the argument's machine mode. 695 TYPE is the data type of the argument (as a tree). 696 This is null for libcalls where that information may 697 not be available. 698 CUM is a variable of type CUMULATIVE_ARGS which gives info about 699 the preceding args and about the function being called. 700 NAMED is nonzero if this argument is a named parameter 701 (otherwise it is an extra parameter matching an ellipsis). */ 702 703 /* On the 32000 all args are pushed, except if -mregparm is specified 704 then the first two words of arguments are passed in r0, r1. 705 *NOTE* -mregparm does not work. 706 It exists only to test register calling conventions. */ 707 708 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 709 ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx_REG ((MODE), (CUM) / 4) : 0) 710 711 /* For an arg passed partly in registers and partly in memory, 712 this is the number of registers used. 713 For args passed entirely in registers or entirely in memory, zero. */ 714 715 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 716 ((TARGET_REGPARM && (CUM) < 8 \ 717 && 8 < ((CUM) + ((MODE) == BLKmode \ 718 ? int_size_in_bytes (TYPE) \ 719 : GET_MODE_SIZE (MODE)))) \ 720 ? 2 - (CUM) / 4 : 0) 721 722 /* Output assembler code to FILE to increment profiler label # LABELNO 723 for profiling a function entry. 724 725 THIS DEFINITION FOR THE 32000 IS A GUESS. IT HAS NOT BEEN TESTED. */ 726 727 #define FUNCTION_PROFILER(FILE, LABELNO) \ 728 fprintf (FILE, "\taddr LP%d,r0\n\tbsr mcount\n", (LABELNO)) 729 730 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 731 the stack pointer does not matter. The value is tested only in 732 functions that have frame pointers. 733 No definition is equivalent to always zero. 734 735 We use 0, because using 1 requires hair in output_function_epilogue() 736 that is worse than the stack adjust we could save. */ 737 738 /* #define EXIT_IGNORE_STACK 1 */ 739 740 /* Store in the variable DEPTH the initial difference between the 741 frame pointer reg contents and the stack pointer reg contents, 742 as of the start of the function body. This depends on the layout 743 of the fixed parts of the stack frame and on how registers are saved. */ 744 745 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ 746 { \ 747 int regno; \ 748 int offset = -4; \ 749 for (regno = 0; regno < FRAME_POINTER_REGNUM; regno++) \ 750 if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 751 offset += 4; \ 752 if (flag_pic && current_function_uses_pic_offset_table) \ 753 offset += 4; \ 754 (DEPTH) = (offset + get_frame_size () \ 755 + (get_frame_size () == 0 ? 0 : 4)); \ 756 } 757 758 759 /* Output assembler code for a block containing the constant parts 760 of a trampoline, leaving space for the variable parts. */ 761 762 /* On the 32k, the trampoline looks like this: 763 764 addr 0(pc),r2 765 movd 16(r2),tos 766 movd 12(r2),r1 767 ret 0 768 .align 4 769 .int STATIC 770 .int FUNCTION 771 772 Putting the data in following data is easier than figuring out how to 773 do stores to memory in reverse byte order (the way immediate operands 774 on the 32k are stored). */ 775 776 #define TRAMPOLINE_TEMPLATE(FILE) \ 777 { \ 778 fprintf (FILE, "\taddr 0(pc),r2\n"); \ 779 fprintf (FILE, "\tmovd 16(r2),tos\n"); \ 780 fprintf (FILE, "\tmovd 12(r2),r1\n"); \ 781 fprintf (FILE, "\tret 0\n"); \ 782 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 783 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); \ 784 } 785 786 /* Length in units of the trampoline for entering a nested function. */ 787 788 #define TRAMPOLINE_SIZE 20 789 790 /* Emit RTL insns to initialize the variable parts of a trampoline. 791 FNADDR is an RTX for the address of the function's pure code. 792 CXT is an RTX for the static chain value for the function. */ 793 794 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 795 { \ 796 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 12)), CXT); \ 797 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (TRAMP, 16)), FNADDR); \ 798 } 799 800 /* Addressing modes, and classification of registers for them. */ 801 802 /* Macros to check register numbers against specific register classes. */ 803 804 /* These assume that REGNO is a hard or pseudo reg number. 805 They give nonzero only if REGNO is a hard reg of the suitable class 806 or a pseudo reg currently allocated to a suitable hard reg. 807 Since they use reg_renumber, they are safe only once reg_renumber 808 has been allocated, which happens in local-alloc.c. */ 809 810 /* note that FP and SP cannot be used as an index. What about PC? */ 811 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 812 ((REGNO) < F0_REGNUM || (unsigned)reg_renumber[REGNO] < F0_REGNUM) 813 #define REGNO_OK_FOR_BASE_P(REGNO) \ 814 ((REGNO) < F0_REGNUM || (unsigned)reg_renumber[REGNO] < F0_REGNUM \ 815 || (REGNO) == FRAME_POINTER_REGNUM || (REGNO) == STACK_POINTER_REGNUM) 816 817 #define FP_REG_P(X) \ 818 (GET_CODE (X) == REG && REGNO (X) >= F0_REGNUM && REGNO (X) < FRAME_POINTER_REGNUM) 819 820 /* Maximum number of registers that can appear in a valid memory address. */ 821 822 #define MAX_REGS_PER_ADDRESS 2 823 824 /* Recognize any constant value that is a valid address. 825 This might not work on future ns32k processors as negative 826 displacements are not officially allowed but a mode reserved 827 to National. This works on processors up to 32532, though, 828 and we don't expect any new ones in the series ;-( */ 829 830 #define CONSTANT_ADDRESS_P(X) \ 831 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 832 || GET_CODE (X) == CONST \ 833 || (GET_CODE (X) == CONST_INT \ 834 && NS32K_DISPLACEMENT_P (INTVAL (X)))) 835 836 #define CONSTANT_ADDRESS_NO_LABEL_P(X) \ 837 (GET_CODE (X) == CONST_INT \ 838 && NS32K_DISPLACEMENT_P (INTVAL (X))) 839 840 /* Return the register class of a scratch register needed to copy IN into 841 or out of a register in CLASS in MODE. If it can be done directly, 842 NO_REGS is returned. */ 843 844 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 845 secondary_reload_class (CLASS, MODE, IN) 846 847 /* Certain machines have the property that some registers cannot be 848 copied to some other registers without using memory. Define this 849 macro on those machines to be a C expression that is nonzero if 850 objects of mode M in registers of CLASS1 can only be copied to 851 registers of class CLASS2 by storing a register of CLASS1 into 852 memory and loading that memory location into a register of CLASS2. 853 854 On the ns32k, floating point regs can only be loaded through memory 855 856 The movdf and movsf insns in ns32k.md copy between general and 857 floating registers using the stack. In principle, we could get 858 better code not allowing that case in the constraints and defining 859 SECONDARY_MEMORY_NEEDED in practice, though the stack slots used 860 are not available for optimization. */ 861 862 #if 0 863 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, M) \ 864 secondary_memory_needed(CLASS1, CLASS2, M) 865 #endif 866 867 /* SMALL_REGISTER_CLASSES is a run time option. This should no longer 868 be necessary and should go when we have confidence that we won't run 869 out of spill registers */ 870 #define SMALL_REGISTER_CLASSES (target_flags & MASK_SRC) 871 872 /* A C expression whose value is nonzero if pseudos that have been 873 assigned to registers of class CLASS would likely be spilled 874 because registers of CLASS are needed for spill registers. 875 876 The default definition won't do because class LONG_FLOAT_REG0 has two 877 registers which are always accessed as a pair */ 878 879 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 880 (reg_class_size[(int) (CLASS)] == 1 || (CLASS) == LONG_FLOAT_REG0) 881 882 883 /* Nonzero if the constant value X is a legitimate general operand. 884 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 885 886 #define LEGITIMATE_CONSTANT_P(X) 1 887 888 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 889 and check its validity for a certain class. 890 We have two alternate definitions for each of them. 891 The usual definition accepts all pseudo regs; the other rejects 892 them unless they have been allocated suitable hard regs. 893 The symbol REG_OK_STRICT causes the latter definition to be used. 894 895 Most source files want to accept pseudo regs in the hope that 896 they will get allocated to the class that the insn wants them to be in. 897 Source files for reload pass need to be strict. 898 After reload, it makes no difference, since pseudo regs have 899 been eliminated by then. */ 900 901 #ifndef REG_OK_STRICT 902 903 /* Nonzero if X is a hard reg that can be used as an index 904 or if it is a pseudo reg. */ 905 #define REG_OK_FOR_INDEX_P(X) \ 906 (REGNO (X) < F0_REGNUM || REGNO (X) >= FIRST_PSEUDO_REGISTER) 907 /* Nonzero if X is a hard reg that can be used as a base reg 908 of if it is a pseudo reg. */ 909 #define REG_OK_FOR_BASE_P(X) (REGNO (X) < F0_REGNUM || REGNO (X) >= FRAME_POINTER_REGNUM) 910 /* Nonzero if X is a floating point reg or a pseudo reg. */ 911 912 #else 913 914 /* Nonzero if X is a hard reg that can be used as an index. */ 915 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 916 /* Nonzero if X is a hard reg that can be used as a base reg. */ 917 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 918 919 #endif 920 921 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 922 that is a valid memory address for an instruction. 923 The MODE argument is the machine mode for the MEM expression 924 that wants to use this address. 925 926 The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 927 928 /* 1 if X is an address that we could indirect through. */ 929 /***** NOTE ***** There is a bug in the Sequent assembler which fails 930 to fixup addressing information for symbols used as offsets 931 from registers which are not FP or SP (or SB or PC). This 932 makes _x(fp) valid, while _x(r0) is invalid. */ 933 934 #define INDIRECTABLE_1_ADDRESS_P(X) \ 935 (CONSTANT_ADDRESS_P (X) \ 936 || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 937 || (GET_CODE (X) == PLUS \ 938 && GET_CODE (XEXP (X, 0)) == REG \ 939 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ 940 && ((flag_pic || TARGET_HIMEM) ? \ 941 CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1)) \ 942 : \ 943 CONSTANT_ADDRESS_P (XEXP (X, 1))) \ 944 && (GET_CODE (X) != CONST_INT || NS32K_DISPLACEMENT_P (INTVAL (X))))) 945 946 /* 1 if integer I will fit in a 4 byte displacement field. 947 Strictly speaking, we can't be sure that a symbol will fit this range. 948 But, in practice, it always will. */ 949 950 /* idall@eleceng.adelaide.edu.au says that the 32016 and 32032 951 can handle the full range of displacements--it is only the addresses 952 that have a limited range. So the following was deleted: 953 (((i) <= 16777215 && (i) >= -16777216) 954 || ((TARGET_32532 || TARGET_32332) && ...)) */ 955 #define NS32K_DISPLACEMENT_P(i) \ 956 ((i) < (1 << 29) && (i) >= - (1 << 29)) 957 958 /* Check for frame pointer or stack pointer. */ 959 #define MEM_REG(X) \ 960 (GET_CODE (X) == REG && (REGNO (X) == FRAME_POINTER_REGNUM \ 961 || REGNO(X) == STACK_POINTER_REGNUM)) 962 963 /* A memory ref whose address is the FP or SP, with optional integer offset, 964 or (on certain machines) a constant address. */ 965 #define INDIRECTABLE_2_ADDRESS_P(X) \ 966 (GET_CODE (X) == MEM \ 967 && (((xfoo0 = XEXP (X, 0), MEM_REG (xfoo0)) \ 968 || (GET_CODE (xfoo0) == PLUS \ 969 && MEM_REG (XEXP (xfoo0, 0)) \ 970 && CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfoo0, 1)))) \ 971 || (TARGET_SB && CONSTANT_ADDRESS_P (xfoo0)))) 972 973 /* Go to ADDR if X is a valid address not using indexing. 974 (This much is the easy part.) */ 975 #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ 976 { \ 977 if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \ 978 if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \ 979 if (GET_CODE (X) == PLUS) \ 980 if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (X, 1))) \ 981 if (INDIRECTABLE_2_ADDRESS_P (XEXP (X, 0))) \ 982 goto ADDR; \ 983 } 984 985 /* Go to ADDR if X is a valid address not using indexing. 986 (This much is the easy part.) */ 987 #define GO_IF_INDEXING(X, MODE, ADDR) \ 988 { register rtx xfoob = (X); \ 989 if (GET_CODE (xfoob) == PLUS && INDEX_TERM_P (XEXP (xfoob, 0), MODE)) \ 990 GO_IF_INDEXABLE_ADDRESS (XEXP (xfoob, 1), ADDR); \ 991 if (GET_CODE (xfoob) == PLUS && INDEX_TERM_P (XEXP (xfoob, 1), MODE)) \ 992 GO_IF_INDEXABLE_ADDRESS (XEXP (xfoob, 0), ADDR); } \ 993 994 #define GO_IF_INDEXABLE_ADDRESS(X, ADDR) \ 995 { if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; \ 996 if (INDIRECTABLE_2_ADDRESS_P (X)) goto ADDR; \ 997 if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; \ 998 } 999 1000 /* 1 if PROD is either a reg times size of mode MODE 1001 or just a reg, if MODE is just one byte. Actually, on the ns32k, 1002 since the index mode is independent of the operand size, 1003 we can match more stuff... 1004 1005 This macro's expansion uses the temporary variables xfoo0, xfoo1 1006 and xfoo2 that must be declared in the surrounding context. */ 1007 #define INDEX_TERM_P(PROD, MODE) \ 1008 ((GET_CODE (PROD) == REG && REG_OK_FOR_INDEX_P (PROD)) \ 1009 || (GET_CODE (PROD) == MULT \ 1010 && (xfoo0 = XEXP (PROD, 0), xfoo1 = XEXP (PROD, 1), \ 1011 (GET_CODE (xfoo1) == CONST_INT \ 1012 && GET_CODE (xfoo0) == REG \ 1013 && FITS_INDEX_RANGE (INTVAL (xfoo1)) \ 1014 && REG_OK_FOR_INDEX_P (xfoo0))))) 1015 1016 #define FITS_INDEX_RANGE(X) \ 1017 ((xfoo2 = (unsigned)(X)-1), \ 1018 ((xfoo2 < 4 && xfoo2 != 2) || xfoo2 == 7)) 1019 1020 /* Note that xfoo0, xfoo1, xfoo2 are used in some of the submacros above. */ 1021 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1022 { register rtx xfooy, xfoo0, xfoo1; \ 1023 unsigned xfoo2; \ 1024 xfooy = X; \ 1025 if (flag_pic && cfun && ! current_function_uses_pic_offset_table \ 1026 && global_symbolic_reference_mentioned_p (X, 1)) \ 1027 current_function_uses_pic_offset_table = 1; \ 1028 GO_IF_NONINDEXED_ADDRESS (xfooy, ADDR); \ 1029 if (GET_CODE (xfooy) == PLUS) \ 1030 { \ 1031 if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfooy, 1)) \ 1032 && GET_CODE (XEXP (xfooy, 0)) == PLUS) \ 1033 xfooy = XEXP (xfooy, 0); \ 1034 else if (CONSTANT_ADDRESS_NO_LABEL_P (XEXP (xfooy, 0)) \ 1035 && GET_CODE (XEXP (xfooy, 1)) == PLUS) \ 1036 xfooy = XEXP (xfooy, 1); \ 1037 GO_IF_INDEXING (xfooy, MODE, ADDR); \ 1038 } \ 1039 else if (INDEX_TERM_P (xfooy, MODE)) \ 1040 goto ADDR; \ 1041 else if (GET_CODE (xfooy) == PRE_DEC) \ 1042 { \ 1043 if (REGNO (XEXP (xfooy, 0)) == STACK_POINTER_REGNUM) goto ADDR; \ 1044 } \ 1045 } 1046 1047 /* Try machine-dependent ways of modifying an illegitimate address 1048 to be legitimate. If we find one, return the new, valid address. 1049 This macro is used in only one place: `memory_address' in explow.c. 1050 1051 OLDX is the address as it was before break_out_memory_refs was called. 1052 In some cases it is useful to look at this to decide what needs to be done. 1053 1054 MODE and WIN are passed so that this macro can use 1055 GO_IF_LEGITIMATE_ADDRESS. 1056 1057 It is always safe for this macro to do nothing. It exists to recognize 1058 opportunities to optimize the output. 1059 1060 For the ns32k, we do nothing */ 1061 1062 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {} 1063 1064 /* Nonzero if the constant value X is a legitimate general operand 1065 when generating PIC code. It is given that flag_pic is on and 1066 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1067 1068 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1069 (((! current_function_uses_pic_offset_table \ 1070 && symbolic_reference_mentioned_p (X))? \ 1071 (current_function_uses_pic_offset_table = 1):0 \ 1072 ), (! SYMBOLIC_CONST (X) \ 1073 || GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF)) 1074 1075 #define SYMBOLIC_CONST(X) \ 1076 (GET_CODE (X) == SYMBOL_REF \ 1077 || GET_CODE (X) == LABEL_REF \ 1078 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1079 1080 /* Go to LABEL if ADDR (a legitimate address expression) 1081 has an effect that depends on the machine mode it is used for. 1082 On the ns32k, only predecrement and postincrement address depend thus 1083 (the amount of decrement or increment being the length of the operand). */ 1084 1085 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1086 { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \ 1087 goto LABEL;} 1088 1089 /* Specify the machine mode that this machine uses 1090 for the index in the tablejump instruction. 1091 HI mode is more efficient but the range is not wide enough for 1092 all programs. */ 1093 #define CASE_VECTOR_MODE SImode 1094 1095 /* Define as C expression which evaluates to nonzero if the tablejump 1096 instruction expects the table to contain offsets from the address of the 1097 table. 1098 Do not define this if the table should contain absolute addresses. */ 1099 #define CASE_VECTOR_PC_RELATIVE 1 1100 1101 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1102 #define DEFAULT_SIGNED_CHAR 1 1103 1104 /* Max number of bytes we can move from memory to memory 1105 in one reasonably fast instruction. */ 1106 #define MOVE_MAX 4 1107 1108 /* The number of scalar move insns which should be generated instead 1109 of a string move insn or a library call. 1110 1111 We have a smart movstrsi insn */ 1112 #define MOVE_RATIO 0 1113 1114 #define STORE_RATIO (optimize_size ? 3 : 15) 1115 #define STORE_BY_PIECES_P(SIZE, ALIGN) \ 1116 (move_by_pieces_ninsns (SIZE, ALIGN) < (unsigned int) STORE_RATIO) 1117 1118 1119 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1120 #define SLOW_BYTE_ACCESS 0 1121 1122 /* Define if shifts truncate the shift count 1123 which implies one can omit a sign-extension or zero-extension 1124 of a shift count. */ 1125 /* #define SHIFT_COUNT_TRUNCATED */ 1126 1127 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1128 is done just by pretending it is already truncated. */ 1129 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1130 1131 /* Specify the machine mode that pointers have. 1132 After generation of rtl, the compiler makes no further distinction 1133 between pointers and any other objects of this machine mode. */ 1134 #define Pmode SImode 1135 1136 /* A function address in a call instruction 1137 is a byte address (for indexing purposes) 1138 so give the MEM rtx a byte's mode. */ 1139 #define FUNCTION_MODE QImode 1140 1141 /* Tell final.c how to eliminate redundant test instructions. */ 1142 1143 /* Here we define machine-dependent flags and fields in cc_status 1144 (see `conditions.h'). */ 1145 1146 /* This bit means that what ought to be in the Z bit 1147 should be tested in the F bit. */ 1148 #define CC_Z_IN_F 04000 1149 1150 /* This bit means that what ought to be in the Z bit 1151 is complemented in the F bit. */ 1152 #define CC_Z_IN_NOT_F 010000 1153 1154 /* This bit means that the L bit indicates unordered (IEEE) comparison. 1155 */ 1156 #define CC_UNORD 020000 1157 1158 /* Store in cc_status the expressions 1159 that the condition codes will describe 1160 after execution of an instruction whose pattern is EXP. 1161 Do not alter them if the instruction would not alter the cc's. */ 1162 1163 #define NOTICE_UPDATE_CC(EXP, INSN) \ 1164 { if (GET_CODE (EXP) == SET) \ 1165 { if (GET_CODE (SET_DEST (EXP)) == CC0) \ 1166 { cc_status.flags = 0; \ 1167 cc_status.value1 = SET_DEST (EXP); \ 1168 cc_status.value2 = SET_SRC (EXP); \ 1169 } \ 1170 else if (GET_CODE (SET_SRC (EXP)) == CALL) \ 1171 { CC_STATUS_INIT; } \ 1172 else if (GET_CODE (SET_DEST (EXP)) == REG) \ 1173 { if (cc_status.value1 \ 1174 && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value1)) \ 1175 cc_status.value1 = 0; \ 1176 if (cc_status.value2 \ 1177 && reg_overlap_mentioned_p (SET_DEST (EXP), cc_status.value2)) \ 1178 cc_status.value2 = 0; \ 1179 } \ 1180 else if (GET_CODE (SET_DEST (EXP)) == MEM) \ 1181 { CC_STATUS_INIT; } \ 1182 } \ 1183 else if (GET_CODE (EXP) == PARALLEL \ 1184 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \ 1185 { if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == CC0) \ 1186 { cc_status.flags = 0; \ 1187 cc_status.value1 = SET_DEST (XVECEXP (EXP, 0, 0)); \ 1188 cc_status.value2 = SET_SRC (XVECEXP (EXP, 0, 0)); \ 1189 } \ 1190 else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == REG) \ 1191 { if (cc_status.value1 \ 1192 && reg_overlap_mentioned_p (SET_DEST (XVECEXP (EXP, 0, 0)), cc_status.value1)) \ 1193 cc_status.value1 = 0; \ 1194 if (cc_status.value2 \ 1195 && reg_overlap_mentioned_p (SET_DEST (XVECEXP (EXP, 0, 0)), cc_status.value2)) \ 1196 cc_status.value2 = 0; \ 1197 } \ 1198 else if (GET_CODE (SET_DEST (XVECEXP (EXP, 0, 0))) == MEM) \ 1199 { CC_STATUS_INIT; } \ 1200 } \ 1201 else if (GET_CODE (EXP) == CALL) \ 1202 { /* all bets are off */ CC_STATUS_INIT; } \ 1203 else { /* nothing happens? CC_STATUS_INIT; */} \ 1204 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \ 1205 && cc_status.value2 \ 1206 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \ 1207 abort (); \ 1208 } 1209 1210 /* Describe the costs of the following register moves which are discouraged: 1211 1.) Moves between the Floating point registers and the frame pointer and stack pointer 1212 2.) Moves between the stack pointer and the frame pointer 1213 3.) Moves between the floating point and general registers 1214 1215 These all involve two memory references. This is worse than a memory 1216 to memory move (default cost 4) 1217 */ 1218 1219 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1220 register_move_cost (CLASS1, CLASS2) 1221 1222 #define OUTPUT_JUMP(NORMAL, NO_OV) \ 1223 { if (cc_status.flags & CC_NO_OVERFLOW) \ 1224 return NO_OV; \ 1225 return NORMAL; } 1226 1227 /* Dividing the output into sections */ 1228 1229 /* Output before read-only data. */ 1230 1231 #define TEXT_SECTION_ASM_OP "\t.text" 1232 1233 /* Output before writable data. */ 1234 1235 #define DATA_SECTION_ASM_OP "\t.data" 1236 1237 /* Define the output Assembly Language */ 1238 1239 /* Output to assembler file text saying following lines 1240 may contain character constants, extra white space, comments, etc. */ 1241 1242 #define ASM_APP_ON "#APP\n" 1243 1244 /* Output to assembler file text saying following lines 1245 no longer contain unusual constructs. */ 1246 1247 #define ASM_APP_OFF "#NO_APP\n" 1248 1249 /* Output of Data */ 1250 1251 /* This is how to output an assembler line defining an external/static 1252 address which is not in tree format (for collect.c). */ 1253 1254 /* The prefix to add to user-visible assembler symbols. */ 1255 #define USER_LABEL_PREFIX "_" 1256 1257 /* This is how to output an insn to push a register on the stack. 1258 It need not be very fast code. */ 1259 1260 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1261 fprintf (FILE, "\tmovd %s,tos\n", reg_names[REGNO]) 1262 1263 /* This is how to output an insn to pop a register from the stack. 1264 It need not be very fast code. */ 1265 1266 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1267 fprintf (FILE, "\tmovd tos,%s\n", reg_names[REGNO]) 1268 1269 /* This is how to output a command to make the user-level label named NAME 1270 defined for reference from other files. */ 1271 1272 /* Globalizing directive for a label. */ 1273 #define GLOBAL_ASM_OP ".globl " 1274 1275 /* This is how to store into the string LABEL 1276 the symbol_ref name of an internal numbered label where 1277 PREFIX is the class of label and NUM is the number within the class. 1278 This is suitable for output with `assemble_name'. */ 1279 1280 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1281 sprintf (LABEL, "*%s%ld", PREFIX, (long) NUM) 1282 1283 /* This is how to align the code that follows an unconditional branch. */ 1284 1285 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) (2) 1286 1287 /* This is how to output an element of a case-vector that is absolute. 1288 (The ns32k does not use such vectors, 1289 but we must define this macro anyway.) */ 1290 1291 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1292 fprintf (FILE, "\t.long L%d\n", VALUE) 1293 1294 /* This is how to output an element of a case-vector that is relative. */ 1295 /* ** Notice that the second element is LI format! */ 1296 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1297 fprintf (FILE, "\t.long L%d-LI%d\n", VALUE, REL) 1298 1299 /* This is how to output an assembler line 1300 that says to advance the location counter 1301 to a multiple of 2**LOG bytes. */ 1302 1303 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1304 fprintf (FILE, "\t.align %d\n", (LOG)) 1305 1306 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1307 fprintf (FILE, "\t.space %u\n", (int)(SIZE)) 1308 1309 /* This says how to output an assembler line 1310 to define a global common symbol. */ 1311 1312 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1313 ( fputs (".comm ", (FILE)), \ 1314 assemble_name ((FILE), (NAME)), \ 1315 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 1316 1317 /* This says how to output an assembler line 1318 to define a local common symbol. */ 1319 1320 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1321 ( fputs (".lcomm ", (FILE)), \ 1322 assemble_name ((FILE), (NAME)), \ 1323 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 1324 1325 /* Print an instruction operand X on file FILE. 1326 CODE is the code from the %-spec that requested printing this operand; 1327 if `%z3' was used to print operand 3, then CODE is 'z'. */ 1328 1329 /* %$ means print the prefix for an immediate operand. */ 1330 1331 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1332 ((CODE) == '$' || (CODE) == '?') 1333 1334 #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) 1335 1336 /* Print a memory operand whose address is X, on file FILE. */ 1337 1338 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address(FILE, ADDR) 1339 1340 extern const unsigned int ns32k_reg_class_contents[N_REG_CLASSES][1]; 1341 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; /* smallest class containing REGNO */ 1342 1343 /* 1344 Local variables: 1345 version-control: t 1346 End: 1347 */ 1348