1 /* Subroutines for insn-output.c for SPARC.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com)
5 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
6 at Cygnus Support.
7
8 This file is part of GCC.
9
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
13 any later version.
14
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
24
25 #include "config.h"
26 #include "system.h"
27 #include "coretypes.h"
28 #include "tm.h"
29 #include "tree.h"
30 #include "rtl.h"
31 #include "regs.h"
32 #include "hard-reg-set.h"
33 #include "real.h"
34 #include "insn-config.h"
35 #include "conditions.h"
36 #include "output.h"
37 #include "insn-attr.h"
38 #include "flags.h"
39 #include "function.h"
40 #include "expr.h"
41 #include "optabs.h"
42 #include "recog.h"
43 #include "toplev.h"
44 #include "ggc.h"
45 #include "tm_p.h"
46 #include "debug.h"
47 #include "target.h"
48 #include "target-def.h"
49 #include "cfglayout.h"
50
51 /* 1 if the caller has placed an "unimp" insn immediately after the call.
52 This is used in v8 code when calling a function that returns a structure.
53 v9 doesn't have this. Be careful to have this test be the same as that
54 used on the call. */
55
56 #define SKIP_CALLERS_UNIMP_P \
57 (!TARGET_ARCH64 && current_function_returns_struct \
58 && ! integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl))) \
59 && (TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) \
60 == INTEGER_CST))
61
62 /* Global variables for machine-dependent things. */
63
64 /* Size of frame. Need to know this to emit return insns from leaf procedures.
65 ACTUAL_FSIZE is set by compute_frame_size() which is called during the
66 reload pass. This is important as the value is later used in insn
67 scheduling (to see what can go in a delay slot).
68 APPARENT_FSIZE is the size of the stack less the register save area and less
69 the outgoing argument area. It is used when saving call preserved regs. */
70 static HOST_WIDE_INT apparent_fsize;
71 static HOST_WIDE_INT actual_fsize;
72
73 /* Number of live general or floating point registers needed to be
74 saved (as 4-byte quantities). */
75 static int num_gfregs;
76
77 /* Save the operands last given to a compare for use when we
78 generate a scc or bcc insn. */
79 rtx sparc_compare_op0, sparc_compare_op1;
80
81 /* Coordinate with the md file wrt special insns created by
82 sparc_nonflat_function_epilogue. */
83 bool sparc_emitting_epilogue;
84
85 /* Vector to say how input registers are mapped to output registers.
86 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to
87 eliminate it. You must use -fomit-frame-pointer to get that. */
88 char leaf_reg_remap[] =
89 { 0, 1, 2, 3, 4, 5, 6, 7,
90 -1, -1, -1, -1, -1, -1, 14, -1,
91 -1, -1, -1, -1, -1, -1, -1, -1,
92 8, 9, 10, 11, 12, 13, -1, 15,
93
94 32, 33, 34, 35, 36, 37, 38, 39,
95 40, 41, 42, 43, 44, 45, 46, 47,
96 48, 49, 50, 51, 52, 53, 54, 55,
97 56, 57, 58, 59, 60, 61, 62, 63,
98 64, 65, 66, 67, 68, 69, 70, 71,
99 72, 73, 74, 75, 76, 77, 78, 79,
100 80, 81, 82, 83, 84, 85, 86, 87,
101 88, 89, 90, 91, 92, 93, 94, 95,
102 96, 97, 98, 99, 100};
103
104 /* Vector, indexed by hard register number, which contains 1
105 for a register that is allowable in a candidate for leaf
106 function treatment. */
107 char sparc_leaf_regs[] =
108 { 1, 1, 1, 1, 1, 1, 1, 1,
109 0, 0, 0, 0, 0, 0, 1, 0,
110 0, 0, 0, 0, 0, 0, 0, 0,
111 1, 1, 1, 1, 1, 1, 0, 1,
112 1, 1, 1, 1, 1, 1, 1, 1,
113 1, 1, 1, 1, 1, 1, 1, 1,
114 1, 1, 1, 1, 1, 1, 1, 1,
115 1, 1, 1, 1, 1, 1, 1, 1,
116 1, 1, 1, 1, 1, 1, 1, 1,
117 1, 1, 1, 1, 1, 1, 1, 1,
118 1, 1, 1, 1, 1, 1, 1, 1,
119 1, 1, 1, 1, 1, 1, 1, 1,
120 1, 1, 1, 1, 1};
121
122 struct machine_function GTY(())
123 {
124 /* Some local-dynamic TLS symbol name. */
125 const char *some_ld_name;
126 };
127
128 /* Name of where we pretend to think the frame pointer points.
129 Normally, this is "%fp", but if we are in a leaf procedure,
130 this is "%sp+something". We record "something" separately as it may be
131 too big for reg+constant addressing. */
132
133 static const char *frame_base_name;
134 static HOST_WIDE_INT frame_base_offset;
135
136 static void sparc_init_modes (void);
137 static int save_regs (FILE *, int, int, const char *, int, int, HOST_WIDE_INT);
138 static int restore_regs (FILE *, int, int, const char *, int, int);
139 static void build_big_number (FILE *, HOST_WIDE_INT, const char *);
140 static void scan_record_type (tree, int *, int *, int *);
141 static int function_arg_slotno (const CUMULATIVE_ARGS *, enum machine_mode,
142 tree, int, int, int *, int *);
143
144 static int supersparc_adjust_cost (rtx, rtx, rtx, int);
145 static int hypersparc_adjust_cost (rtx, rtx, rtx, int);
146
147 static void sparc_output_addr_vec (rtx);
148 static void sparc_output_addr_diff_vec (rtx);
149 static void sparc_output_deferred_case_vectors (void);
150 static int check_return_regs (rtx);
151 static int epilogue_renumber (rtx *, int);
152 static bool sparc_assemble_integer (rtx, unsigned int, int);
153 static int set_extends (rtx);
154 static void output_restore_regs (FILE *, int);
155 static void sparc_output_function_prologue (FILE *, HOST_WIDE_INT);
156 static void sparc_output_function_epilogue (FILE *, HOST_WIDE_INT);
157 static void sparc_flat_function_epilogue (FILE *, HOST_WIDE_INT);
158 static void sparc_flat_function_prologue (FILE *, HOST_WIDE_INT);
159 static void sparc_flat_save_restore (FILE *, const char *, int,
160 unsigned long, unsigned long,
161 const char *, const char *,
162 HOST_WIDE_INT);
163 static void sparc_nonflat_function_epilogue (FILE *, HOST_WIDE_INT, int);
164 static void sparc_nonflat_function_prologue (FILE *, HOST_WIDE_INT, int);
165 #ifdef OBJECT_FORMAT_ELF
166 static void sparc_elf_asm_named_section (const char *, unsigned int);
167 #endif
168 static void sparc_aout_select_section (tree, int, unsigned HOST_WIDE_INT)
169 ATTRIBUTE_UNUSED;
170 static void sparc_aout_select_rtx_section (enum machine_mode, rtx,
171 unsigned HOST_WIDE_INT)
172 ATTRIBUTE_UNUSED;
173
174 static int sparc_adjust_cost (rtx, rtx, rtx, int);
175 static int sparc_issue_rate (void);
176 static void sparc_sched_init (FILE *, int, int);
177 static int sparc_use_dfa_pipeline_interface (void);
178 static int sparc_use_sched_lookahead (void);
179
180 static void emit_soft_tfmode_libcall (const char *, int, rtx *);
181 static void emit_soft_tfmode_binop (enum rtx_code, rtx *);
182 static void emit_soft_tfmode_unop (enum rtx_code, rtx *);
183 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *);
184 static void emit_hard_tfmode_operation (enum rtx_code, rtx *);
185
186 static bool sparc_function_ok_for_sibcall (tree, tree);
187 static void sparc_init_libfuncs (void);
188 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
189 HOST_WIDE_INT, tree);
190 static struct machine_function * sparc_init_machine_status (void);
191 static bool sparc_cannot_force_const_mem (rtx);
192 static rtx sparc_tls_get_addr (void);
193 static rtx sparc_tls_got (void);
194 static const char *get_some_local_dynamic_name (void);
195 static int get_some_local_dynamic_name_1 (rtx *, void *);
196 static bool sparc_rtx_costs (rtx, int, int, int *);
197
198 /* Option handling. */
199
200 /* Code model option as passed by user. */
201 const char *sparc_cmodel_string;
202 /* Parsed value. */
203 enum cmodel sparc_cmodel;
204
205 char sparc_hard_reg_printed[8];
206
207 struct sparc_cpu_select sparc_select[] =
208 {
209 /* switch name, tune arch */
210 { (char *)0, "default", 1, 1 },
211 { (char *)0, "-mcpu=", 1, 1 },
212 { (char *)0, "-mtune=", 1, 0 },
213 { 0, 0, 0, 0 }
214 };
215
216 /* CPU type. This is set from TARGET_CPU_DEFAULT and -m{cpu,tune}=xxx. */
217 enum processor_type sparc_cpu;
218
219 /* Initialize the GCC target structure. */
220
221 /* The sparc default is to use .half rather than .short for aligned
222 HI objects. Use .word instead of .long on non-ELF systems. */
223 #undef TARGET_ASM_ALIGNED_HI_OP
224 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
225 #ifndef OBJECT_FORMAT_ELF
226 #undef TARGET_ASM_ALIGNED_SI_OP
227 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
228 #endif
229
230 #undef TARGET_ASM_UNALIGNED_HI_OP
231 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t"
232 #undef TARGET_ASM_UNALIGNED_SI_OP
233 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t"
234 #undef TARGET_ASM_UNALIGNED_DI_OP
235 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t"
236
237 /* The target hook has to handle DI-mode values. */
238 #undef TARGET_ASM_INTEGER
239 #define TARGET_ASM_INTEGER sparc_assemble_integer
240
241 #undef TARGET_ASM_FUNCTION_PROLOGUE
242 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_output_function_prologue
243 #undef TARGET_ASM_FUNCTION_EPILOGUE
244 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_output_function_epilogue
245
246 #undef TARGET_SCHED_ADJUST_COST
247 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost
248 #undef TARGET_SCHED_ISSUE_RATE
249 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate
250 #undef TARGET_SCHED_INIT
251 #define TARGET_SCHED_INIT sparc_sched_init
252 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
253 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE sparc_use_dfa_pipeline_interface
254 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
255 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead
256
257 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
258 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall
259
260 #undef TARGET_INIT_LIBFUNCS
261 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs
262
263 #ifdef HAVE_AS_TLS
264 #undef TARGET_HAVE_TLS
265 #define TARGET_HAVE_TLS true
266 #endif
267 #undef TARGET_CANNOT_FORCE_CONST_MEM
268 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem
269
270 #undef TARGET_ASM_OUTPUT_MI_THUNK
271 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk
272 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
273 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
274
275 #undef TARGET_RTX_COSTS
276 #define TARGET_RTX_COSTS sparc_rtx_costs
277 #undef TARGET_ADDRESS_COST
278 #define TARGET_ADDRESS_COST hook_int_rtx_0
279
280 struct gcc_target targetm = TARGET_INITIALIZER;
281
282 /* Validate and override various options, and do some machine dependent
283 initialization. */
284
285 void
sparc_override_options(void)286 sparc_override_options (void)
287 {
288 static struct code_model {
289 const char *const name;
290 const int value;
291 } const cmodels[] = {
292 { "32", CM_32 },
293 { "medlow", CM_MEDLOW },
294 { "medmid", CM_MEDMID },
295 { "medany", CM_MEDANY },
296 { "embmedany", CM_EMBMEDANY },
297 { 0, 0 }
298 };
299 const struct code_model *cmodel;
300 /* Map TARGET_CPU_DEFAULT to value for -m{arch,tune}=. */
301 static struct cpu_default {
302 const int cpu;
303 const char *const name;
304 } const cpu_default[] = {
305 /* There must be one entry here for each TARGET_CPU value. */
306 { TARGET_CPU_sparc, "cypress" },
307 { TARGET_CPU_sparclet, "tsc701" },
308 { TARGET_CPU_sparclite, "f930" },
309 { TARGET_CPU_v8, "v8" },
310 { TARGET_CPU_hypersparc, "hypersparc" },
311 { TARGET_CPU_sparclite86x, "sparclite86x" },
312 { TARGET_CPU_supersparc, "supersparc" },
313 { TARGET_CPU_v9, "v9" },
314 { TARGET_CPU_ultrasparc, "ultrasparc" },
315 { TARGET_CPU_ultrasparc3, "ultrasparc3" },
316 { 0, 0 }
317 };
318 const struct cpu_default *def;
319 /* Table of values for -m{cpu,tune}=. */
320 static struct cpu_table {
321 const char *const name;
322 const enum processor_type processor;
323 const int disable;
324 const int enable;
325 } const cpu_table[] = {
326 { "v7", PROCESSOR_V7, MASK_ISA, 0 },
327 { "cypress", PROCESSOR_CYPRESS, MASK_ISA, 0 },
328 { "v8", PROCESSOR_V8, MASK_ISA, MASK_V8 },
329 /* TI TMS390Z55 supersparc */
330 { "supersparc", PROCESSOR_SUPERSPARC, MASK_ISA, MASK_V8 },
331 { "sparclite", PROCESSOR_SPARCLITE, MASK_ISA, MASK_SPARCLITE },
332 /* The Fujitsu MB86930 is the original sparclite chip, with no fpu.
333 The Fujitsu MB86934 is the recent sparclite chip, with an fpu. */
334 { "f930", PROCESSOR_F930, MASK_ISA|MASK_FPU, MASK_SPARCLITE },
335 { "f934", PROCESSOR_F934, MASK_ISA, MASK_SPARCLITE|MASK_FPU },
336 { "hypersparc", PROCESSOR_HYPERSPARC, MASK_ISA, MASK_V8|MASK_FPU },
337 { "sparclite86x", PROCESSOR_SPARCLITE86X, MASK_ISA|MASK_FPU,
338 MASK_SPARCLITE },
339 { "sparclet", PROCESSOR_SPARCLET, MASK_ISA, MASK_SPARCLET },
340 /* TEMIC sparclet */
341 { "tsc701", PROCESSOR_TSC701, MASK_ISA, MASK_SPARCLET },
342 { "v9", PROCESSOR_V9, MASK_ISA, MASK_V9 },
343 /* TI ultrasparc I, II, IIi */
344 { "ultrasparc", PROCESSOR_ULTRASPARC, MASK_ISA, MASK_V9
345 /* Although insns using %y are deprecated, it is a clear win on current
346 ultrasparcs. */
347 |MASK_DEPRECATED_V8_INSNS},
348 /* TI ultrasparc III */
349 /* ??? Check if %y issue still holds true in ultra3. */
350 { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
351 { 0, 0, 0, 0 }
352 };
353 const struct cpu_table *cpu;
354 const struct sparc_cpu_select *sel;
355 int fpu;
356
357 #ifndef SPARC_BI_ARCH
358 /* Check for unsupported architecture size. */
359 if (! TARGET_64BIT != DEFAULT_ARCH32_P)
360 error ("%s is not supported by this configuration",
361 DEFAULT_ARCH32_P ? "-m64" : "-m32");
362 #endif
363
364 /* We force all 64bit archs to use 128 bit long double */
365 if (TARGET_64BIT && ! TARGET_LONG_DOUBLE_128)
366 {
367 error ("-mlong-double-64 not allowed with -m64");
368 target_flags |= MASK_LONG_DOUBLE_128;
369 }
370
371 /* Code model selection. */
372 sparc_cmodel = SPARC_DEFAULT_CMODEL;
373
374 #ifdef SPARC_BI_ARCH
375 if (TARGET_ARCH32)
376 sparc_cmodel = CM_32;
377 #endif
378
379 if (sparc_cmodel_string != NULL)
380 {
381 if (TARGET_ARCH64)
382 {
383 for (cmodel = &cmodels[0]; cmodel->name; cmodel++)
384 if (strcmp (sparc_cmodel_string, cmodel->name) == 0)
385 break;
386 if (cmodel->name == NULL)
387 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string);
388 else
389 sparc_cmodel = cmodel->value;
390 }
391 else
392 error ("-mcmodel= is not supported on 32 bit systems");
393 }
394
395 fpu = TARGET_FPU; /* save current -mfpu status */
396
397 /* Set the default CPU. */
398 for (def = &cpu_default[0]; def->name; ++def)
399 if (def->cpu == TARGET_CPU_DEFAULT)
400 break;
401 if (! def->name)
402 abort ();
403 sparc_select[0].string = def->name;
404
405 for (sel = &sparc_select[0]; sel->name; ++sel)
406 {
407 if (sel->string)
408 {
409 for (cpu = &cpu_table[0]; cpu->name; ++cpu)
410 if (! strcmp (sel->string, cpu->name))
411 {
412 if (sel->set_tune_p)
413 sparc_cpu = cpu->processor;
414
415 if (sel->set_arch_p)
416 {
417 target_flags &= ~cpu->disable;
418 target_flags |= cpu->enable;
419 }
420 break;
421 }
422
423 if (! cpu->name)
424 error ("bad value (%s) for %s switch", sel->string, sel->name);
425 }
426 }
427
428 /* If -mfpu or -mno-fpu was explicitly used, don't override with
429 the processor default. Clear MASK_FPU_SET to avoid confusing
430 the reverse mapping from switch values to names. */
431 if (TARGET_FPU_SET)
432 {
433 target_flags = (target_flags & ~MASK_FPU) | fpu;
434 target_flags &= ~MASK_FPU_SET;
435 }
436
437 /* Don't allow -mvis if FPU is disabled. */
438 if (! TARGET_FPU)
439 target_flags &= ~MASK_VIS;
440
441 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions
442 are available.
443 -m64 also implies v9. */
444 if (TARGET_VIS || TARGET_ARCH64)
445 {
446 target_flags |= MASK_V9;
447 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE);
448 }
449
450 /* Use the deprecated v8 insns for sparc64 in 32 bit mode. */
451 if (TARGET_V9 && TARGET_ARCH32)
452 target_flags |= MASK_DEPRECATED_V8_INSNS;
453
454 /* V8PLUS requires V9, makes no sense in 64 bit mode. */
455 if (! TARGET_V9 || TARGET_ARCH64)
456 target_flags &= ~MASK_V8PLUS;
457
458 /* Don't use stack biasing in 32 bit mode. */
459 if (TARGET_ARCH32)
460 target_flags &= ~MASK_STACK_BIAS;
461
462 /* Supply a default value for align_functions. */
463 if (align_functions == 0
464 && (sparc_cpu == PROCESSOR_ULTRASPARC
465 || sparc_cpu == PROCESSOR_ULTRASPARC3))
466 align_functions = 32;
467
468 /* Validate PCC_STRUCT_RETURN. */
469 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN)
470 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1);
471
472 /* Only use .uaxword when compiling for a 64-bit target. */
473 if (!TARGET_ARCH64)
474 targetm.asm_out.unaligned_op.di = NULL;
475
476 /* Do various machine dependent initializations. */
477 sparc_init_modes ();
478
479 /* Set up function hooks. */
480 init_machine_status = sparc_init_machine_status;
481 }
482
483 /* Miscellaneous utilities. */
484
485 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move
486 or branch on register contents instructions. */
487
488 int
v9_regcmp_p(enum rtx_code code)489 v9_regcmp_p (enum rtx_code code)
490 {
491 return (code == EQ || code == NE || code == GE || code == LT
492 || code == LE || code == GT);
493 }
494
495
496 /* Operand constraints. */
497
498 /* Return nonzero only if OP is a register of mode MODE,
499 or const0_rtx. */
500
501 int
reg_or_0_operand(rtx op,enum machine_mode mode)502 reg_or_0_operand (rtx op, enum machine_mode mode)
503 {
504 if (register_operand (op, mode))
505 return 1;
506 if (op == const0_rtx)
507 return 1;
508 if (GET_MODE (op) == VOIDmode && GET_CODE (op) == CONST_DOUBLE
509 && CONST_DOUBLE_HIGH (op) == 0
510 && CONST_DOUBLE_LOW (op) == 0)
511 return 1;
512 if (fp_zero_operand (op, mode))
513 return 1;
514 return 0;
515 }
516
517 /* Return nonzero only if OP is const1_rtx. */
518
519 int
const1_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)520 const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
521 {
522 return op == const1_rtx;
523 }
524
525 /* Nonzero if OP is a floating point value with value 0.0. */
526
527 int
fp_zero_operand(rtx op,enum machine_mode mode)528 fp_zero_operand (rtx op, enum machine_mode mode)
529 {
530 if (GET_MODE_CLASS (GET_MODE (op)) != MODE_FLOAT)
531 return 0;
532 return op == CONST0_RTX (mode);
533 }
534
535 /* Nonzero if OP is a register operand in floating point register. */
536
537 int
fp_register_operand(rtx op,enum machine_mode mode)538 fp_register_operand (rtx op, enum machine_mode mode)
539 {
540 if (! register_operand (op, mode))
541 return 0;
542 if (GET_CODE (op) == SUBREG)
543 op = SUBREG_REG (op);
544 return GET_CODE (op) == REG && SPARC_FP_REG_P (REGNO (op));
545 }
546
547 /* Nonzero if OP is a floating point constant which can
548 be loaded into an integer register using a single
549 sethi instruction. */
550
551 int
fp_sethi_p(rtx op)552 fp_sethi_p (rtx op)
553 {
554 if (GET_CODE (op) == CONST_DOUBLE)
555 {
556 REAL_VALUE_TYPE r;
557 long i;
558
559 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
560 if (REAL_VALUES_EQUAL (r, dconst0) &&
561 ! REAL_VALUE_MINUS_ZERO (r))
562 return 0;
563 REAL_VALUE_TO_TARGET_SINGLE (r, i);
564 if (SPARC_SETHI_P (i))
565 return 1;
566 }
567
568 return 0;
569 }
570
571 /* Nonzero if OP is a floating point constant which can
572 be loaded into an integer register using a single
573 mov instruction. */
574
575 int
fp_mov_p(rtx op)576 fp_mov_p (rtx op)
577 {
578 if (GET_CODE (op) == CONST_DOUBLE)
579 {
580 REAL_VALUE_TYPE r;
581 long i;
582
583 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
584 if (REAL_VALUES_EQUAL (r, dconst0) &&
585 ! REAL_VALUE_MINUS_ZERO (r))
586 return 0;
587 REAL_VALUE_TO_TARGET_SINGLE (r, i);
588 if (SPARC_SIMM13_P (i))
589 return 1;
590 }
591
592 return 0;
593 }
594
595 /* Nonzero if OP is a floating point constant which can
596 be loaded into an integer register using a high/losum
597 instruction sequence. */
598
599 int
fp_high_losum_p(rtx op)600 fp_high_losum_p (rtx op)
601 {
602 /* The constraints calling this should only be in
603 SFmode move insns, so any constant which cannot
604 be moved using a single insn will do. */
605 if (GET_CODE (op) == CONST_DOUBLE)
606 {
607 REAL_VALUE_TYPE r;
608 long i;
609
610 REAL_VALUE_FROM_CONST_DOUBLE (r, op);
611 if (REAL_VALUES_EQUAL (r, dconst0) &&
612 ! REAL_VALUE_MINUS_ZERO (r))
613 return 0;
614 REAL_VALUE_TO_TARGET_SINGLE (r, i);
615 if (! SPARC_SETHI_P (i)
616 && ! SPARC_SIMM13_P (i))
617 return 1;
618 }
619
620 return 0;
621 }
622
623 /* Nonzero if OP is an integer register. */
624
625 int
intreg_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)626 intreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
627 {
628 return (register_operand (op, SImode)
629 || (TARGET_ARCH64 && register_operand (op, DImode)));
630 }
631
632 /* Nonzero if OP is a floating point condition code register. */
633
634 int
fcc_reg_operand(rtx op,enum machine_mode mode)635 fcc_reg_operand (rtx op, enum machine_mode mode)
636 {
637 /* This can happen when recog is called from combine. Op may be a MEM.
638 Fail instead of calling abort in this case. */
639 if (GET_CODE (op) != REG)
640 return 0;
641
642 if (mode != VOIDmode && mode != GET_MODE (op))
643 return 0;
644 if (mode == VOIDmode
645 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
646 return 0;
647
648 #if 0 /* ??? ==> 1 when %fcc0-3 are pseudos first. See gen_compare_reg(). */
649 if (reg_renumber == 0)
650 return REGNO (op) >= FIRST_PSEUDO_REGISTER;
651 return REGNO_OK_FOR_CCFP_P (REGNO (op));
652 #else
653 return (unsigned) REGNO (op) - SPARC_FIRST_V9_FCC_REG < 4;
654 #endif
655 }
656
657 /* Nonzero if OP is a floating point condition code fcc0 register. */
658
659 int
fcc0_reg_operand(rtx op,enum machine_mode mode)660 fcc0_reg_operand (rtx op, enum machine_mode mode)
661 {
662 /* This can happen when recog is called from combine. Op may be a MEM.
663 Fail instead of calling abort in this case. */
664 if (GET_CODE (op) != REG)
665 return 0;
666
667 if (mode != VOIDmode && mode != GET_MODE (op))
668 return 0;
669 if (mode == VOIDmode
670 && (GET_MODE (op) != CCFPmode && GET_MODE (op) != CCFPEmode))
671 return 0;
672
673 return REGNO (op) == SPARC_FCC_REG;
674 }
675
676 /* Nonzero if OP is an integer or floating point condition code register. */
677
678 int
icc_or_fcc_reg_operand(rtx op,enum machine_mode mode)679 icc_or_fcc_reg_operand (rtx op, enum machine_mode mode)
680 {
681 if (GET_CODE (op) == REG && REGNO (op) == SPARC_ICC_REG)
682 {
683 if (mode != VOIDmode && mode != GET_MODE (op))
684 return 0;
685 if (mode == VOIDmode
686 && GET_MODE (op) != CCmode && GET_MODE (op) != CCXmode)
687 return 0;
688 return 1;
689 }
690
691 return fcc_reg_operand (op, mode);
692 }
693
694 /* Nonzero if OP can appear as the dest of a RESTORE insn. */
695 int
restore_operand(rtx op,enum machine_mode mode)696 restore_operand (rtx op, enum machine_mode mode)
697 {
698 return (GET_CODE (op) == REG && GET_MODE (op) == mode
699 && (REGNO (op) < 8 || (REGNO (op) >= 24 && REGNO (op) < 32)));
700 }
701
702 /* Call insn on SPARC can take a PC-relative constant address, or any regular
703 memory address. */
704
705 int
call_operand(rtx op,enum machine_mode mode)706 call_operand (rtx op, enum machine_mode mode)
707 {
708 if (GET_CODE (op) != MEM)
709 abort ();
710 op = XEXP (op, 0);
711 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
712 }
713
714 int
call_operand_address(rtx op,enum machine_mode mode)715 call_operand_address (rtx op, enum machine_mode mode)
716 {
717 return (symbolic_operand (op, mode) || memory_address_p (Pmode, op));
718 }
719
720 /* If OP is a SYMBOL_REF of a thread-local symbol, return its TLS mode,
721 otherwise return 0. */
722
723 int
tls_symbolic_operand(rtx op)724 tls_symbolic_operand (rtx op)
725 {
726 if (GET_CODE (op) != SYMBOL_REF)
727 return 0;
728 return SYMBOL_REF_TLS_MODEL (op);
729 }
730
731 int
tgd_symbolic_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)732 tgd_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
733 {
734 return tls_symbolic_operand (op) == TLS_MODEL_GLOBAL_DYNAMIC;
735 }
736
737 int
tld_symbolic_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)738 tld_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
739 {
740 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_DYNAMIC;
741 }
742
743 int
tie_symbolic_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)744 tie_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
745 {
746 return tls_symbolic_operand (op) == TLS_MODEL_INITIAL_EXEC;
747 }
748
749 int
tle_symbolic_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)750 tle_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
751 {
752 return tls_symbolic_operand (op) == TLS_MODEL_LOCAL_EXEC;
753 }
754
755 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
756 reference and a constant. */
757
758 int
symbolic_operand(register rtx op,enum machine_mode mode)759 symbolic_operand (register rtx op, enum machine_mode mode)
760 {
761 enum machine_mode omode = GET_MODE (op);
762
763 if (omode != mode && omode != VOIDmode && mode != VOIDmode)
764 return 0;
765
766 switch (GET_CODE (op))
767 {
768 case SYMBOL_REF:
769 return !SYMBOL_REF_TLS_MODEL (op);
770
771 case LABEL_REF:
772 return 1;
773
774 case CONST:
775 op = XEXP (op, 0);
776 return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
777 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
778 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
779 && GET_CODE (XEXP (op, 1)) == CONST_INT);
780
781 default:
782 return 0;
783 }
784 }
785
786 /* Return truth value of statement that OP is a symbolic memory
787 operand of mode MODE. */
788
789 int
symbolic_memory_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)790 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
791 {
792 if (GET_CODE (op) == SUBREG)
793 op = SUBREG_REG (op);
794 if (GET_CODE (op) != MEM)
795 return 0;
796 op = XEXP (op, 0);
797 return ((GET_CODE (op) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (op))
798 || GET_CODE (op) == CONST || GET_CODE (op) == HIGH
799 || GET_CODE (op) == LABEL_REF);
800 }
801
802 /* Return truth value of statement that OP is a LABEL_REF of mode MODE. */
803
804 int
label_ref_operand(rtx op,enum machine_mode mode)805 label_ref_operand (rtx op, enum machine_mode mode)
806 {
807 if (GET_CODE (op) != LABEL_REF)
808 return 0;
809 if (GET_MODE (op) != mode)
810 return 0;
811 return 1;
812 }
813
814 /* Return 1 if the operand is an argument used in generating pic references
815 in either the medium/low or medium/anywhere code models of sparc64. */
816
817 int
sp64_medium_pic_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)818 sp64_medium_pic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
819 {
820 /* Check for (const (minus (symbol_ref:GOT)
821 (const (minus (label) (pc))))). */
822 if (GET_CODE (op) != CONST)
823 return 0;
824 op = XEXP (op, 0);
825 if (GET_CODE (op) != MINUS)
826 return 0;
827 if (GET_CODE (XEXP (op, 0)) != SYMBOL_REF)
828 return 0;
829 /* ??? Ensure symbol is GOT. */
830 if (GET_CODE (XEXP (op, 1)) != CONST)
831 return 0;
832 if (GET_CODE (XEXP (XEXP (op, 1), 0)) != MINUS)
833 return 0;
834 return 1;
835 }
836
837 /* Return 1 if the operand is a data segment reference. This includes
838 the readonly data segment, or in other words anything but the text segment.
839 This is needed in the medium/anywhere code model on v9. These values
840 are accessed with EMBMEDANY_BASE_REG. */
841
842 int
data_segment_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)843 data_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
844 {
845 switch (GET_CODE (op))
846 {
847 case SYMBOL_REF :
848 return ! SYMBOL_REF_FUNCTION_P (op);
849 case PLUS :
850 /* Assume canonical format of symbol + constant.
851 Fall through. */
852 case CONST :
853 return data_segment_operand (XEXP (op, 0), VOIDmode);
854 default :
855 return 0;
856 }
857 }
858
859 /* Return 1 if the operand is a text segment reference.
860 This is needed in the medium/anywhere code model on v9. */
861
862 int
text_segment_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)863 text_segment_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
864 {
865 switch (GET_CODE (op))
866 {
867 case LABEL_REF :
868 return 1;
869 case SYMBOL_REF :
870 return SYMBOL_REF_FUNCTION_P (op);
871 case PLUS :
872 /* Assume canonical format of symbol + constant.
873 Fall through. */
874 case CONST :
875 return text_segment_operand (XEXP (op, 0), VOIDmode);
876 default :
877 return 0;
878 }
879 }
880
881 /* Return 1 if the operand is either a register or a memory operand that is
882 not symbolic. */
883
884 int
reg_or_nonsymb_mem_operand(register rtx op,enum machine_mode mode)885 reg_or_nonsymb_mem_operand (register rtx op, enum machine_mode mode)
886 {
887 if (register_operand (op, mode))
888 return 1;
889
890 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
891 return 1;
892
893 return 0;
894 }
895
896 int
splittable_symbolic_memory_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)897 splittable_symbolic_memory_operand (rtx op,
898 enum machine_mode mode ATTRIBUTE_UNUSED)
899 {
900 if (GET_CODE (op) != MEM)
901 return 0;
902 if (! symbolic_operand (XEXP (op, 0), Pmode))
903 return 0;
904 return 1;
905 }
906
907 int
splittable_immediate_memory_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)908 splittable_immediate_memory_operand (rtx op,
909 enum machine_mode mode ATTRIBUTE_UNUSED)
910 {
911 if (GET_CODE (op) != MEM)
912 return 0;
913 if (! immediate_operand (XEXP (op, 0), Pmode))
914 return 0;
915 return 1;
916 }
917
918 /* Return truth value of whether OP is EQ or NE. */
919
920 int
eq_or_neq(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)921 eq_or_neq (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
922 {
923 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
924 }
925
926 /* Return 1 if this is a comparison operator, but not an EQ, NE, GEU,
927 or LTU for non-floating-point. We handle those specially. */
928
929 int
normal_comp_operator(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)930 normal_comp_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
931 {
932 enum rtx_code code = GET_CODE (op);
933
934 if (GET_RTX_CLASS (code) != '<')
935 return 0;
936
937 if (GET_MODE (XEXP (op, 0)) == CCFPmode
938 || GET_MODE (XEXP (op, 0)) == CCFPEmode)
939 return 1;
940
941 return (code != NE && code != EQ && code != GEU && code != LTU);
942 }
943
944 /* Return 1 if this is a comparison operator. This allows the use of
945 MATCH_OPERATOR to recognize all the branch insns. */
946
947 int
noov_compare_op(register rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)948 noov_compare_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
949 {
950 enum rtx_code code = GET_CODE (op);
951
952 if (GET_RTX_CLASS (code) != '<')
953 return 0;
954
955 if (GET_MODE (XEXP (op, 0)) == CC_NOOVmode
956 || GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
957 /* These are the only branches which work with CC_NOOVmode. */
958 return (code == EQ || code == NE || code == GE || code == LT);
959 return 1;
960 }
961
962 /* Return 1 if this is a 64-bit comparison operator. This allows the use of
963 MATCH_OPERATOR to recognize all the branch insns. */
964
965 int
noov_compare64_op(register rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)966 noov_compare64_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
967 {
968 enum rtx_code code = GET_CODE (op);
969
970 if (! TARGET_V9)
971 return 0;
972
973 if (GET_RTX_CLASS (code) != '<')
974 return 0;
975
976 if (GET_MODE (XEXP (op, 0)) == CCX_NOOVmode)
977 /* These are the only branches which work with CCX_NOOVmode. */
978 return (code == EQ || code == NE || code == GE || code == LT);
979 return (GET_MODE (XEXP (op, 0)) == CCXmode);
980 }
981
982 /* Nonzero if OP is a comparison operator suitable for use in v9
983 conditional move or branch on register contents instructions. */
984
985 int
v9_regcmp_op(register rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)986 v9_regcmp_op (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
987 {
988 enum rtx_code code = GET_CODE (op);
989
990 if (GET_RTX_CLASS (code) != '<')
991 return 0;
992
993 return v9_regcmp_p (code);
994 }
995
996 /* Return 1 if this is a SIGN_EXTEND or ZERO_EXTEND operation. */
997
998 int
extend_op(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)999 extend_op (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1000 {
1001 return GET_CODE (op) == SIGN_EXTEND || GET_CODE (op) == ZERO_EXTEND;
1002 }
1003
1004 /* Return nonzero if OP is an operator of mode MODE which can set
1005 the condition codes explicitly. We do not include PLUS and MINUS
1006 because these require CC_NOOVmode, which we handle explicitly. */
1007
1008 int
cc_arithop(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1009 cc_arithop (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1010 {
1011 if (GET_CODE (op) == AND
1012 || GET_CODE (op) == IOR
1013 || GET_CODE (op) == XOR)
1014 return 1;
1015
1016 return 0;
1017 }
1018
1019 /* Return nonzero if OP is an operator of mode MODE which can bitwise
1020 complement its second operand and set the condition codes explicitly. */
1021
1022 int
cc_arithopn(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1023 cc_arithopn (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1024 {
1025 /* XOR is not here because combine canonicalizes (xor (not ...) ...)
1026 and (xor ... (not ...)) to (not (xor ...)). */
1027 return (GET_CODE (op) == AND
1028 || GET_CODE (op) == IOR);
1029 }
1030
1031 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1032 signed 13 bit immediate field. This is an acceptable SImode operand for
1033 most 3 address instructions. */
1034
1035 int
arith_operand(rtx op,enum machine_mode mode)1036 arith_operand (rtx op, enum machine_mode mode)
1037 {
1038 if (register_operand (op, mode))
1039 return 1;
1040 if (GET_CODE (op) != CONST_INT)
1041 return 0;
1042 return SMALL_INT32 (op);
1043 }
1044
1045 /* Return true if OP is a constant 4096 */
1046
1047 int
arith_4096_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1048 arith_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1049 {
1050 if (GET_CODE (op) != CONST_INT)
1051 return 0;
1052 else
1053 return INTVAL (op) == 4096;
1054 }
1055
1056 /* Return true if OP is suitable as second operand for add/sub */
1057
1058 int
arith_add_operand(rtx op,enum machine_mode mode)1059 arith_add_operand (rtx op, enum machine_mode mode)
1060 {
1061 return arith_operand (op, mode) || arith_4096_operand (op, mode);
1062 }
1063
1064 /* Return true if OP is a CONST_INT or a CONST_DOUBLE which can fit in the
1065 immediate field of OR and XOR instructions. Used for 64-bit
1066 constant formation patterns. */
1067 int
const64_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1068 const64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1069 {
1070 return ((GET_CODE (op) == CONST_INT
1071 && SPARC_SIMM13_P (INTVAL (op)))
1072 #if HOST_BITS_PER_WIDE_INT != 64
1073 || (GET_CODE (op) == CONST_DOUBLE
1074 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1075 && (CONST_DOUBLE_HIGH (op) ==
1076 ((CONST_DOUBLE_LOW (op) & 0x80000000) != 0 ?
1077 (HOST_WIDE_INT)-1 : 0)))
1078 #endif
1079 );
1080 }
1081
1082 /* The same, but only for sethi instructions. */
1083 int
const64_high_operand(rtx op,enum machine_mode mode)1084 const64_high_operand (rtx op, enum machine_mode mode)
1085 {
1086 return ((GET_CODE (op) == CONST_INT
1087 && (INTVAL (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1088 && SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1089 )
1090 || (GET_CODE (op) == CONST_DOUBLE
1091 && CONST_DOUBLE_HIGH (op) == 0
1092 && (CONST_DOUBLE_LOW (op) & ~(HOST_WIDE_INT)0x3ff) != 0
1093 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op))));
1094 }
1095
1096 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1097 signed 11 bit immediate field. This is an acceptable SImode operand for
1098 the movcc instructions. */
1099
1100 int
arith11_operand(rtx op,enum machine_mode mode)1101 arith11_operand (rtx op, enum machine_mode mode)
1102 {
1103 return (register_operand (op, mode)
1104 || (GET_CODE (op) == CONST_INT && SPARC_SIMM11_P (INTVAL (op))));
1105 }
1106
1107 /* Return true if OP is a register, or is a CONST_INT that can fit in a
1108 signed 10 bit immediate field. This is an acceptable SImode operand for
1109 the movrcc instructions. */
1110
1111 int
arith10_operand(rtx op,enum machine_mode mode)1112 arith10_operand (rtx op, enum machine_mode mode)
1113 {
1114 return (register_operand (op, mode)
1115 || (GET_CODE (op) == CONST_INT && SPARC_SIMM10_P (INTVAL (op))));
1116 }
1117
1118 /* Return true if OP is a register, is a CONST_INT that fits in a 13 bit
1119 immediate field, or is a CONST_DOUBLE whose both parts fit in a 13 bit
1120 immediate field.
1121 v9: Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1122 can fit in a 13 bit immediate field. This is an acceptable DImode operand
1123 for most 3 address instructions. */
1124
1125 int
arith_double_operand(rtx op,enum machine_mode mode)1126 arith_double_operand (rtx op, enum machine_mode mode)
1127 {
1128 return (register_operand (op, mode)
1129 || (GET_CODE (op) == CONST_INT && SMALL_INT (op))
1130 || (! TARGET_ARCH64
1131 && GET_CODE (op) == CONST_DOUBLE
1132 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1133 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_HIGH (op) + 0x1000) < 0x2000)
1134 || (TARGET_ARCH64
1135 && GET_CODE (op) == CONST_DOUBLE
1136 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x1000) < 0x2000
1137 && ((CONST_DOUBLE_HIGH (op) == -1
1138 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0x1000)
1139 || (CONST_DOUBLE_HIGH (op) == 0
1140 && (CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
1141 }
1142
1143 /* Return true if OP is a constant 4096 for DImode on ARCH64 */
1144
1145 int
arith_double_4096_operand(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1146 arith_double_4096_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1147 {
1148 return (TARGET_ARCH64 &&
1149 ((GET_CODE (op) == CONST_INT && INTVAL (op) == 4096) ||
1150 (GET_CODE (op) == CONST_DOUBLE &&
1151 CONST_DOUBLE_LOW (op) == 4096 &&
1152 CONST_DOUBLE_HIGH (op) == 0)));
1153 }
1154
1155 /* Return true if OP is suitable as second operand for add/sub in DImode */
1156
1157 int
arith_double_add_operand(rtx op,enum machine_mode mode)1158 arith_double_add_operand (rtx op, enum machine_mode mode)
1159 {
1160 return arith_double_operand (op, mode) || arith_double_4096_operand (op, mode);
1161 }
1162
1163 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1164 can fit in an 11 bit immediate field. This is an acceptable DImode
1165 operand for the movcc instructions. */
1166 /* ??? Replace with arith11_operand? */
1167
1168 int
arith11_double_operand(rtx op,enum machine_mode mode)1169 arith11_double_operand (rtx op, enum machine_mode mode)
1170 {
1171 return (register_operand (op, mode)
1172 || (GET_CODE (op) == CONST_DOUBLE
1173 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1174 && (unsigned HOST_WIDE_INT) (CONST_DOUBLE_LOW (op) + 0x400) < 0x800
1175 && ((CONST_DOUBLE_HIGH (op) == -1
1176 && (CONST_DOUBLE_LOW (op) & 0x400) == 0x400)
1177 || (CONST_DOUBLE_HIGH (op) == 0
1178 && (CONST_DOUBLE_LOW (op) & 0x400) == 0)))
1179 || (GET_CODE (op) == CONST_INT
1180 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1181 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x400) < 0x800));
1182 }
1183
1184 /* Return true if OP is a register, or is a CONST_INT or CONST_DOUBLE that
1185 can fit in an 10 bit immediate field. This is an acceptable DImode
1186 operand for the movrcc instructions. */
1187 /* ??? Replace with arith10_operand? */
1188
1189 int
arith10_double_operand(rtx op,enum machine_mode mode)1190 arith10_double_operand (rtx op, enum machine_mode mode)
1191 {
1192 return (register_operand (op, mode)
1193 || (GET_CODE (op) == CONST_DOUBLE
1194 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1195 && (unsigned) (CONST_DOUBLE_LOW (op) + 0x200) < 0x400
1196 && ((CONST_DOUBLE_HIGH (op) == -1
1197 && (CONST_DOUBLE_LOW (op) & 0x200) == 0x200)
1198 || (CONST_DOUBLE_HIGH (op) == 0
1199 && (CONST_DOUBLE_LOW (op) & 0x200) == 0)))
1200 || (GET_CODE (op) == CONST_INT
1201 && (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode)
1202 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x200) < 0x400));
1203 }
1204
1205 /* Return truth value of whether OP is an integer which fits the
1206 range constraining immediate operands in most three-address insns,
1207 which have a 13 bit immediate field. */
1208
1209 int
small_int(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1210 small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1211 {
1212 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
1213 }
1214
1215 int
small_int_or_double(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1216 small_int_or_double (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1217 {
1218 return ((GET_CODE (op) == CONST_INT && SMALL_INT (op))
1219 || (GET_CODE (op) == CONST_DOUBLE
1220 && CONST_DOUBLE_HIGH (op) == 0
1221 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))));
1222 }
1223
1224 /* Recognize operand values for the umul instruction. That instruction sign
1225 extends immediate values just like all other sparc instructions, but
1226 interprets the extended result as an unsigned number. */
1227
1228 int
uns_small_int(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1229 uns_small_int (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1230 {
1231 #if HOST_BITS_PER_WIDE_INT > 32
1232 /* All allowed constants will fit a CONST_INT. */
1233 return (GET_CODE (op) == CONST_INT
1234 && ((INTVAL (op) >= 0 && INTVAL (op) < 0x1000)
1235 || (INTVAL (op) >= 0xFFFFF000
1236 && INTVAL (op) <= 0xFFFFFFFF)));
1237 #else
1238 return ((GET_CODE (op) == CONST_INT && (unsigned) INTVAL (op) < 0x1000)
1239 || (GET_CODE (op) == CONST_DOUBLE
1240 && CONST_DOUBLE_HIGH (op) == 0
1241 && (unsigned) CONST_DOUBLE_LOW (op) - 0xFFFFF000 < 0x1000));
1242 #endif
1243 }
1244
1245 int
uns_arith_operand(rtx op,enum machine_mode mode)1246 uns_arith_operand (rtx op, enum machine_mode mode)
1247 {
1248 return register_operand (op, mode) || uns_small_int (op, mode);
1249 }
1250
1251 /* Return truth value of statement that OP is a call-clobbered register. */
1252 int
clobbered_register(rtx op,enum machine_mode mode ATTRIBUTE_UNUSED)1253 clobbered_register (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1254 {
1255 return (GET_CODE (op) == REG && call_used_regs[REGNO (op)]);
1256 }
1257
1258 /* Return 1 if OP is a valid operand for the source of a move insn. */
1259
1260 int
input_operand(rtx op,enum machine_mode mode)1261 input_operand (rtx op, enum machine_mode mode)
1262 {
1263 /* If both modes are non-void they must be the same. */
1264 if (mode != VOIDmode && GET_MODE (op) != VOIDmode && mode != GET_MODE (op))
1265 return 0;
1266
1267 /* Accept CONSTANT_P_RTX, since it will be gone by CSE1 and result in 0/1. */
1268 if (GET_CODE (op) == CONSTANT_P_RTX)
1269 return 1;
1270
1271 /* Allow any one instruction integer constant, and all CONST_INT
1272 variants when we are working in DImode and !arch64. */
1273 if (GET_MODE_CLASS (mode) == MODE_INT
1274 && ((GET_CODE (op) == CONST_INT
1275 && (SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))
1276 || SPARC_SIMM13_P (INTVAL (op))
1277 || (mode == DImode
1278 && ! TARGET_ARCH64)))
1279 || (TARGET_ARCH64
1280 && GET_CODE (op) == CONST_DOUBLE
1281 && ((CONST_DOUBLE_HIGH (op) == 0
1282 && SPARC_SETHI_P (CONST_DOUBLE_LOW (op)))
1283 ||
1284 #if HOST_BITS_PER_WIDE_INT == 64
1285 (CONST_DOUBLE_HIGH (op) == 0
1286 && SPARC_SIMM13_P (CONST_DOUBLE_LOW (op)))
1287 #else
1288 (SPARC_SIMM13_P (CONST_DOUBLE_LOW (op))
1289 && (((CONST_DOUBLE_LOW (op) & 0x80000000) == 0
1290 && CONST_DOUBLE_HIGH (op) == 0)
1291 || (CONST_DOUBLE_HIGH (op) == -1
1292 && CONST_DOUBLE_LOW (op) & 0x80000000) != 0))
1293 #endif
1294 ))))
1295 return 1;
1296
1297 /* If !arch64 and this is a DImode const, allow it so that
1298 the splits can be generated. */
1299 if (! TARGET_ARCH64
1300 && mode == DImode
1301 && GET_CODE (op) == CONST_DOUBLE)
1302 return 1;
1303
1304 if (register_operand (op, mode))
1305 return 1;
1306
1307 if (GET_MODE_CLASS (mode) == MODE_FLOAT
1308 && GET_CODE (op) == CONST_DOUBLE)
1309 return 1;
1310
1311 /* If this is a SUBREG, look inside so that we handle
1312 paradoxical ones. */
1313 if (GET_CODE (op) == SUBREG)
1314 op = SUBREG_REG (op);
1315
1316 /* Check for valid MEM forms. */
1317 if (GET_CODE (op) == MEM)
1318 {
1319 rtx inside = XEXP (op, 0);
1320
1321 if (GET_CODE (inside) == LO_SUM)
1322 {
1323 /* We can't allow these because all of the splits
1324 (eventually as they trickle down into DFmode
1325 splits) require offsettable memory references. */
1326 if (! TARGET_V9
1327 && GET_MODE (op) == TFmode)
1328 return 0;
1329
1330 return (register_operand (XEXP (inside, 0), Pmode)
1331 && CONSTANT_P (XEXP (inside, 1)));
1332 }
1333 return memory_address_p (mode, inside);
1334 }
1335
1336 return 0;
1337 }
1338
1339 /* Return 1 if OP is valid for the lhs of a compare insn. */
1340
1341 int
compare_operand(rtx op,enum machine_mode mode)1342 compare_operand (rtx op, enum machine_mode mode)
1343 {
1344 if (GET_CODE (op) == ZERO_EXTRACT)
1345 return (register_operand (XEXP (op, 0), mode)
1346 && small_int_or_double (XEXP (op, 1), mode)
1347 && small_int_or_double (XEXP (op, 2), mode)
1348 /* This matches cmp_zero_extract. */
1349 && ((mode == SImode
1350 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1351 && INTVAL (XEXP (op, 2)) > 19)
1352 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1353 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 19)))
1354 /* This matches cmp_zero_extract_sp64. */
1355 || (mode == DImode
1356 && TARGET_ARCH64
1357 && ((GET_CODE (XEXP (op, 2)) == CONST_INT
1358 && INTVAL (XEXP (op, 2)) > 51)
1359 || (GET_CODE (XEXP (op, 2)) == CONST_DOUBLE
1360 && CONST_DOUBLE_LOW (XEXP (op, 2)) > 51)))));
1361 else
1362 return register_operand (op, mode);
1363 }
1364
1365
1366 /* We know it can't be done in one insn when we get here,
1367 the movsi expander guarantees this. */
1368 void
sparc_emit_set_const32(rtx op0,rtx op1)1369 sparc_emit_set_const32 (rtx op0, rtx op1)
1370 {
1371 enum machine_mode mode = GET_MODE (op0);
1372 rtx temp;
1373
1374 if (GET_CODE (op1) == CONST_INT)
1375 {
1376 HOST_WIDE_INT value = INTVAL (op1);
1377
1378 if (SPARC_SETHI_P (value & GET_MODE_MASK (mode))
1379 || SPARC_SIMM13_P (value))
1380 abort ();
1381 }
1382
1383 /* Full 2-insn decomposition is needed. */
1384 if (reload_in_progress || reload_completed)
1385 temp = op0;
1386 else
1387 temp = gen_reg_rtx (mode);
1388
1389 if (GET_CODE (op1) == CONST_INT)
1390 {
1391 /* Emit them as real moves instead of a HIGH/LO_SUM,
1392 this way CSE can see everything and reuse intermediate
1393 values if it wants. */
1394 if (TARGET_ARCH64
1395 && HOST_BITS_PER_WIDE_INT != 64
1396 && (INTVAL (op1) & 0x80000000) != 0)
1397 emit_insn (gen_rtx_SET
1398 (VOIDmode, temp,
1399 immed_double_const (INTVAL (op1) & ~(HOST_WIDE_INT)0x3ff,
1400 0, DImode)));
1401 else
1402 emit_insn (gen_rtx_SET (VOIDmode, temp,
1403 GEN_INT (INTVAL (op1)
1404 & ~(HOST_WIDE_INT)0x3ff)));
1405
1406 emit_insn (gen_rtx_SET (VOIDmode,
1407 op0,
1408 gen_rtx_IOR (mode, temp,
1409 GEN_INT (INTVAL (op1) & 0x3ff))));
1410 }
1411 else
1412 {
1413 /* A symbol, emit in the traditional way. */
1414 emit_insn (gen_rtx_SET (VOIDmode, temp,
1415 gen_rtx_HIGH (mode, op1)));
1416 emit_insn (gen_rtx_SET (VOIDmode,
1417 op0, gen_rtx_LO_SUM (mode, temp, op1)));
1418
1419 }
1420 }
1421
1422
1423 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register.
1424 If TEMP is non-zero, we are forbidden to use any other scratch
1425 registers. Otherwise, we are allowed to generate them as needed.
1426
1427 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY
1428 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */
1429 void
sparc_emit_set_symbolic_const64(rtx op0,rtx op1,rtx temp)1430 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp)
1431 {
1432 rtx temp1, temp2, temp3, temp4, temp5;
1433 rtx ti_temp = 0;
1434
1435 if (temp && GET_MODE (temp) == TImode)
1436 {
1437 ti_temp = temp;
1438 temp = gen_rtx_REG (DImode, REGNO (temp));
1439 }
1440
1441 /* SPARC-V9 code-model support. */
1442 switch (sparc_cmodel)
1443 {
1444 case CM_MEDLOW:
1445 /* The range spanned by all instructions in the object is less
1446 than 2^31 bytes (2GB) and the distance from any instruction
1447 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1448 than 2^31 bytes (2GB).
1449
1450 The executable must be in the low 4TB of the virtual address
1451 space.
1452
1453 sethi %hi(symbol), %temp1
1454 or %temp1, %lo(symbol), %reg */
1455 if (temp)
1456 temp1 = temp; /* op0 is allowed. */
1457 else
1458 temp1 = gen_reg_rtx (DImode);
1459
1460 emit_insn (gen_rtx_SET (VOIDmode, temp1, gen_rtx_HIGH (DImode, op1)));
1461 emit_insn (gen_rtx_SET (VOIDmode, op0, gen_rtx_LO_SUM (DImode, temp1, op1)));
1462 break;
1463
1464 case CM_MEDMID:
1465 /* The range spanned by all instructions in the object is less
1466 than 2^31 bytes (2GB) and the distance from any instruction
1467 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1468 than 2^31 bytes (2GB).
1469
1470 The executable must be in the low 16TB of the virtual address
1471 space.
1472
1473 sethi %h44(symbol), %temp1
1474 or %temp1, %m44(symbol), %temp2
1475 sllx %temp2, 12, %temp3
1476 or %temp3, %l44(symbol), %reg */
1477 if (temp)
1478 {
1479 temp1 = op0;
1480 temp2 = op0;
1481 temp3 = temp; /* op0 is allowed. */
1482 }
1483 else
1484 {
1485 temp1 = gen_reg_rtx (DImode);
1486 temp2 = gen_reg_rtx (DImode);
1487 temp3 = gen_reg_rtx (DImode);
1488 }
1489
1490 emit_insn (gen_seth44 (temp1, op1));
1491 emit_insn (gen_setm44 (temp2, temp1, op1));
1492 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1493 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12))));
1494 emit_insn (gen_setl44 (op0, temp3, op1));
1495 break;
1496
1497 case CM_MEDANY:
1498 /* The range spanned by all instructions in the object is less
1499 than 2^31 bytes (2GB) and the distance from any instruction
1500 to the location of the label _GLOBAL_OFFSET_TABLE_ is less
1501 than 2^31 bytes (2GB).
1502
1503 The executable can be placed anywhere in the virtual address
1504 space.
1505
1506 sethi %hh(symbol), %temp1
1507 sethi %lm(symbol), %temp2
1508 or %temp1, %hm(symbol), %temp3
1509 sllx %temp3, 32, %temp4
1510 or %temp4, %temp2, %temp5
1511 or %temp5, %lo(symbol), %reg */
1512 if (temp)
1513 {
1514 /* It is possible that one of the registers we got for operands[2]
1515 might coincide with that of operands[0] (which is why we made
1516 it TImode). Pick the other one to use as our scratch. */
1517 if (rtx_equal_p (temp, op0))
1518 {
1519 if (ti_temp)
1520 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1521 else
1522 abort();
1523 }
1524 temp1 = op0;
1525 temp2 = temp; /* op0 is _not_ allowed, see above. */
1526 temp3 = op0;
1527 temp4 = op0;
1528 temp5 = op0;
1529 }
1530 else
1531 {
1532 temp1 = gen_reg_rtx (DImode);
1533 temp2 = gen_reg_rtx (DImode);
1534 temp3 = gen_reg_rtx (DImode);
1535 temp4 = gen_reg_rtx (DImode);
1536 temp5 = gen_reg_rtx (DImode);
1537 }
1538
1539 emit_insn (gen_sethh (temp1, op1));
1540 emit_insn (gen_setlm (temp2, op1));
1541 emit_insn (gen_sethm (temp3, temp1, op1));
1542 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1543 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1544 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1545 gen_rtx_PLUS (DImode, temp4, temp2)));
1546 emit_insn (gen_setlo (op0, temp5, op1));
1547 break;
1548
1549 case CM_EMBMEDANY:
1550 /* Old old old backwards compatibility kruft here.
1551 Essentially it is MEDLOW with a fixed 64-bit
1552 virtual base added to all data segment addresses.
1553 Text-segment stuff is computed like MEDANY, we can't
1554 reuse the code above because the relocation knobs
1555 look different.
1556
1557 Data segment: sethi %hi(symbol), %temp1
1558 add %temp1, EMBMEDANY_BASE_REG, %temp2
1559 or %temp2, %lo(symbol), %reg */
1560 if (data_segment_operand (op1, GET_MODE (op1)))
1561 {
1562 if (temp)
1563 {
1564 temp1 = temp; /* op0 is allowed. */
1565 temp2 = op0;
1566 }
1567 else
1568 {
1569 temp1 = gen_reg_rtx (DImode);
1570 temp2 = gen_reg_rtx (DImode);
1571 }
1572
1573 emit_insn (gen_embmedany_sethi (temp1, op1));
1574 emit_insn (gen_embmedany_brsum (temp2, temp1));
1575 emit_insn (gen_embmedany_losum (op0, temp2, op1));
1576 }
1577
1578 /* Text segment: sethi %uhi(symbol), %temp1
1579 sethi %hi(symbol), %temp2
1580 or %temp1, %ulo(symbol), %temp3
1581 sllx %temp3, 32, %temp4
1582 or %temp4, %temp2, %temp5
1583 or %temp5, %lo(symbol), %reg */
1584 else
1585 {
1586 if (temp)
1587 {
1588 /* It is possible that one of the registers we got for operands[2]
1589 might coincide with that of operands[0] (which is why we made
1590 it TImode). Pick the other one to use as our scratch. */
1591 if (rtx_equal_p (temp, op0))
1592 {
1593 if (ti_temp)
1594 temp = gen_rtx_REG (DImode, REGNO (temp) + 1);
1595 else
1596 abort();
1597 }
1598 temp1 = op0;
1599 temp2 = temp; /* op0 is _not_ allowed, see above. */
1600 temp3 = op0;
1601 temp4 = op0;
1602 temp5 = op0;
1603 }
1604 else
1605 {
1606 temp1 = gen_reg_rtx (DImode);
1607 temp2 = gen_reg_rtx (DImode);
1608 temp3 = gen_reg_rtx (DImode);
1609 temp4 = gen_reg_rtx (DImode);
1610 temp5 = gen_reg_rtx (DImode);
1611 }
1612
1613 emit_insn (gen_embmedany_textuhi (temp1, op1));
1614 emit_insn (gen_embmedany_texthi (temp2, op1));
1615 emit_insn (gen_embmedany_textulo (temp3, temp1, op1));
1616 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1617 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32))));
1618 emit_insn (gen_rtx_SET (VOIDmode, temp5,
1619 gen_rtx_PLUS (DImode, temp4, temp2)));
1620 emit_insn (gen_embmedany_textlo (op0, temp5, op1));
1621 }
1622 break;
1623
1624 default:
1625 abort();
1626 }
1627 }
1628
1629 /* These avoid problems when cross compiling. If we do not
1630 go through all this hair then the optimizer will see
1631 invalid REG_EQUAL notes or in some cases none at all. */
1632 static void sparc_emit_set_safe_HIGH64 (rtx, HOST_WIDE_INT);
1633 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT);
1634 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT);
1635 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT);
1636
1637 #if HOST_BITS_PER_WIDE_INT == 64
1638 #define GEN_HIGHINT64(__x) GEN_INT ((__x) & ~(HOST_WIDE_INT)0x3ff)
1639 #define GEN_INT64(__x) GEN_INT (__x)
1640 #else
1641 #define GEN_HIGHINT64(__x) \
1642 immed_double_const ((__x) & ~(HOST_WIDE_INT)0x3ff, 0, DImode)
1643 #define GEN_INT64(__x) \
1644 immed_double_const ((__x) & 0xffffffff, \
1645 ((__x) & 0x80000000 ? -1 : 0), DImode)
1646 #endif
1647
1648 /* The optimizer is not to assume anything about exactly
1649 which bits are set for a HIGH, they are unspecified.
1650 Unfortunately this leads to many missed optimizations
1651 during CSE. We mask out the non-HIGH bits, and matches
1652 a plain movdi, to alleviate this problem. */
1653 static void
sparc_emit_set_safe_HIGH64(rtx dest,HOST_WIDE_INT val)1654 sparc_emit_set_safe_HIGH64 (rtx dest, HOST_WIDE_INT val)
1655 {
1656 emit_insn (gen_rtx_SET (VOIDmode, dest, GEN_HIGHINT64 (val)));
1657 }
1658
1659 static rtx
gen_safe_SET64(rtx dest,HOST_WIDE_INT val)1660 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val)
1661 {
1662 return gen_rtx_SET (VOIDmode, dest, GEN_INT64 (val));
1663 }
1664
1665 static rtx
gen_safe_OR64(rtx src,HOST_WIDE_INT val)1666 gen_safe_OR64 (rtx src, HOST_WIDE_INT val)
1667 {
1668 return gen_rtx_IOR (DImode, src, GEN_INT64 (val));
1669 }
1670
1671 static rtx
gen_safe_XOR64(rtx src,HOST_WIDE_INT val)1672 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val)
1673 {
1674 return gen_rtx_XOR (DImode, src, GEN_INT64 (val));
1675 }
1676
1677 /* Worker routines for 64-bit constant formation on arch64.
1678 One of the key things to be doing in these emissions is
1679 to create as many temp REGs as possible. This makes it
1680 possible for half-built constants to be used later when
1681 such values are similar to something required later on.
1682 Without doing this, the optimizer cannot see such
1683 opportunities. */
1684
1685 static void sparc_emit_set_const64_quick1 (rtx, rtx,
1686 unsigned HOST_WIDE_INT, int);
1687
1688 static void
sparc_emit_set_const64_quick1(rtx op0,rtx temp,unsigned HOST_WIDE_INT low_bits,int is_neg)1689 sparc_emit_set_const64_quick1 (rtx op0, rtx temp,
1690 unsigned HOST_WIDE_INT low_bits, int is_neg)
1691 {
1692 unsigned HOST_WIDE_INT high_bits;
1693
1694 if (is_neg)
1695 high_bits = (~low_bits) & 0xffffffff;
1696 else
1697 high_bits = low_bits;
1698
1699 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1700 if (!is_neg)
1701 {
1702 emit_insn (gen_rtx_SET (VOIDmode, op0,
1703 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1704 }
1705 else
1706 {
1707 /* If we are XOR'ing with -1, then we should emit a one's complement
1708 instead. This way the combiner will notice logical operations
1709 such as ANDN later on and substitute. */
1710 if ((low_bits & 0x3ff) == 0x3ff)
1711 {
1712 emit_insn (gen_rtx_SET (VOIDmode, op0,
1713 gen_rtx_NOT (DImode, temp)));
1714 }
1715 else
1716 {
1717 emit_insn (gen_rtx_SET (VOIDmode, op0,
1718 gen_safe_XOR64 (temp,
1719 (-(HOST_WIDE_INT)0x400
1720 | (low_bits & 0x3ff)))));
1721 }
1722 }
1723 }
1724
1725 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT,
1726 unsigned HOST_WIDE_INT, int);
1727
1728 static void
sparc_emit_set_const64_quick2(rtx op0,rtx temp,unsigned HOST_WIDE_INT high_bits,unsigned HOST_WIDE_INT low_immediate,int shift_count)1729 sparc_emit_set_const64_quick2 (rtx op0, rtx temp,
1730 unsigned HOST_WIDE_INT high_bits,
1731 unsigned HOST_WIDE_INT low_immediate,
1732 int shift_count)
1733 {
1734 rtx temp2 = op0;
1735
1736 if ((high_bits & 0xfffffc00) != 0)
1737 {
1738 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1739 if ((high_bits & ~0xfffffc00) != 0)
1740 emit_insn (gen_rtx_SET (VOIDmode, op0,
1741 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1742 else
1743 temp2 = temp;
1744 }
1745 else
1746 {
1747 emit_insn (gen_safe_SET64 (temp, high_bits));
1748 temp2 = temp;
1749 }
1750
1751 /* Now shift it up into place. */
1752 emit_insn (gen_rtx_SET (VOIDmode, op0,
1753 gen_rtx_ASHIFT (DImode, temp2,
1754 GEN_INT (shift_count))));
1755
1756 /* If there is a low immediate part piece, finish up by
1757 putting that in as well. */
1758 if (low_immediate != 0)
1759 emit_insn (gen_rtx_SET (VOIDmode, op0,
1760 gen_safe_OR64 (op0, low_immediate)));
1761 }
1762
1763 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT,
1764 unsigned HOST_WIDE_INT);
1765
1766 /* Full 64-bit constant decomposition. Even though this is the
1767 'worst' case, we still optimize a few things away. */
1768 static void
sparc_emit_set_const64_longway(rtx op0,rtx temp,unsigned HOST_WIDE_INT high_bits,unsigned HOST_WIDE_INT low_bits)1769 sparc_emit_set_const64_longway (rtx op0, rtx temp,
1770 unsigned HOST_WIDE_INT high_bits,
1771 unsigned HOST_WIDE_INT low_bits)
1772 {
1773 rtx sub_temp;
1774
1775 if (reload_in_progress || reload_completed)
1776 sub_temp = op0;
1777 else
1778 sub_temp = gen_reg_rtx (DImode);
1779
1780 if ((high_bits & 0xfffffc00) != 0)
1781 {
1782 sparc_emit_set_safe_HIGH64 (temp, high_bits);
1783 if ((high_bits & ~0xfffffc00) != 0)
1784 emit_insn (gen_rtx_SET (VOIDmode,
1785 sub_temp,
1786 gen_safe_OR64 (temp, (high_bits & 0x3ff))));
1787 else
1788 sub_temp = temp;
1789 }
1790 else
1791 {
1792 emit_insn (gen_safe_SET64 (temp, high_bits));
1793 sub_temp = temp;
1794 }
1795
1796 if (!reload_in_progress && !reload_completed)
1797 {
1798 rtx temp2 = gen_reg_rtx (DImode);
1799 rtx temp3 = gen_reg_rtx (DImode);
1800 rtx temp4 = gen_reg_rtx (DImode);
1801
1802 emit_insn (gen_rtx_SET (VOIDmode, temp4,
1803 gen_rtx_ASHIFT (DImode, sub_temp,
1804 GEN_INT (32))));
1805
1806 sparc_emit_set_safe_HIGH64 (temp2, low_bits);
1807 if ((low_bits & ~0xfffffc00) != 0)
1808 {
1809 emit_insn (gen_rtx_SET (VOIDmode, temp3,
1810 gen_safe_OR64 (temp2, (low_bits & 0x3ff))));
1811 emit_insn (gen_rtx_SET (VOIDmode, op0,
1812 gen_rtx_PLUS (DImode, temp4, temp3)));
1813 }
1814 else
1815 {
1816 emit_insn (gen_rtx_SET (VOIDmode, op0,
1817 gen_rtx_PLUS (DImode, temp4, temp2)));
1818 }
1819 }
1820 else
1821 {
1822 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff);
1823 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff);
1824 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff);
1825 int to_shift = 12;
1826
1827 /* We are in the middle of reload, so this is really
1828 painful. However we do still make an attempt to
1829 avoid emitting truly stupid code. */
1830 if (low1 != const0_rtx)
1831 {
1832 emit_insn (gen_rtx_SET (VOIDmode, op0,
1833 gen_rtx_ASHIFT (DImode, sub_temp,
1834 GEN_INT (to_shift))));
1835 emit_insn (gen_rtx_SET (VOIDmode, op0,
1836 gen_rtx_IOR (DImode, op0, low1)));
1837 sub_temp = op0;
1838 to_shift = 12;
1839 }
1840 else
1841 {
1842 to_shift += 12;
1843 }
1844 if (low2 != const0_rtx)
1845 {
1846 emit_insn (gen_rtx_SET (VOIDmode, op0,
1847 gen_rtx_ASHIFT (DImode, sub_temp,
1848 GEN_INT (to_shift))));
1849 emit_insn (gen_rtx_SET (VOIDmode, op0,
1850 gen_rtx_IOR (DImode, op0, low2)));
1851 sub_temp = op0;
1852 to_shift = 8;
1853 }
1854 else
1855 {
1856 to_shift += 8;
1857 }
1858 emit_insn (gen_rtx_SET (VOIDmode, op0,
1859 gen_rtx_ASHIFT (DImode, sub_temp,
1860 GEN_INT (to_shift))));
1861 if (low3 != const0_rtx)
1862 emit_insn (gen_rtx_SET (VOIDmode, op0,
1863 gen_rtx_IOR (DImode, op0, low3)));
1864 /* phew... */
1865 }
1866 }
1867
1868 /* Analyze a 64-bit constant for certain properties. */
1869 static void analyze_64bit_constant (unsigned HOST_WIDE_INT,
1870 unsigned HOST_WIDE_INT,
1871 int *, int *, int *);
1872
1873 static void
analyze_64bit_constant(unsigned HOST_WIDE_INT high_bits,unsigned HOST_WIDE_INT low_bits,int * hbsp,int * lbsp,int * abbasp)1874 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits,
1875 unsigned HOST_WIDE_INT low_bits,
1876 int *hbsp, int *lbsp, int *abbasp)
1877 {
1878 int lowest_bit_set, highest_bit_set, all_bits_between_are_set;
1879 int i;
1880
1881 lowest_bit_set = highest_bit_set = -1;
1882 i = 0;
1883 do
1884 {
1885 if ((lowest_bit_set == -1)
1886 && ((low_bits >> i) & 1))
1887 lowest_bit_set = i;
1888 if ((highest_bit_set == -1)
1889 && ((high_bits >> (32 - i - 1)) & 1))
1890 highest_bit_set = (64 - i - 1);
1891 }
1892 while (++i < 32
1893 && ((highest_bit_set == -1)
1894 || (lowest_bit_set == -1)));
1895 if (i == 32)
1896 {
1897 i = 0;
1898 do
1899 {
1900 if ((lowest_bit_set == -1)
1901 && ((high_bits >> i) & 1))
1902 lowest_bit_set = i + 32;
1903 if ((highest_bit_set == -1)
1904 && ((low_bits >> (32 - i - 1)) & 1))
1905 highest_bit_set = 32 - i - 1;
1906 }
1907 while (++i < 32
1908 && ((highest_bit_set == -1)
1909 || (lowest_bit_set == -1)));
1910 }
1911 /* If there are no bits set this should have gone out
1912 as one instruction! */
1913 if (lowest_bit_set == -1
1914 || highest_bit_set == -1)
1915 abort ();
1916 all_bits_between_are_set = 1;
1917 for (i = lowest_bit_set; i <= highest_bit_set; i++)
1918 {
1919 if (i < 32)
1920 {
1921 if ((low_bits & (1 << i)) != 0)
1922 continue;
1923 }
1924 else
1925 {
1926 if ((high_bits & (1 << (i - 32))) != 0)
1927 continue;
1928 }
1929 all_bits_between_are_set = 0;
1930 break;
1931 }
1932 *hbsp = highest_bit_set;
1933 *lbsp = lowest_bit_set;
1934 *abbasp = all_bits_between_are_set;
1935 }
1936
1937 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT);
1938
1939 static int
const64_is_2insns(unsigned HOST_WIDE_INT high_bits,unsigned HOST_WIDE_INT low_bits)1940 const64_is_2insns (unsigned HOST_WIDE_INT high_bits,
1941 unsigned HOST_WIDE_INT low_bits)
1942 {
1943 int highest_bit_set, lowest_bit_set, all_bits_between_are_set;
1944
1945 if (high_bits == 0
1946 || high_bits == 0xffffffff)
1947 return 1;
1948
1949 analyze_64bit_constant (high_bits, low_bits,
1950 &highest_bit_set, &lowest_bit_set,
1951 &all_bits_between_are_set);
1952
1953 if ((highest_bit_set == 63
1954 || lowest_bit_set == 0)
1955 && all_bits_between_are_set != 0)
1956 return 1;
1957
1958 if ((highest_bit_set - lowest_bit_set) < 21)
1959 return 1;
1960
1961 return 0;
1962 }
1963
1964 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT,
1965 unsigned HOST_WIDE_INT,
1966 int, int);
1967
1968 static unsigned HOST_WIDE_INT
create_simple_focus_bits(unsigned HOST_WIDE_INT high_bits,unsigned HOST_WIDE_INT low_bits,int lowest_bit_set,int shift)1969 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits,
1970 unsigned HOST_WIDE_INT low_bits,
1971 int lowest_bit_set, int shift)
1972 {
1973 HOST_WIDE_INT hi, lo;
1974
1975 if (lowest_bit_set < 32)
1976 {
1977 lo = (low_bits >> lowest_bit_set) << shift;
1978 hi = ((high_bits << (32 - lowest_bit_set)) << shift);
1979 }
1980 else
1981 {
1982 lo = 0;
1983 hi = ((high_bits >> (lowest_bit_set - 32)) << shift);
1984 }
1985 if (hi & lo)
1986 abort ();
1987 return (hi | lo);
1988 }
1989
1990 /* Here we are sure to be arch64 and this is an integer constant
1991 being loaded into a register. Emit the most efficient
1992 insn sequence possible. Detection of all the 1-insn cases
1993 has been done already. */
1994 void
sparc_emit_set_const64(rtx op0,rtx op1)1995 sparc_emit_set_const64 (rtx op0, rtx op1)
1996 {
1997 unsigned HOST_WIDE_INT high_bits, low_bits;
1998 int lowest_bit_set, highest_bit_set;
1999 int all_bits_between_are_set;
2000 rtx temp = 0;
2001
2002 /* Sanity check that we know what we are working with. */
2003 if (! TARGET_ARCH64)
2004 abort ();
2005
2006 if (GET_CODE (op0) != SUBREG)
2007 {
2008 if (GET_CODE (op0) != REG
2009 || (REGNO (op0) >= SPARC_FIRST_FP_REG
2010 && REGNO (op0) <= SPARC_LAST_V9_FP_REG))
2011 abort ();
2012 }
2013
2014 if (reload_in_progress || reload_completed)
2015 temp = op0;
2016
2017 if (GET_CODE (op1) != CONST_DOUBLE
2018 && GET_CODE (op1) != CONST_INT)
2019 {
2020 sparc_emit_set_symbolic_const64 (op0, op1, temp);
2021 return;
2022 }
2023
2024 if (! temp)
2025 temp = gen_reg_rtx (DImode);
2026
2027 if (GET_CODE (op1) == CONST_DOUBLE)
2028 {
2029 #if HOST_BITS_PER_WIDE_INT == 64
2030 high_bits = (CONST_DOUBLE_LOW (op1) >> 32) & 0xffffffff;
2031 low_bits = CONST_DOUBLE_LOW (op1) & 0xffffffff;
2032 #else
2033 high_bits = CONST_DOUBLE_HIGH (op1);
2034 low_bits = CONST_DOUBLE_LOW (op1);
2035 #endif
2036 }
2037 else
2038 {
2039 #if HOST_BITS_PER_WIDE_INT == 64
2040 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff);
2041 low_bits = (INTVAL (op1) & 0xffffffff);
2042 #else
2043 high_bits = ((INTVAL (op1) < 0) ?
2044 0xffffffff :
2045 0x00000000);
2046 low_bits = INTVAL (op1);
2047 #endif
2048 }
2049
2050 /* low_bits bits 0 --> 31
2051 high_bits bits 32 --> 63 */
2052
2053 analyze_64bit_constant (high_bits, low_bits,
2054 &highest_bit_set, &lowest_bit_set,
2055 &all_bits_between_are_set);
2056
2057 /* First try for a 2-insn sequence. */
2058
2059 /* These situations are preferred because the optimizer can
2060 * do more things with them:
2061 * 1) mov -1, %reg
2062 * sllx %reg, shift, %reg
2063 * 2) mov -1, %reg
2064 * srlx %reg, shift, %reg
2065 * 3) mov some_small_const, %reg
2066 * sllx %reg, shift, %reg
2067 */
2068 if (((highest_bit_set == 63
2069 || lowest_bit_set == 0)
2070 && all_bits_between_are_set != 0)
2071 || ((highest_bit_set - lowest_bit_set) < 12))
2072 {
2073 HOST_WIDE_INT the_const = -1;
2074 int shift = lowest_bit_set;
2075
2076 if ((highest_bit_set != 63
2077 && lowest_bit_set != 0)
2078 || all_bits_between_are_set == 0)
2079 {
2080 the_const =
2081 create_simple_focus_bits (high_bits, low_bits,
2082 lowest_bit_set, 0);
2083 }
2084 else if (lowest_bit_set == 0)
2085 shift = -(63 - highest_bit_set);
2086
2087 if (! SPARC_SIMM13_P (the_const))
2088 abort ();
2089
2090 emit_insn (gen_safe_SET64 (temp, the_const));
2091 if (shift > 0)
2092 emit_insn (gen_rtx_SET (VOIDmode,
2093 op0,
2094 gen_rtx_ASHIFT (DImode,
2095 temp,
2096 GEN_INT (shift))));
2097 else if (shift < 0)
2098 emit_insn (gen_rtx_SET (VOIDmode,
2099 op0,
2100 gen_rtx_LSHIFTRT (DImode,
2101 temp,
2102 GEN_INT (-shift))));
2103 else
2104 abort ();
2105 return;
2106 }
2107
2108 /* Now a range of 22 or less bits set somewhere.
2109 * 1) sethi %hi(focus_bits), %reg
2110 * sllx %reg, shift, %reg
2111 * 2) sethi %hi(focus_bits), %reg
2112 * srlx %reg, shift, %reg
2113 */
2114 if ((highest_bit_set - lowest_bit_set) < 21)
2115 {
2116 unsigned HOST_WIDE_INT focus_bits =
2117 create_simple_focus_bits (high_bits, low_bits,
2118 lowest_bit_set, 10);
2119
2120 if (! SPARC_SETHI_P (focus_bits))
2121 abort ();
2122
2123 sparc_emit_set_safe_HIGH64 (temp, focus_bits);
2124
2125 /* If lowest_bit_set == 10 then a sethi alone could have done it. */
2126 if (lowest_bit_set < 10)
2127 emit_insn (gen_rtx_SET (VOIDmode,
2128 op0,
2129 gen_rtx_LSHIFTRT (DImode, temp,
2130 GEN_INT (10 - lowest_bit_set))));
2131 else if (lowest_bit_set > 10)
2132 emit_insn (gen_rtx_SET (VOIDmode,
2133 op0,
2134 gen_rtx_ASHIFT (DImode, temp,
2135 GEN_INT (lowest_bit_set - 10))));
2136 else
2137 abort ();
2138 return;
2139 }
2140
2141 /* 1) sethi %hi(low_bits), %reg
2142 * or %reg, %lo(low_bits), %reg
2143 * 2) sethi %hi(~low_bits), %reg
2144 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg
2145 */
2146 if (high_bits == 0
2147 || high_bits == 0xffffffff)
2148 {
2149 sparc_emit_set_const64_quick1 (op0, temp, low_bits,
2150 (high_bits == 0xffffffff));
2151 return;
2152 }
2153
2154 /* Now, try 3-insn sequences. */
2155
2156 /* 1) sethi %hi(high_bits), %reg
2157 * or %reg, %lo(high_bits), %reg
2158 * sllx %reg, 32, %reg
2159 */
2160 if (low_bits == 0)
2161 {
2162 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32);
2163 return;
2164 }
2165
2166 /* We may be able to do something quick
2167 when the constant is negated, so try that. */
2168 if (const64_is_2insns ((~high_bits) & 0xffffffff,
2169 (~low_bits) & 0xfffffc00))
2170 {
2171 /* NOTE: The trailing bits get XOR'd so we need the
2172 non-negated bits, not the negated ones. */
2173 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff;
2174
2175 if ((((~high_bits) & 0xffffffff) == 0
2176 && ((~low_bits) & 0x80000000) == 0)
2177 || (((~high_bits) & 0xffffffff) == 0xffffffff
2178 && ((~low_bits) & 0x80000000) != 0))
2179 {
2180 int fast_int = (~low_bits & 0xffffffff);
2181
2182 if ((SPARC_SETHI_P (fast_int)
2183 && (~high_bits & 0xffffffff) == 0)
2184 || SPARC_SIMM13_P (fast_int))
2185 emit_insn (gen_safe_SET64 (temp, fast_int));
2186 else
2187 sparc_emit_set_const64 (temp, GEN_INT64 (fast_int));
2188 }
2189 else
2190 {
2191 rtx negated_const;
2192 #if HOST_BITS_PER_WIDE_INT == 64
2193 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) |
2194 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32));
2195 #else
2196 negated_const = immed_double_const ((~low_bits) & 0xfffffc00,
2197 (~high_bits) & 0xffffffff,
2198 DImode);
2199 #endif
2200 sparc_emit_set_const64 (temp, negated_const);
2201 }
2202
2203 /* If we are XOR'ing with -1, then we should emit a one's complement
2204 instead. This way the combiner will notice logical operations
2205 such as ANDN later on and substitute. */
2206 if (trailing_bits == 0x3ff)
2207 {
2208 emit_insn (gen_rtx_SET (VOIDmode, op0,
2209 gen_rtx_NOT (DImode, temp)));
2210 }
2211 else
2212 {
2213 emit_insn (gen_rtx_SET (VOIDmode,
2214 op0,
2215 gen_safe_XOR64 (temp,
2216 (-0x400 | trailing_bits))));
2217 }
2218 return;
2219 }
2220
2221 /* 1) sethi %hi(xxx), %reg
2222 * or %reg, %lo(xxx), %reg
2223 * sllx %reg, yyy, %reg
2224 *
2225 * ??? This is just a generalized version of the low_bits==0
2226 * thing above, FIXME...
2227 */
2228 if ((highest_bit_set - lowest_bit_set) < 32)
2229 {
2230 unsigned HOST_WIDE_INT focus_bits =
2231 create_simple_focus_bits (high_bits, low_bits,
2232 lowest_bit_set, 0);
2233
2234 /* We can't get here in this state. */
2235 if (highest_bit_set < 32
2236 || lowest_bit_set >= 32)
2237 abort ();
2238
2239 /* So what we know is that the set bits straddle the
2240 middle of the 64-bit word. */
2241 sparc_emit_set_const64_quick2 (op0, temp,
2242 focus_bits, 0,
2243 lowest_bit_set);
2244 return;
2245 }
2246
2247 /* 1) sethi %hi(high_bits), %reg
2248 * or %reg, %lo(high_bits), %reg
2249 * sllx %reg, 32, %reg
2250 * or %reg, low_bits, %reg
2251 */
2252 if (SPARC_SIMM13_P(low_bits)
2253 && ((int)low_bits > 0))
2254 {
2255 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32);
2256 return;
2257 }
2258
2259 /* The easiest way when all else fails, is full decomposition. */
2260 #if 0
2261 printf ("sparc_emit_set_const64: Hard constant [%08lx%08lx] neg[%08lx%08lx]\n",
2262 high_bits, low_bits, ~high_bits, ~low_bits);
2263 #endif
2264 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits);
2265 }
2266
2267 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
2268 return the mode to be used for the comparison. For floating-point,
2269 CCFP[E]mode is used. CC_NOOVmode should be used when the first operand
2270 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special
2271 processing is needed. */
2272
2273 enum machine_mode
select_cc_mode(enum rtx_code op,rtx x,rtx y ATTRIBUTE_UNUSED)2274 select_cc_mode (enum rtx_code op, rtx x, rtx y ATTRIBUTE_UNUSED)
2275 {
2276 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2277 {
2278 switch (op)
2279 {
2280 case EQ:
2281 case NE:
2282 case UNORDERED:
2283 case ORDERED:
2284 case UNLT:
2285 case UNLE:
2286 case UNGT:
2287 case UNGE:
2288 case UNEQ:
2289 case LTGT:
2290 return CCFPmode;
2291
2292 case LT:
2293 case LE:
2294 case GT:
2295 case GE:
2296 return CCFPEmode;
2297
2298 default:
2299 abort ();
2300 }
2301 }
2302 else if (GET_CODE (x) == PLUS || GET_CODE (x) == MINUS
2303 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT)
2304 {
2305 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2306 return CCX_NOOVmode;
2307 else
2308 return CC_NOOVmode;
2309 }
2310 else
2311 {
2312 if (TARGET_ARCH64 && GET_MODE (x) == DImode)
2313 return CCXmode;
2314 else
2315 return CCmode;
2316 }
2317 }
2318
2319 /* X and Y are two things to compare using CODE. Emit the compare insn and
2320 return the rtx for the cc reg in the proper mode. */
2321
2322 rtx
gen_compare_reg(enum rtx_code code,rtx x,rtx y)2323 gen_compare_reg (enum rtx_code code, rtx x, rtx y)
2324 {
2325 enum machine_mode mode = SELECT_CC_MODE (code, x, y);
2326 rtx cc_reg;
2327
2328 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the
2329 fcc regs (cse can't tell they're really call clobbered regs and will
2330 remove a duplicate comparison even if there is an intervening function
2331 call - it will then try to reload the cc reg via an int reg which is why
2332 we need the movcc patterns). It is possible to provide the movcc
2333 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two
2334 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be
2335 to tell cse that CCFPE mode registers (even pseudos) are call
2336 clobbered. */
2337
2338 /* ??? This is an experiment. Rather than making changes to cse which may
2339 or may not be easy/clean, we do our own cse. This is possible because
2340 we will generate hard registers. Cse knows they're call clobbered (it
2341 doesn't know the same thing about pseudos). If we guess wrong, no big
2342 deal, but if we win, great! */
2343
2344 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2345 #if 1 /* experiment */
2346 {
2347 int reg;
2348 /* We cycle through the registers to ensure they're all exercised. */
2349 static int next_fcc_reg = 0;
2350 /* Previous x,y for each fcc reg. */
2351 static rtx prev_args[4][2];
2352
2353 /* Scan prev_args for x,y. */
2354 for (reg = 0; reg < 4; reg++)
2355 if (prev_args[reg][0] == x && prev_args[reg][1] == y)
2356 break;
2357 if (reg == 4)
2358 {
2359 reg = next_fcc_reg;
2360 prev_args[reg][0] = x;
2361 prev_args[reg][1] = y;
2362 next_fcc_reg = (next_fcc_reg + 1) & 3;
2363 }
2364 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG);
2365 }
2366 #else
2367 cc_reg = gen_reg_rtx (mode);
2368 #endif /* ! experiment */
2369 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
2370 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG);
2371 else
2372 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG);
2373
2374 emit_insn (gen_rtx_SET (VOIDmode, cc_reg,
2375 gen_rtx_COMPARE (mode, x, y)));
2376
2377 return cc_reg;
2378 }
2379
2380 /* This function is used for v9 only.
2381 CODE is the code for an Scc's comparison.
2382 OPERANDS[0] is the target of the Scc insn.
2383 OPERANDS[1] is the value we compare against const0_rtx (which hasn't
2384 been generated yet).
2385
2386 This function is needed to turn
2387
2388 (set (reg:SI 110)
2389 (gt (reg:CCX 100 %icc)
2390 (const_int 0)))
2391 into
2392 (set (reg:SI 110)
2393 (gt:DI (reg:CCX 100 %icc)
2394 (const_int 0)))
2395
2396 IE: The instruction recognizer needs to see the mode of the comparison to
2397 find the right instruction. We could use "gt:DI" right in the
2398 define_expand, but leaving it out allows us to handle DI, SI, etc.
2399
2400 We refer to the global sparc compare operands sparc_compare_op0 and
2401 sparc_compare_op1. */
2402
2403 int
gen_v9_scc(enum rtx_code compare_code,register rtx * operands)2404 gen_v9_scc (enum rtx_code compare_code, register rtx *operands)
2405 {
2406 rtx temp, op0, op1;
2407
2408 if (! TARGET_ARCH64
2409 && (GET_MODE (sparc_compare_op0) == DImode
2410 || GET_MODE (operands[0]) == DImode))
2411 return 0;
2412
2413 op0 = sparc_compare_op0;
2414 op1 = sparc_compare_op1;
2415
2416 /* Try to use the movrCC insns. */
2417 if (TARGET_ARCH64
2418 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
2419 && op1 == const0_rtx
2420 && v9_regcmp_p (compare_code))
2421 {
2422 /* Special case for op0 != 0. This can be done with one instruction if
2423 operands[0] == sparc_compare_op0. */
2424
2425 if (compare_code == NE
2426 && GET_MODE (operands[0]) == DImode
2427 && rtx_equal_p (op0, operands[0]))
2428 {
2429 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2430 gen_rtx_IF_THEN_ELSE (DImode,
2431 gen_rtx_fmt_ee (compare_code, DImode,
2432 op0, const0_rtx),
2433 const1_rtx,
2434 operands[0])));
2435 return 1;
2436 }
2437
2438 if (reg_overlap_mentioned_p (operands[0], op0))
2439 {
2440 /* Handle the case where operands[0] == sparc_compare_op0.
2441 We "early clobber" the result. */
2442 op0 = gen_reg_rtx (GET_MODE (sparc_compare_op0));
2443 emit_move_insn (op0, sparc_compare_op0);
2444 }
2445
2446 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2447 if (GET_MODE (op0) != DImode)
2448 {
2449 temp = gen_reg_rtx (DImode);
2450 convert_move (temp, op0, 0);
2451 }
2452 else
2453 temp = op0;
2454 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2455 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2456 gen_rtx_fmt_ee (compare_code, DImode,
2457 temp, const0_rtx),
2458 const1_rtx,
2459 operands[0])));
2460 return 1;
2461 }
2462 else
2463 {
2464 operands[1] = gen_compare_reg (compare_code, op0, op1);
2465
2466 switch (GET_MODE (operands[1]))
2467 {
2468 case CCmode :
2469 case CCXmode :
2470 case CCFPEmode :
2471 case CCFPmode :
2472 break;
2473 default :
2474 abort ();
2475 }
2476 emit_insn (gen_rtx_SET (VOIDmode, operands[0], const0_rtx));
2477 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
2478 gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]),
2479 gen_rtx_fmt_ee (compare_code,
2480 GET_MODE (operands[1]),
2481 operands[1], const0_rtx),
2482 const1_rtx, operands[0])));
2483 return 1;
2484 }
2485 }
2486
2487 /* Emit a conditional jump insn for the v9 architecture using comparison code
2488 CODE and jump target LABEL.
2489 This function exists to take advantage of the v9 brxx insns. */
2490
2491 void
emit_v9_brxx_insn(enum rtx_code code,rtx op0,rtx label)2492 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label)
2493 {
2494 emit_jump_insn (gen_rtx_SET (VOIDmode,
2495 pc_rtx,
2496 gen_rtx_IF_THEN_ELSE (VOIDmode,
2497 gen_rtx_fmt_ee (code, GET_MODE (op0),
2498 op0, const0_rtx),
2499 gen_rtx_LABEL_REF (VOIDmode, label),
2500 pc_rtx)));
2501 }
2502
2503 /* Generate a DFmode part of a hard TFmode register.
2504 REG is the TFmode hard register, LOW is 1 for the
2505 low 64bit of the register and 0 otherwise.
2506 */
2507 rtx
gen_df_reg(rtx reg,int low)2508 gen_df_reg (rtx reg, int low)
2509 {
2510 int regno = REGNO (reg);
2511
2512 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0))
2513 regno += (TARGET_ARCH64 && regno < 32) ? 1 : 2;
2514 return gen_rtx_REG (DFmode, regno);
2515 }
2516
2517 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value.
2518 Unlike normal calls, TFmode operands are passed by reference. It is
2519 assumed that no more than 3 operands are required. */
2520
2521 static void
emit_soft_tfmode_libcall(const char * func_name,int nargs,rtx * operands)2522 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
2523 {
2524 rtx ret_slot = NULL, arg[3], func_sym;
2525 int i;
2526
2527 /* We only expect to be called for conversions, unary, and binary ops. */
2528 if (nargs < 2 || nargs > 3)
2529 abort ();
2530
2531 for (i = 0; i < nargs; ++i)
2532 {
2533 rtx this_arg = operands[i];
2534 rtx this_slot;
2535
2536 /* TFmode arguments and return values are passed by reference. */
2537 if (GET_MODE (this_arg) == TFmode)
2538 {
2539 int force_stack_temp;
2540
2541 force_stack_temp = 0;
2542 if (TARGET_BUGGY_QP_LIB && i == 0)
2543 force_stack_temp = 1;
2544
2545 if (GET_CODE (this_arg) == MEM
2546 && ! force_stack_temp)
2547 this_arg = XEXP (this_arg, 0);
2548 else if (CONSTANT_P (this_arg)
2549 && ! force_stack_temp)
2550 {
2551 this_slot = force_const_mem (TFmode, this_arg);
2552 this_arg = XEXP (this_slot, 0);
2553 }
2554 else
2555 {
2556 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode), 0);
2557
2558 /* Operand 0 is the return value. We'll copy it out later. */
2559 if (i > 0)
2560 emit_move_insn (this_slot, this_arg);
2561 else
2562 ret_slot = this_slot;
2563
2564 this_arg = XEXP (this_slot, 0);
2565 }
2566 }
2567
2568 arg[i] = this_arg;
2569 }
2570
2571 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name);
2572
2573 if (GET_MODE (operands[0]) == TFmode)
2574 {
2575 if (nargs == 2)
2576 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2,
2577 arg[0], GET_MODE (arg[0]),
2578 arg[1], GET_MODE (arg[1]));
2579 else
2580 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3,
2581 arg[0], GET_MODE (arg[0]),
2582 arg[1], GET_MODE (arg[1]),
2583 arg[2], GET_MODE (arg[2]));
2584
2585 if (ret_slot)
2586 emit_move_insn (operands[0], ret_slot);
2587 }
2588 else
2589 {
2590 rtx ret;
2591
2592 if (nargs != 2)
2593 abort ();
2594
2595 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL,
2596 GET_MODE (operands[0]), 1,
2597 arg[1], GET_MODE (arg[1]));
2598
2599 if (ret != operands[0])
2600 emit_move_insn (operands[0], ret);
2601 }
2602 }
2603
2604 /* Expand soft-float TFmode calls to sparc abi routines. */
2605
2606 static void
emit_soft_tfmode_binop(enum rtx_code code,rtx * operands)2607 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands)
2608 {
2609 const char *func;
2610
2611 switch (code)
2612 {
2613 case PLUS:
2614 func = "_Qp_add";
2615 break;
2616 case MINUS:
2617 func = "_Qp_sub";
2618 break;
2619 case MULT:
2620 func = "_Qp_mul";
2621 break;
2622 case DIV:
2623 func = "_Qp_div";
2624 break;
2625 default:
2626 abort ();
2627 }
2628
2629 emit_soft_tfmode_libcall (func, 3, operands);
2630 }
2631
2632 static void
emit_soft_tfmode_unop(enum rtx_code code,rtx * operands)2633 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands)
2634 {
2635 const char *func;
2636
2637 switch (code)
2638 {
2639 case SQRT:
2640 func = "_Qp_sqrt";
2641 break;
2642 default:
2643 abort ();
2644 }
2645
2646 emit_soft_tfmode_libcall (func, 2, operands);
2647 }
2648
2649 static void
emit_soft_tfmode_cvt(enum rtx_code code,rtx * operands)2650 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands)
2651 {
2652 const char *func;
2653
2654 switch (code)
2655 {
2656 case FLOAT_EXTEND:
2657 switch (GET_MODE (operands[1]))
2658 {
2659 case SFmode:
2660 func = "_Qp_stoq";
2661 break;
2662 case DFmode:
2663 func = "_Qp_dtoq";
2664 break;
2665 default:
2666 abort ();
2667 }
2668 break;
2669
2670 case FLOAT_TRUNCATE:
2671 switch (GET_MODE (operands[0]))
2672 {
2673 case SFmode:
2674 func = "_Qp_qtos";
2675 break;
2676 case DFmode:
2677 func = "_Qp_qtod";
2678 break;
2679 default:
2680 abort ();
2681 }
2682 break;
2683
2684 case FLOAT:
2685 switch (GET_MODE (operands[1]))
2686 {
2687 case SImode:
2688 func = "_Qp_itoq";
2689 break;
2690 case DImode:
2691 func = "_Qp_xtoq";
2692 break;
2693 default:
2694 abort ();
2695 }
2696 break;
2697
2698 case UNSIGNED_FLOAT:
2699 switch (GET_MODE (operands[1]))
2700 {
2701 case SImode:
2702 func = "_Qp_uitoq";
2703 break;
2704 case DImode:
2705 func = "_Qp_uxtoq";
2706 break;
2707 default:
2708 abort ();
2709 }
2710 break;
2711
2712 case FIX:
2713 switch (GET_MODE (operands[0]))
2714 {
2715 case SImode:
2716 func = "_Qp_qtoi";
2717 break;
2718 case DImode:
2719 func = "_Qp_qtox";
2720 break;
2721 default:
2722 abort ();
2723 }
2724 break;
2725
2726 case UNSIGNED_FIX:
2727 switch (GET_MODE (operands[0]))
2728 {
2729 case SImode:
2730 func = "_Qp_qtoui";
2731 break;
2732 case DImode:
2733 func = "_Qp_qtoux";
2734 break;
2735 default:
2736 abort ();
2737 }
2738 break;
2739
2740 default:
2741 abort ();
2742 }
2743
2744 emit_soft_tfmode_libcall (func, 2, operands);
2745 }
2746
2747 /* Expand a hard-float tfmode operation. All arguments must be in
2748 registers. */
2749
2750 static void
emit_hard_tfmode_operation(enum rtx_code code,rtx * operands)2751 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands)
2752 {
2753 rtx op, dest;
2754
2755 if (GET_RTX_CLASS (code) == '1')
2756 {
2757 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2758 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]);
2759 }
2760 else
2761 {
2762 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]);
2763 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]);
2764 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]),
2765 operands[1], operands[2]);
2766 }
2767
2768 if (register_operand (operands[0], VOIDmode))
2769 dest = operands[0];
2770 else
2771 dest = gen_reg_rtx (GET_MODE (operands[0]));
2772
2773 emit_insn (gen_rtx_SET (VOIDmode, dest, op));
2774
2775 if (dest != operands[0])
2776 emit_move_insn (operands[0], dest);
2777 }
2778
2779 void
emit_tfmode_binop(enum rtx_code code,rtx * operands)2780 emit_tfmode_binop (enum rtx_code code, rtx *operands)
2781 {
2782 if (TARGET_HARD_QUAD)
2783 emit_hard_tfmode_operation (code, operands);
2784 else
2785 emit_soft_tfmode_binop (code, operands);
2786 }
2787
2788 void
emit_tfmode_unop(enum rtx_code code,rtx * operands)2789 emit_tfmode_unop (enum rtx_code code, rtx *operands)
2790 {
2791 if (TARGET_HARD_QUAD)
2792 emit_hard_tfmode_operation (code, operands);
2793 else
2794 emit_soft_tfmode_unop (code, operands);
2795 }
2796
2797 void
emit_tfmode_cvt(enum rtx_code code,rtx * operands)2798 emit_tfmode_cvt (enum rtx_code code, rtx *operands)
2799 {
2800 if (TARGET_HARD_QUAD)
2801 emit_hard_tfmode_operation (code, operands);
2802 else
2803 emit_soft_tfmode_cvt (code, operands);
2804 }
2805
2806 /* Return nonzero if a return peephole merging return with
2807 setting of output register is ok. */
2808 int
leaf_return_peephole_ok(void)2809 leaf_return_peephole_ok (void)
2810 {
2811 return (actual_fsize == 0);
2812 }
2813
2814 /* Return nonzero if a branch/jump/call instruction will be emitting
2815 nop into its delay slot. */
2816
2817 int
empty_delay_slot(rtx insn)2818 empty_delay_slot (rtx insn)
2819 {
2820 rtx seq;
2821
2822 /* If no previous instruction (should not happen), return true. */
2823 if (PREV_INSN (insn) == NULL)
2824 return 1;
2825
2826 seq = NEXT_INSN (PREV_INSN (insn));
2827 if (GET_CODE (PATTERN (seq)) == SEQUENCE)
2828 return 0;
2829
2830 return 1;
2831 }
2832
2833 /* Return nonzero if TRIAL can go into the function epilogue's
2834 delay slot. SLOT is the slot we are trying to fill. */
2835
2836 int
eligible_for_epilogue_delay(rtx trial,int slot)2837 eligible_for_epilogue_delay (rtx trial, int slot)
2838 {
2839 rtx pat, src;
2840
2841 if (slot >= 1)
2842 return 0;
2843
2844 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2845 return 0;
2846
2847 if (get_attr_length (trial) != 1)
2848 return 0;
2849
2850 /* If there are any call-saved registers, we should scan TRIAL if it
2851 does not reference them. For now just make it easy. */
2852 if (num_gfregs)
2853 return 0;
2854
2855 /* If the function uses __builtin_eh_return, the eh_return machinery
2856 occupies the delay slot. */
2857 if (current_function_calls_eh_return)
2858 return 0;
2859
2860 /* In the case of a true leaf function, anything can go into the delay slot.
2861 A delay slot only exists however if the frame size is zero, otherwise
2862 we will put an insn to adjust the stack after the return. */
2863 if (current_function_uses_only_leaf_regs)
2864 {
2865 if (leaf_return_peephole_ok ())
2866 return ((get_attr_in_uncond_branch_delay (trial)
2867 == IN_BRANCH_DELAY_TRUE));
2868 return 0;
2869 }
2870
2871 pat = PATTERN (trial);
2872
2873 /* Otherwise, only operations which can be done in tandem with
2874 a `restore' or `return' insn can go into the delay slot. */
2875 if (GET_CODE (SET_DEST (pat)) != REG
2876 || REGNO (SET_DEST (pat)) < 24)
2877 return 0;
2878
2879 /* If this instruction sets up floating point register and we have a return
2880 instruction, it can probably go in. But restore will not work
2881 with FP_REGS. */
2882 if (REGNO (SET_DEST (pat)) >= 32)
2883 {
2884 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2885 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2886 return 1;
2887 return 0;
2888 }
2889
2890 /* The set of insns matched here must agree precisely with the set of
2891 patterns paired with a RETURN in sparc.md. */
2892
2893 src = SET_SRC (pat);
2894
2895 /* This matches "*return_[qhs]i" or even "*return_di" on TARGET_ARCH64. */
2896 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2897 && arith_operand (src, GET_MODE (src)))
2898 {
2899 if (TARGET_ARCH64)
2900 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2901 else
2902 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
2903 }
2904
2905 /* This matches "*return_di". */
2906 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
2907 && arith_double_operand (src, GET_MODE (src)))
2908 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
2909
2910 /* This matches "*return_sf_no_fpu". */
2911 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
2912 && register_operand (src, SFmode))
2913 return 1;
2914
2915 /* If we have return instruction, anything that does not use
2916 local or output registers and can go into a delay slot wins. */
2917 else if (TARGET_V9 && ! epilogue_renumber (&pat, 1)
2918 && (get_attr_in_uncond_branch_delay (trial) == IN_BRANCH_DELAY_TRUE))
2919 return 1;
2920
2921 /* This matches "*return_addsi". */
2922 else if (GET_CODE (src) == PLUS
2923 && arith_operand (XEXP (src, 0), SImode)
2924 && arith_operand (XEXP (src, 1), SImode)
2925 && (register_operand (XEXP (src, 0), SImode)
2926 || register_operand (XEXP (src, 1), SImode)))
2927 return 1;
2928
2929 /* This matches "*return_adddi". */
2930 else if (GET_CODE (src) == PLUS
2931 && arith_double_operand (XEXP (src, 0), DImode)
2932 && arith_double_operand (XEXP (src, 1), DImode)
2933 && (register_operand (XEXP (src, 0), DImode)
2934 || register_operand (XEXP (src, 1), DImode)))
2935 return 1;
2936
2937 /* This can match "*return_losum_[sd]i".
2938 Catch only some cases, so that return_losum* don't have
2939 to be too big. */
2940 else if (GET_CODE (src) == LO_SUM
2941 && ! TARGET_CM_MEDMID
2942 && ((register_operand (XEXP (src, 0), SImode)
2943 && immediate_operand (XEXP (src, 1), SImode))
2944 || (TARGET_ARCH64
2945 && register_operand (XEXP (src, 0), DImode)
2946 && immediate_operand (XEXP (src, 1), DImode))))
2947 return 1;
2948
2949 /* sll{,x} reg,1,reg2 is add reg,reg,reg2 as well. */
2950 else if (GET_CODE (src) == ASHIFT
2951 && (register_operand (XEXP (src, 0), SImode)
2952 || register_operand (XEXP (src, 0), DImode))
2953 && XEXP (src, 1) == const1_rtx)
2954 return 1;
2955
2956 return 0;
2957 }
2958
2959 /* Return nonzero if TRIAL can go into the call delay slot. */
2960 int
tls_call_delay(rtx trial)2961 tls_call_delay (rtx trial)
2962 {
2963 rtx pat, unspec;
2964
2965 /* Binutils allows
2966 call __tls_get_addr, %tgd_call (foo)
2967 add %l7, %o0, %o0, %tgd_add (foo)
2968 while Sun as/ld does not. */
2969 if (TARGET_GNU_TLS || !TARGET_TLS)
2970 return 1;
2971
2972 pat = PATTERN (trial);
2973 if (GET_CODE (pat) != SET || GET_CODE (SET_DEST (pat)) != PLUS)
2974 return 1;
2975
2976 unspec = XEXP (SET_DEST (pat), 1);
2977 if (GET_CODE (unspec) != UNSPEC
2978 || (XINT (unspec, 1) != UNSPEC_TLSGD
2979 && XINT (unspec, 1) != UNSPEC_TLSLDM))
2980 return 1;
2981
2982 return 0;
2983 }
2984
2985 /* Return nonzero if TRIAL can go into the sibling call
2986 delay slot. */
2987
2988 int
eligible_for_sibcall_delay(rtx trial)2989 eligible_for_sibcall_delay (rtx trial)
2990 {
2991 rtx pat, src;
2992
2993 if (GET_CODE (trial) != INSN || GET_CODE (PATTERN (trial)) != SET)
2994 return 0;
2995
2996 if (get_attr_length (trial) != 1)
2997 return 0;
2998
2999 pat = PATTERN (trial);
3000
3001 if (current_function_uses_only_leaf_regs)
3002 {
3003 /* If the tail call is done using the call instruction,
3004 we have to restore %o7 in the delay slot. */
3005 if ((TARGET_ARCH64 && ! TARGET_CM_MEDLOW) || flag_pic)
3006 return 0;
3007
3008 /* %g1 is used to build the function address */
3009 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat))
3010 return 0;
3011
3012 return 1;
3013 }
3014
3015 /* Otherwise, only operations which can be done in tandem with
3016 a `restore' insn can go into the delay slot. */
3017 if (GET_CODE (SET_DEST (pat)) != REG
3018 || REGNO (SET_DEST (pat)) < 24
3019 || REGNO (SET_DEST (pat)) >= 32)
3020 return 0;
3021
3022 /* If it mentions %o7, it can't go in, because sibcall will clobber it
3023 in most cases. */
3024 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat))
3025 return 0;
3026
3027 src = SET_SRC (pat);
3028
3029 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3030 && arith_operand (src, GET_MODE (src)))
3031 {
3032 if (TARGET_ARCH64)
3033 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3034 else
3035 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode);
3036 }
3037
3038 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT
3039 && arith_double_operand (src, GET_MODE (src)))
3040 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode);
3041
3042 else if (! TARGET_FPU && restore_operand (SET_DEST (pat), SFmode)
3043 && register_operand (src, SFmode))
3044 return 1;
3045
3046 else if (GET_CODE (src) == PLUS
3047 && arith_operand (XEXP (src, 0), SImode)
3048 && arith_operand (XEXP (src, 1), SImode)
3049 && (register_operand (XEXP (src, 0), SImode)
3050 || register_operand (XEXP (src, 1), SImode)))
3051 return 1;
3052
3053 else if (GET_CODE (src) == PLUS
3054 && arith_double_operand (XEXP (src, 0), DImode)
3055 && arith_double_operand (XEXP (src, 1), DImode)
3056 && (register_operand (XEXP (src, 0), DImode)
3057 || register_operand (XEXP (src, 1), DImode)))
3058 return 1;
3059
3060 else if (GET_CODE (src) == LO_SUM
3061 && ! TARGET_CM_MEDMID
3062 && ((register_operand (XEXP (src, 0), SImode)
3063 && immediate_operand (XEXP (src, 1), SImode))
3064 || (TARGET_ARCH64
3065 && register_operand (XEXP (src, 0), DImode)
3066 && immediate_operand (XEXP (src, 1), DImode))))
3067 return 1;
3068
3069 else if (GET_CODE (src) == ASHIFT
3070 && (register_operand (XEXP (src, 0), SImode)
3071 || register_operand (XEXP (src, 0), DImode))
3072 && XEXP (src, 1) == const1_rtx)
3073 return 1;
3074
3075 return 0;
3076 }
3077
3078 static int
check_return_regs(rtx x)3079 check_return_regs (rtx x)
3080 {
3081 switch (GET_CODE (x))
3082 {
3083 case REG:
3084 return IN_OR_GLOBAL_P (x);
3085
3086 case CONST_INT:
3087 case CONST_DOUBLE:
3088 case CONST:
3089 case SYMBOL_REF:
3090 case LABEL_REF:
3091 return 1;
3092
3093 case SET:
3094 case IOR:
3095 case AND:
3096 case XOR:
3097 case PLUS:
3098 case MINUS:
3099 if (check_return_regs (XEXP (x, 1)) == 0)
3100 return 0;
3101 case NOT:
3102 case NEG:
3103 case MEM:
3104 return check_return_regs (XEXP (x, 0));
3105
3106 default:
3107 return 0;
3108 }
3109
3110 }
3111
3112 int
short_branch(int uid1,int uid2)3113 short_branch (int uid1, int uid2)
3114 {
3115 int delta = INSN_ADDRESSES (uid1) - INSN_ADDRESSES (uid2);
3116
3117 /* Leave a few words of "slop". */
3118 if (delta >= -1023 && delta <= 1022)
3119 return 1;
3120
3121 return 0;
3122 }
3123
3124 /* Return nonzero if REG is not used after INSN.
3125 We assume REG is a reload reg, and therefore does
3126 not live past labels or calls or jumps. */
3127 int
reg_unused_after(rtx reg,rtx insn)3128 reg_unused_after (rtx reg, rtx insn)
3129 {
3130 enum rtx_code code, prev_code = UNKNOWN;
3131
3132 while ((insn = NEXT_INSN (insn)))
3133 {
3134 if (prev_code == CALL_INSN && call_used_regs[REGNO (reg)])
3135 return 1;
3136
3137 code = GET_CODE (insn);
3138 if (GET_CODE (insn) == CODE_LABEL)
3139 return 1;
3140
3141 if (GET_RTX_CLASS (code) == 'i')
3142 {
3143 rtx set = single_set (insn);
3144 int in_src = set && reg_overlap_mentioned_p (reg, SET_SRC (set));
3145 if (set && in_src)
3146 return 0;
3147 if (set && reg_overlap_mentioned_p (reg, SET_DEST (set)))
3148 return 1;
3149 if (set == 0 && reg_overlap_mentioned_p (reg, PATTERN (insn)))
3150 return 0;
3151 }
3152 prev_code = code;
3153 }
3154 return 1;
3155 }
3156
3157 /* Determine if it's legal to put X into the constant pool. This
3158 is not possible if X contains the address of a symbol that is
3159 not constant (TLS) or not known at final link time (PIC). */
3160
3161 static bool
sparc_cannot_force_const_mem(rtx x)3162 sparc_cannot_force_const_mem (rtx x)
3163 {
3164 switch (GET_CODE (x))
3165 {
3166 case CONST_INT:
3167 case CONST_DOUBLE:
3168 /* Accept all non-symbolic constants. */
3169 return false;
3170
3171 case LABEL_REF:
3172 /* Labels are OK iff we are non-PIC. */
3173 return flag_pic != 0;
3174
3175 case SYMBOL_REF:
3176 /* 'Naked' TLS symbol references are never OK,
3177 non-TLS symbols are OK iff we are non-PIC. */
3178 if (SYMBOL_REF_TLS_MODEL (x))
3179 return true;
3180 else
3181 return flag_pic != 0;
3182
3183 case CONST:
3184 return sparc_cannot_force_const_mem (XEXP (x, 0));
3185 case PLUS:
3186 case MINUS:
3187 return sparc_cannot_force_const_mem (XEXP (x, 0))
3188 || sparc_cannot_force_const_mem (XEXP (x, 1));
3189 case UNSPEC:
3190 return true;
3191 default:
3192 abort ();
3193 }
3194 }
3195
3196 /* The table we use to reference PIC data. */
3197 static GTY(()) rtx global_offset_table;
3198
3199 /* The function we use to get at it. */
3200 static GTY(()) rtx get_pc_symbol;
3201 static GTY(()) char get_pc_symbol_name[256];
3202
3203 /* Ensure that we are not using patterns that are not OK with PIC. */
3204
3205 int
check_pic(int i)3206 check_pic (int i)
3207 {
3208 switch (flag_pic)
3209 {
3210 case 1:
3211 if (GET_CODE (recog_data.operand[i]) == SYMBOL_REF
3212 || (GET_CODE (recog_data.operand[i]) == CONST
3213 && ! (GET_CODE (XEXP (recog_data.operand[i], 0)) == MINUS
3214 && (XEXP (XEXP (recog_data.operand[i], 0), 0)
3215 == global_offset_table)
3216 && (GET_CODE (XEXP (XEXP (recog_data.operand[i], 0), 1))
3217 == CONST))))
3218 abort ();
3219 case 2:
3220 default:
3221 return 1;
3222 }
3223 }
3224
3225 /* Return true if X is an address which needs a temporary register when
3226 reloaded while generating PIC code. */
3227
3228 int
pic_address_needs_scratch(rtx x)3229 pic_address_needs_scratch (rtx x)
3230 {
3231 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
3232 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
3233 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
3234 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3235 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
3236 return 1;
3237
3238 return 0;
3239 }
3240
3241 /* Determine if a given RTX is a valid constant. We already know this
3242 satisfies CONSTANT_P. */
3243
3244 bool
legitimate_constant_p(rtx x)3245 legitimate_constant_p (rtx x)
3246 {
3247 rtx inner;
3248
3249 switch (GET_CODE (x))
3250 {
3251 case SYMBOL_REF:
3252 /* TLS symbols are not constant. */
3253 if (SYMBOL_REF_TLS_MODEL (x))
3254 return false;
3255 break;
3256
3257 case CONST:
3258 inner = XEXP (x, 0);
3259
3260 /* Offsets of TLS symbols are never valid.
3261 Discourage CSE from creating them. */
3262 if (GET_CODE (inner) == PLUS
3263 && tls_symbolic_operand (XEXP (inner, 0)))
3264 return false;
3265 break;
3266
3267 case CONST_DOUBLE:
3268 if (GET_MODE (x) == VOIDmode)
3269 return true;
3270
3271 /* Floating point constants are generally not ok.
3272 The only exception is 0.0 in VIS. */
3273 if (TARGET_VIS
3274 && (GET_MODE (x) == SFmode
3275 || GET_MODE (x) == DFmode
3276 || GET_MODE (x) == TFmode)
3277 && fp_zero_operand (x, GET_MODE (x)))
3278 return true;
3279
3280 return false;
3281
3282 default:
3283 break;
3284 }
3285
3286 return true;
3287 }
3288
3289 /* Determine if a given RTX is a valid constant address. */
3290
3291 bool
constant_address_p(rtx x)3292 constant_address_p (rtx x)
3293 {
3294 switch (GET_CODE (x))
3295 {
3296 case LABEL_REF:
3297 case CONST_INT:
3298 case HIGH:
3299 return true;
3300
3301 case CONST:
3302 if (flag_pic && pic_address_needs_scratch (x))
3303 return false;
3304 return legitimate_constant_p (x);
3305
3306 case SYMBOL_REF:
3307 return !flag_pic && legitimate_constant_p (x);
3308
3309 default:
3310 return false;
3311 }
3312 }
3313
3314 /* Nonzero if the constant value X is a legitimate general operand
3315 when generating PIC code. It is given that flag_pic is on and
3316 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
3317
3318 bool
legitimate_pic_operand_p(rtx x)3319 legitimate_pic_operand_p (rtx x)
3320 {
3321 if (pic_address_needs_scratch (x))
3322 return false;
3323 if (tls_symbolic_operand (x)
3324 || (GET_CODE (x) == CONST
3325 && GET_CODE (XEXP (x, 0)) == PLUS
3326 && tls_symbolic_operand (XEXP (XEXP (x, 0), 0))))
3327 return false;
3328 return true;
3329 }
3330
3331 /* Return nonzero if ADDR is a valid memory address.
3332 STRICT specifies whether strict register checking applies. */
3333
3334 int
legitimate_address_p(enum machine_mode mode,rtx addr,int strict)3335 legitimate_address_p (enum machine_mode mode, rtx addr, int strict)
3336 {
3337 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL, imm2;
3338
3339 if (REG_P (addr) || GET_CODE (addr) == SUBREG)
3340 rs1 = addr;
3341 else if (GET_CODE (addr) == PLUS)
3342 {
3343 rs1 = XEXP (addr, 0);
3344 rs2 = XEXP (addr, 1);
3345
3346 /* Canonicalize. REG comes first, if there are no regs,
3347 LO_SUM comes first. */
3348 if (!REG_P (rs1)
3349 && GET_CODE (rs1) != SUBREG
3350 && (REG_P (rs2)
3351 || GET_CODE (rs2) == SUBREG
3352 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
3353 {
3354 rs1 = XEXP (addr, 1);
3355 rs2 = XEXP (addr, 0);
3356 }
3357
3358 if ((flag_pic == 1
3359 && rs1 == pic_offset_table_rtx
3360 && !REG_P (rs2)
3361 && GET_CODE (rs2) != SUBREG
3362 && GET_CODE (rs2) != LO_SUM
3363 && GET_CODE (rs2) != MEM
3364 && !tls_symbolic_operand (rs2)
3365 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
3366 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
3367 || ((REG_P (rs1)
3368 || GET_CODE (rs1) == SUBREG)
3369 && RTX_OK_FOR_OFFSET_P (rs2)))
3370 {
3371 imm1 = rs2;
3372 rs2 = NULL;
3373 }
3374 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
3375 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
3376 {
3377 /* We prohibit REG + REG for TFmode when there are no instructions
3378 which accept REG+REG instructions. We do this because REG+REG
3379 is not an offsetable address. If we get the situation in reload
3380 where source and destination of a movtf pattern are both MEMs with
3381 REG+REG address, then only one of them gets converted to an
3382 offsetable address. */
3383 if (mode == TFmode
3384 && !(TARGET_FPU && TARGET_ARCH64 && TARGET_V9
3385 && TARGET_HARD_QUAD))
3386 return 0;
3387
3388 /* We prohibit REG + REG on ARCH32 if not optimizing for
3389 DFmode/DImode because then mem_min_alignment is likely to be zero
3390 after reload and the forced split would lack a matching splitter
3391 pattern. */
3392 if (TARGET_ARCH32 && !optimize
3393 && (mode == DFmode || mode == DImode))
3394 return 0;
3395 }
3396 else if (USE_AS_OFFSETABLE_LO10
3397 && GET_CODE (rs1) == LO_SUM
3398 && TARGET_ARCH64
3399 && ! TARGET_CM_MEDMID
3400 && RTX_OK_FOR_OLO10_P (rs2))
3401 {
3402 imm2 = rs2;
3403 rs2 = NULL;
3404 imm1 = XEXP (rs1, 1);
3405 rs1 = XEXP (rs1, 0);
3406 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3407 return 0;
3408 }
3409 }
3410 else if (GET_CODE (addr) == LO_SUM)
3411 {
3412 rs1 = XEXP (addr, 0);
3413 imm1 = XEXP (addr, 1);
3414
3415 if (! CONSTANT_P (imm1) || tls_symbolic_operand (rs1))
3416 return 0;
3417
3418 /* We can't allow TFmode, because an offset greater than or equal to the
3419 alignment (8) may cause the LO_SUM to overflow if !v9. */
3420 if (mode == TFmode && !TARGET_V9)
3421 return 0;
3422 }
3423 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
3424 return 1;
3425 else
3426 return 0;
3427
3428 if (GET_CODE (rs1) == SUBREG)
3429 rs1 = SUBREG_REG (rs1);
3430 if (!REG_P (rs1))
3431 return 0;
3432
3433 if (rs2)
3434 {
3435 if (GET_CODE (rs2) == SUBREG)
3436 rs2 = SUBREG_REG (rs2);
3437 if (!REG_P (rs2))
3438 return 0;
3439 }
3440
3441 if (strict)
3442 {
3443 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1))
3444 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2))))
3445 return 0;
3446 }
3447 else
3448 {
3449 if ((REGNO (rs1) >= 32
3450 && REGNO (rs1) != FRAME_POINTER_REGNUM
3451 && REGNO (rs1) < FIRST_PSEUDO_REGISTER)
3452 || (rs2
3453 && (REGNO (rs2) >= 32
3454 && REGNO (rs2) != FRAME_POINTER_REGNUM
3455 && REGNO (rs2) < FIRST_PSEUDO_REGISTER)))
3456 return 0;
3457 }
3458 return 1;
3459 }
3460
3461 /* Construct the SYMBOL_REF for the tls_get_offset function. */
3462
3463 static GTY(()) rtx sparc_tls_symbol;
3464 static rtx
sparc_tls_get_addr(void)3465 sparc_tls_get_addr (void)
3466 {
3467 if (!sparc_tls_symbol)
3468 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr");
3469
3470 return sparc_tls_symbol;
3471 }
3472
3473 static rtx
sparc_tls_got(void)3474 sparc_tls_got (void)
3475 {
3476 rtx temp;
3477 if (flag_pic)
3478 {
3479 current_function_uses_pic_offset_table = 1;
3480 return pic_offset_table_rtx;
3481 }
3482
3483 if (!global_offset_table)
3484 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3485 temp = gen_reg_rtx (Pmode);
3486 emit_move_insn (temp, global_offset_table);
3487 return temp;
3488 }
3489
3490
3491 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3492 this (thread-local) address. */
3493
3494 rtx
legitimize_tls_address(rtx addr)3495 legitimize_tls_address (rtx addr)
3496 {
3497 rtx temp1, temp2, temp3, ret, o0, got, insn;
3498
3499 if (no_new_pseudos)
3500 abort ();
3501
3502 if (GET_CODE (addr) == SYMBOL_REF)
3503 switch (SYMBOL_REF_TLS_MODEL (addr))
3504 {
3505 case TLS_MODEL_GLOBAL_DYNAMIC:
3506 start_sequence ();
3507 temp1 = gen_reg_rtx (SImode);
3508 temp2 = gen_reg_rtx (SImode);
3509 ret = gen_reg_rtx (Pmode);
3510 o0 = gen_rtx_REG (Pmode, 8);
3511 got = sparc_tls_got ();
3512 emit_insn (gen_tgd_hi22 (temp1, addr));
3513 emit_insn (gen_tgd_lo10 (temp2, temp1, addr));
3514 if (TARGET_ARCH32)
3515 {
3516 emit_insn (gen_tgd_add32 (o0, got, temp2, addr));
3517 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (),
3518 addr, const1_rtx));
3519 }
3520 else
3521 {
3522 emit_insn (gen_tgd_add64 (o0, got, temp2, addr));
3523 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (),
3524 addr, const1_rtx));
3525 }
3526 CALL_INSN_FUNCTION_USAGE (insn)
3527 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3528 CALL_INSN_FUNCTION_USAGE (insn));
3529 insn = get_insns ();
3530 end_sequence ();
3531 emit_libcall_block (insn, ret, o0, addr);
3532 break;
3533
3534 case TLS_MODEL_LOCAL_DYNAMIC:
3535 start_sequence ();
3536 temp1 = gen_reg_rtx (SImode);
3537 temp2 = gen_reg_rtx (SImode);
3538 temp3 = gen_reg_rtx (Pmode);
3539 ret = gen_reg_rtx (Pmode);
3540 o0 = gen_rtx_REG (Pmode, 8);
3541 got = sparc_tls_got ();
3542 emit_insn (gen_tldm_hi22 (temp1));
3543 emit_insn (gen_tldm_lo10 (temp2, temp1));
3544 if (TARGET_ARCH32)
3545 {
3546 emit_insn (gen_tldm_add32 (o0, got, temp2));
3547 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (),
3548 const1_rtx));
3549 }
3550 else
3551 {
3552 emit_insn (gen_tldm_add64 (o0, got, temp2));
3553 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (),
3554 const1_rtx));
3555 }
3556 CALL_INSN_FUNCTION_USAGE (insn)
3557 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_USE (VOIDmode, o0),
3558 CALL_INSN_FUNCTION_USAGE (insn));
3559 insn = get_insns ();
3560 end_sequence ();
3561 emit_libcall_block (insn, temp3, o0,
3562 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3563 UNSPEC_TLSLD_BASE));
3564 temp1 = gen_reg_rtx (SImode);
3565 temp2 = gen_reg_rtx (SImode);
3566 emit_insn (gen_tldo_hix22 (temp1, addr));
3567 emit_insn (gen_tldo_lox10 (temp2, temp1, addr));
3568 if (TARGET_ARCH32)
3569 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr));
3570 else
3571 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr));
3572 break;
3573
3574 case TLS_MODEL_INITIAL_EXEC:
3575 temp1 = gen_reg_rtx (SImode);
3576 temp2 = gen_reg_rtx (SImode);
3577 temp3 = gen_reg_rtx (Pmode);
3578 got = sparc_tls_got ();
3579 emit_insn (gen_tie_hi22 (temp1, addr));
3580 emit_insn (gen_tie_lo10 (temp2, temp1, addr));
3581 if (TARGET_ARCH32)
3582 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr));
3583 else
3584 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr));
3585 if (TARGET_SUN_TLS)
3586 {
3587 ret = gen_reg_rtx (Pmode);
3588 if (TARGET_ARCH32)
3589 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7),
3590 temp3, addr));
3591 else
3592 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7),
3593 temp3, addr));
3594 }
3595 else
3596 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3);
3597 break;
3598
3599 case TLS_MODEL_LOCAL_EXEC:
3600 temp1 = gen_reg_rtx (Pmode);
3601 temp2 = gen_reg_rtx (Pmode);
3602 if (TARGET_ARCH32)
3603 {
3604 emit_insn (gen_tle_hix22_sp32 (temp1, addr));
3605 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr));
3606 }
3607 else
3608 {
3609 emit_insn (gen_tle_hix22_sp64 (temp1, addr));
3610 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr));
3611 }
3612 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2);
3613 break;
3614
3615 default:
3616 abort ();
3617 }
3618
3619 else
3620 abort (); /* for now ... */
3621
3622 return ret;
3623 }
3624
3625
3626 /* Legitimize PIC addresses. If the address is already position-independent,
3627 we return ORIG. Newly generated position-independent addresses go into a
3628 reg. This is REG if nonzero, otherwise we allocate register(s) as
3629 necessary. */
3630
3631 rtx
legitimize_pic_address(rtx orig,enum machine_mode mode ATTRIBUTE_UNUSED,rtx reg)3632 legitimize_pic_address (rtx orig, enum machine_mode mode ATTRIBUTE_UNUSED,
3633 rtx reg)
3634 {
3635 if (GET_CODE (orig) == SYMBOL_REF)
3636 {
3637 rtx pic_ref, address;
3638 rtx insn;
3639
3640 if (reg == 0)
3641 {
3642 if (reload_in_progress || reload_completed)
3643 abort ();
3644 else
3645 reg = gen_reg_rtx (Pmode);
3646 }
3647
3648 if (flag_pic == 2)
3649 {
3650 /* If not during reload, allocate another temp reg here for loading
3651 in the address, so that these instructions can be optimized
3652 properly. */
3653 rtx temp_reg = ((reload_in_progress || reload_completed)
3654 ? reg : gen_reg_rtx (Pmode));
3655
3656 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse
3657 won't get confused into thinking that these two instructions
3658 are loading in the true address of the symbol. If in the
3659 future a PIC rtx exists, that should be used instead. */
3660 if (Pmode == SImode)
3661 {
3662 emit_insn (gen_movsi_high_pic (temp_reg, orig));
3663 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig));
3664 }
3665 else
3666 {
3667 emit_insn (gen_movdi_high_pic (temp_reg, orig));
3668 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig));
3669 }
3670 address = temp_reg;
3671 }
3672 else
3673 address = orig;
3674
3675 pic_ref = gen_rtx_MEM (Pmode,
3676 gen_rtx_PLUS (Pmode,
3677 pic_offset_table_rtx, address));
3678 current_function_uses_pic_offset_table = 1;
3679 RTX_UNCHANGING_P (pic_ref) = 1;
3680 insn = emit_move_insn (reg, pic_ref);
3681 /* Put a REG_EQUAL note on this insn, so that it can be optimized
3682 by loop. */
3683 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig,
3684 REG_NOTES (insn));
3685 return reg;
3686 }
3687 else if (GET_CODE (orig) == CONST)
3688 {
3689 rtx base, offset;
3690
3691 if (GET_CODE (XEXP (orig, 0)) == PLUS
3692 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
3693 return orig;
3694
3695 if (reg == 0)
3696 {
3697 if (reload_in_progress || reload_completed)
3698 abort ();
3699 else
3700 reg = gen_reg_rtx (Pmode);
3701 }
3702
3703 if (GET_CODE (XEXP (orig, 0)) == PLUS)
3704 {
3705 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
3706 offset = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
3707 base == reg ? 0 : reg);
3708 }
3709 else
3710 abort ();
3711
3712 if (GET_CODE (offset) == CONST_INT)
3713 {
3714 if (SMALL_INT (offset))
3715 return plus_constant (base, INTVAL (offset));
3716 else if (! reload_in_progress && ! reload_completed)
3717 offset = force_reg (Pmode, offset);
3718 else
3719 /* If we reach here, then something is seriously wrong. */
3720 abort ();
3721 }
3722 return gen_rtx_PLUS (Pmode, base, offset);
3723 }
3724 else if (GET_CODE (orig) == LABEL_REF)
3725 /* ??? Why do we do this? */
3726 /* Now movsi_pic_label_ref uses it, but we ought to be checking that
3727 the register is live instead, in case it is eliminated. */
3728 current_function_uses_pic_offset_table = 1;
3729
3730 return orig;
3731 }
3732
3733 /* Try machine-dependent ways of modifying an illegitimate address X
3734 to be legitimate. If we find one, return the new, valid address.
3735
3736 OLDX is the address as it was before break_out_memory_refs was called.
3737 In some cases it is useful to look at this to decide what needs to be done.
3738
3739 MODE is the mode of the operand pointed to by X. */
3740
3741 rtx
legitimize_address(rtx x,rtx oldx ATTRIBUTE_UNUSED,enum machine_mode mode)3742 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode)
3743 {
3744 rtx orig_x = x;
3745
3746 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT)
3747 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3748 force_operand (XEXP (x, 0), NULL_RTX));
3749 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT)
3750 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3751 force_operand (XEXP (x, 1), NULL_RTX));
3752 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS)
3753 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX),
3754 XEXP (x, 1));
3755 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS)
3756 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3757 force_operand (XEXP (x, 1), NULL_RTX));
3758
3759 if (x != orig_x && legitimate_address_p (mode, x, FALSE))
3760 return x;
3761
3762 if (tls_symbolic_operand (x))
3763 x = legitimize_tls_address (x);
3764 else if (flag_pic)
3765 x = legitimize_pic_address (x, mode, 0);
3766 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1)))
3767 x = gen_rtx_PLUS (Pmode, XEXP (x, 0),
3768 copy_to_mode_reg (Pmode, XEXP (x, 1)));
3769 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
3770 x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
3771 copy_to_mode_reg (Pmode, XEXP (x, 0)));
3772 else if (GET_CODE (x) == SYMBOL_REF
3773 || GET_CODE (x) == CONST
3774 || GET_CODE (x) == LABEL_REF)
3775 x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
3776 return x;
3777 }
3778
3779 /* Emit special PIC prologues. */
3780
3781 void
load_pic_register(void)3782 load_pic_register (void)
3783 {
3784 /* Labels to get the PC in the prologue of this function. */
3785 int orig_flag_pic = flag_pic;
3786
3787 if (! flag_pic)
3788 abort ();
3789
3790 /* If we haven't emitted the special get_pc helper function, do so now. */
3791 if (get_pc_symbol_name[0] == 0)
3792 {
3793 int align;
3794
3795 ASM_GENERATE_INTERNAL_LABEL (get_pc_symbol_name, "LGETPC", 0);
3796 text_section ();
3797
3798 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
3799 if (align > 0)
3800 ASM_OUTPUT_ALIGN (asm_out_file, align);
3801 (*targetm.asm_out.internal_label) (asm_out_file, "LGETPC", 0);
3802 fputs ("\tretl\n\tadd\t%o7, %l7, %l7\n", asm_out_file);
3803 }
3804
3805 /* Initialize every time through, since we can't easily
3806 know this to be permanent. */
3807 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3808 get_pc_symbol = gen_rtx_SYMBOL_REF (Pmode, get_pc_symbol_name);
3809 flag_pic = 0;
3810
3811 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table,
3812 get_pc_symbol));
3813
3814 flag_pic = orig_flag_pic;
3815
3816 /* Need to emit this whether or not we obey regdecls,
3817 since setjmp/longjmp can cause life info to screw up.
3818 ??? In the case where we don't obey regdecls, this is not sufficient
3819 since we may not fall out the bottom. */
3820 emit_insn (gen_rtx_USE (VOIDmode, pic_offset_table_rtx));
3821 }
3822
3823 /* Return 1 if RTX is a MEM which is known to be aligned to at
3824 least a DESIRED byte boundary. */
3825
3826 int
mem_min_alignment(rtx mem,int desired)3827 mem_min_alignment (rtx mem, int desired)
3828 {
3829 rtx addr, base, offset;
3830
3831 /* If it's not a MEM we can't accept it. */
3832 if (GET_CODE (mem) != MEM)
3833 return 0;
3834
3835 addr = XEXP (mem, 0);
3836 base = offset = NULL_RTX;
3837 if (GET_CODE (addr) == PLUS)
3838 {
3839 if (GET_CODE (XEXP (addr, 0)) == REG)
3840 {
3841 base = XEXP (addr, 0);
3842
3843 /* What we are saying here is that if the base
3844 REG is aligned properly, the compiler will make
3845 sure any REG based index upon it will be so
3846 as well. */
3847 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3848 offset = XEXP (addr, 1);
3849 else
3850 offset = const0_rtx;
3851 }
3852 }
3853 else if (GET_CODE (addr) == REG)
3854 {
3855 base = addr;
3856 offset = const0_rtx;
3857 }
3858
3859 if (base != NULL_RTX)
3860 {
3861 int regno = REGNO (base);
3862
3863 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM)
3864 {
3865 /* Check if the compiler has recorded some information
3866 about the alignment of the base REG. If reload has
3867 completed, we already matched with proper alignments.
3868 If not running global_alloc, reload might give us
3869 unaligned pointer to local stack though. */
3870 if (((cfun != 0
3871 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT)
3872 || (optimize && reload_completed))
3873 && (INTVAL (offset) & (desired - 1)) == 0)
3874 return 1;
3875 }
3876 else
3877 {
3878 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0)
3879 return 1;
3880 }
3881 }
3882 else if (! TARGET_UNALIGNED_DOUBLES
3883 || CONSTANT_P (addr)
3884 || GET_CODE (addr) == LO_SUM)
3885 {
3886 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES
3887 is true, in which case we can only assume that an access is aligned if
3888 it is to a constant address, or the address involves a LO_SUM. */
3889 return 1;
3890 }
3891
3892 /* An obviously unaligned address. */
3893 return 0;
3894 }
3895
3896
3897 /* Vectors to keep interesting information about registers where it can easily
3898 be got. We used to use the actual mode value as the bit number, but there
3899 are more than 32 modes now. Instead we use two tables: one indexed by
3900 hard register number, and one indexed by mode. */
3901
3902 /* The purpose of sparc_mode_class is to shrink the range of modes so that
3903 they all fit (as bit numbers) in a 32 bit word (again). Each real mode is
3904 mapped into one sparc_mode_class mode. */
3905
3906 enum sparc_mode_class {
3907 S_MODE, D_MODE, T_MODE, O_MODE,
3908 SF_MODE, DF_MODE, TF_MODE, OF_MODE,
3909 CC_MODE, CCFP_MODE
3910 };
3911
3912 /* Modes for single-word and smaller quantities. */
3913 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE))
3914
3915 /* Modes for double-word and smaller quantities. */
3916 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE))
3917
3918 /* Modes for quad-word and smaller quantities. */
3919 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE))
3920
3921 /* Modes for 8-word and smaller quantities. */
3922 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE))
3923
3924 /* Modes for single-float quantities. We must allow any single word or
3925 smaller quantity. This is because the fix/float conversion instructions
3926 take integer inputs/outputs from the float registers. */
3927 #define SF_MODES (S_MODES)
3928
3929 /* Modes for double-float and smaller quantities. */
3930 #define DF_MODES (S_MODES | D_MODES)
3931
3932 /* Modes for double-float only quantities. */
3933 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE))
3934
3935 /* Modes for quad-float only quantities. */
3936 #define TF_ONLY_MODES (1 << (int) TF_MODE)
3937
3938 /* Modes for quad-float and smaller quantities. */
3939 #define TF_MODES (DF_MODES | TF_ONLY_MODES)
3940
3941 /* Modes for quad-float and double-float quantities. */
3942 #define TF_MODES_NO_S (DF_MODES_NO_S | TF_ONLY_MODES)
3943
3944 /* Modes for quad-float pair only quantities. */
3945 #define OF_ONLY_MODES (1 << (int) OF_MODE)
3946
3947 /* Modes for quad-float pairs and smaller quantities. */
3948 #define OF_MODES (TF_MODES | OF_ONLY_MODES)
3949
3950 #define OF_MODES_NO_S (TF_MODES_NO_S | OF_ONLY_MODES)
3951
3952 /* Modes for condition codes. */
3953 #define CC_MODES (1 << (int) CC_MODE)
3954 #define CCFP_MODES (1 << (int) CCFP_MODE)
3955
3956 /* Value is 1 if register/mode pair is acceptable on sparc.
3957 The funny mixture of D and T modes is because integer operations
3958 do not specially operate on tetra quantities, so non-quad-aligned
3959 registers can hold quadword quantities (except %o4 and %i4 because
3960 they cross fixed registers). */
3961
3962 /* This points to either the 32 bit or the 64 bit version. */
3963 const int *hard_regno_mode_classes;
3964
3965 static const int hard_32bit_mode_classes[] = {
3966 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3967 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3968 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES,
3969 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES,
3970
3971 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3972 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3973 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3974 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
3975
3976 /* FP regs f32 to f63. Only the even numbered registers actually exist,
3977 and none can hold SFmode/SImode values. */
3978 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3979 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3980 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3981 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
3982
3983 /* %fcc[0123] */
3984 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
3985
3986 /* %icc */
3987 CC_MODES
3988 };
3989
3990 static const int hard_64bit_mode_classes[] = {
3991 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3992 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3993 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3994 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES,
3995
3996 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3997 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3998 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES,
3999 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES,
4000
4001 /* FP regs f32 to f63. Only the even numbered registers actually exist,
4002 and none can hold SFmode/SImode values. */
4003 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4004 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4005 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4006 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0,
4007
4008 /* %fcc[0123] */
4009 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES,
4010
4011 /* %icc */
4012 CC_MODES
4013 };
4014
4015 int sparc_mode_class [NUM_MACHINE_MODES];
4016
4017 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER];
4018
4019 static void
sparc_init_modes(void)4020 sparc_init_modes (void)
4021 {
4022 int i;
4023
4024 for (i = 0; i < NUM_MACHINE_MODES; i++)
4025 {
4026 switch (GET_MODE_CLASS (i))
4027 {
4028 case MODE_INT:
4029 case MODE_PARTIAL_INT:
4030 case MODE_COMPLEX_INT:
4031 if (GET_MODE_SIZE (i) <= 4)
4032 sparc_mode_class[i] = 1 << (int) S_MODE;
4033 else if (GET_MODE_SIZE (i) == 8)
4034 sparc_mode_class[i] = 1 << (int) D_MODE;
4035 else if (GET_MODE_SIZE (i) == 16)
4036 sparc_mode_class[i] = 1 << (int) T_MODE;
4037 else if (GET_MODE_SIZE (i) == 32)
4038 sparc_mode_class[i] = 1 << (int) O_MODE;
4039 else
4040 sparc_mode_class[i] = 0;
4041 break;
4042 case MODE_FLOAT:
4043 case MODE_COMPLEX_FLOAT:
4044 if (GET_MODE_SIZE (i) <= 4)
4045 sparc_mode_class[i] = 1 << (int) SF_MODE;
4046 else if (GET_MODE_SIZE (i) == 8)
4047 sparc_mode_class[i] = 1 << (int) DF_MODE;
4048 else if (GET_MODE_SIZE (i) == 16)
4049 sparc_mode_class[i] = 1 << (int) TF_MODE;
4050 else if (GET_MODE_SIZE (i) == 32)
4051 sparc_mode_class[i] = 1 << (int) OF_MODE;
4052 else
4053 sparc_mode_class[i] = 0;
4054 break;
4055 case MODE_CC:
4056 if (i == (int) CCFPmode || i == (int) CCFPEmode)
4057 sparc_mode_class[i] = 1 << (int) CCFP_MODE;
4058 else
4059 sparc_mode_class[i] = 1 << (int) CC_MODE;
4060 break;
4061 default:
4062 sparc_mode_class[i] = 0;
4063 break;
4064 }
4065 }
4066
4067 if (TARGET_ARCH64)
4068 hard_regno_mode_classes = hard_64bit_mode_classes;
4069 else
4070 hard_regno_mode_classes = hard_32bit_mode_classes;
4071
4072 /* Initialize the array used by REGNO_REG_CLASS. */
4073 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4074 {
4075 if (i < 16 && TARGET_V8PLUS)
4076 sparc_regno_reg_class[i] = I64_REGS;
4077 else if (i < 32 || i == FRAME_POINTER_REGNUM)
4078 sparc_regno_reg_class[i] = GENERAL_REGS;
4079 else if (i < 64)
4080 sparc_regno_reg_class[i] = FP_REGS;
4081 else if (i < 96)
4082 sparc_regno_reg_class[i] = EXTRA_FP_REGS;
4083 else if (i < 100)
4084 sparc_regno_reg_class[i] = FPCC_REGS;
4085 else
4086 sparc_regno_reg_class[i] = NO_REGS;
4087 }
4088 }
4089
4090 /* Save non call used registers from LOW to HIGH at BASE+OFFSET.
4091 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4092 v9 int regs as it simplifies the code. */
4093
4094 static int
save_regs(FILE * file,int low,int high,const char * base,int offset,int n_regs,HOST_WIDE_INT real_offset)4095 save_regs (FILE *file, int low, int high, const char *base,
4096 int offset, int n_regs, HOST_WIDE_INT real_offset)
4097 {
4098 int i;
4099
4100 if (TARGET_ARCH64 && high <= 32)
4101 {
4102 for (i = low; i < high; i++)
4103 {
4104 if (regs_ever_live[i] && ! call_used_regs[i])
4105 {
4106 fprintf (file, "\tstx\t%s, [%s+%d]\n",
4107 reg_names[i], base, offset + 4 * n_regs);
4108 if (dwarf2out_do_frame ())
4109 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4110 n_regs += 2;
4111 }
4112 }
4113 }
4114 else
4115 {
4116 for (i = low; i < high; i += 2)
4117 {
4118 if (regs_ever_live[i] && ! call_used_regs[i])
4119 {
4120 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4121 {
4122 fprintf (file, "\tstd\t%s, [%s+%d]\n",
4123 reg_names[i], base, offset + 4 * n_regs);
4124 if (dwarf2out_do_frame ())
4125 {
4126 char *l = dwarf2out_cfi_label ();
4127 dwarf2out_reg_save (l, i, real_offset + 4 * n_regs);
4128 dwarf2out_reg_save (l, i+1, real_offset + 4 * n_regs + 4);
4129 }
4130 n_regs += 2;
4131 }
4132 else
4133 {
4134 fprintf (file, "\tst\t%s, [%s+%d]\n",
4135 reg_names[i], base, offset + 4 * n_regs);
4136 if (dwarf2out_do_frame ())
4137 dwarf2out_reg_save ("", i, real_offset + 4 * n_regs);
4138 n_regs += 2;
4139 }
4140 }
4141 else
4142 {
4143 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4144 {
4145 fprintf (file, "\tst\t%s, [%s+%d]\n",
4146 reg_names[i+1], base, offset + 4 * n_regs + 4);
4147 if (dwarf2out_do_frame ())
4148 dwarf2out_reg_save ("", i + 1, real_offset + 4 * n_regs + 4);
4149 n_regs += 2;
4150 }
4151 }
4152 }
4153 }
4154 return n_regs;
4155 }
4156
4157 /* Restore non call used registers from LOW to HIGH at BASE+OFFSET.
4158
4159 N_REGS is the number of 4-byte regs saved thus far. This applies even to
4160 v9 int regs as it simplifies the code. */
4161
4162 static int
restore_regs(FILE * file,int low,int high,const char * base,int offset,int n_regs)4163 restore_regs (FILE *file, int low, int high, const char *base,
4164 int offset, int n_regs)
4165 {
4166 int i;
4167
4168 if (TARGET_ARCH64 && high <= 32)
4169 {
4170 for (i = low; i < high; i++)
4171 {
4172 if (regs_ever_live[i] && ! call_used_regs[i])
4173 fprintf (file, "\tldx\t[%s+%d], %s\n",
4174 base, offset + 4 * n_regs, reg_names[i]),
4175 n_regs += 2;
4176 }
4177 }
4178 else
4179 {
4180 for (i = low; i < high; i += 2)
4181 {
4182 if (regs_ever_live[i] && ! call_used_regs[i])
4183 if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4184 fprintf (file, "\tldd\t[%s+%d], %s\n",
4185 base, offset + 4 * n_regs, reg_names[i]),
4186 n_regs += 2;
4187 else
4188 fprintf (file, "\tld\t[%s+%d], %s\n",
4189 base, offset + 4 * n_regs, reg_names[i]),
4190 n_regs += 2;
4191 else if (regs_ever_live[i+1] && ! call_used_regs[i+1])
4192 fprintf (file, "\tld\t[%s+%d], %s\n",
4193 base, offset + 4 * n_regs + 4, reg_names[i+1]),
4194 n_regs += 2;
4195 }
4196 }
4197 return n_regs;
4198 }
4199
4200 /* Compute the frame size required by the function. This function is called
4201 during the reload pass and also by output_function_prologue(). */
4202
4203 HOST_WIDE_INT
compute_frame_size(HOST_WIDE_INT size,int leaf_function)4204 compute_frame_size (HOST_WIDE_INT size, int leaf_function)
4205 {
4206 int n_regs = 0, i;
4207 int outgoing_args_size = (current_function_outgoing_args_size
4208 + REG_PARM_STACK_SPACE (current_function_decl));
4209
4210 /* N_REGS is the number of 4-byte regs saved thus far. This applies
4211 even to v9 int regs to be consistent with save_regs/restore_regs. */
4212
4213 if (TARGET_ARCH64)
4214 {
4215 for (i = 0; i < 8; i++)
4216 if (regs_ever_live[i] && ! call_used_regs[i])
4217 n_regs += 2;
4218 }
4219 else
4220 {
4221 for (i = 0; i < 8; i += 2)
4222 if ((regs_ever_live[i] && ! call_used_regs[i])
4223 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4224 n_regs += 2;
4225 }
4226
4227 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2)
4228 if ((regs_ever_live[i] && ! call_used_regs[i])
4229 || (regs_ever_live[i+1] && ! call_used_regs[i+1]))
4230 n_regs += 2;
4231
4232 /* Set up values for use in `function_epilogue'. */
4233 num_gfregs = n_regs;
4234
4235 if (leaf_function && n_regs == 0
4236 && size == 0 && current_function_outgoing_args_size == 0)
4237 {
4238 actual_fsize = apparent_fsize = 0;
4239 }
4240 else
4241 {
4242 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */
4243 apparent_fsize = (size - STARTING_FRAME_OFFSET + 7) & -8;
4244 apparent_fsize += n_regs * 4;
4245 actual_fsize = apparent_fsize + ((outgoing_args_size + 7) & -8);
4246 }
4247
4248 /* Make sure nothing can clobber our register windows.
4249 If a SAVE must be done, or there is a stack-local variable,
4250 the register window area must be allocated.
4251 ??? For v8 we apparently need an additional 8 bytes of reserved space. */
4252 if (leaf_function == 0 || size > 0)
4253 actual_fsize += (16 * UNITS_PER_WORD) + (TARGET_ARCH64 ? 0 : 8);
4254
4255 return SPARC_STACK_ALIGN (actual_fsize);
4256 }
4257
4258 /* Build big number NUM in register REG and output the result to FILE.
4259 REG is guaranteed to be the only clobbered register. The function
4260 will very likely emit several instructions, so it must not be called
4261 from within a delay slot. */
4262
4263 static void
build_big_number(FILE * file,HOST_WIDE_INT num,const char * reg)4264 build_big_number (FILE *file, HOST_WIDE_INT num, const char *reg)
4265 {
4266 #if HOST_BITS_PER_WIDE_INT == 64
4267 HOST_WIDE_INT high_bits = (num >> 32) & 0xffffffff;
4268
4269 if (high_bits == 0
4270 #else
4271 if (num >= 0
4272 #endif
4273 || ! TARGET_ARCH64)
4274 {
4275 /* We don't use the 'set' macro because it appears to be broken
4276 in the Solaris 7 assembler. */
4277 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4278 num, reg);
4279 if ((num & 0x3ff) != 0)
4280 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4281 reg, num, reg);
4282 }
4283 #if HOST_BITS_PER_WIDE_INT == 64
4284 else if (high_bits == 0xffffffff) /* && TARGET_ARCH64 */
4285 #else
4286 else /* num < 0 && TARGET_ARCH64 */
4287 #endif
4288 {
4289 /* Sethi does not sign extend, so we must use a little trickery
4290 to use it for negative numbers. Invert the constant before
4291 loading it in, then use xor immediate to invert the loaded bits
4292 (along with the upper 32 bits) to the desired constant. This
4293 works because the sethi and immediate fields overlap. */
4294 HOST_WIDE_INT inv = ~num;
4295 HOST_WIDE_INT low = -0x400 + (num & 0x3ff);
4296
4297 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4298 inv, reg);
4299 fprintf (file, "\txor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4300 reg, low, reg);
4301 }
4302 #if HOST_BITS_PER_WIDE_INT == 64
4303 else /* TARGET_ARCH64 */
4304 {
4305 /* We don't use the 'setx' macro because if requires a scratch register.
4306 This is the translation of sparc_emit_set_const64_longway into asm.
4307 Hopefully we will soon have prologue/epilogue emitted as RTL. */
4308 HOST_WIDE_INT low1 = (num >> (32 - 12)) & 0xfff;
4309 HOST_WIDE_INT low2 = (num >> (32 - 12 - 12)) & 0xfff;
4310 HOST_WIDE_INT low3 = (num >> (32 - 12 - 12 - 8)) & 0x0ff;
4311 int to_shift = 12;
4312
4313 /* We don't use the 'set' macro because it appears to be broken
4314 in the Solaris 7 assembler. */
4315 fprintf (file, "\tsethi\t%%hi("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4316 high_bits, reg);
4317 if ((high_bits & 0x3ff) != 0)
4318 fprintf (file, "\tor\t%s, %%lo("HOST_WIDE_INT_PRINT_DEC"), %s\n",
4319 reg, high_bits, reg);
4320
4321 if (low1 != 0)
4322 {
4323 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4324 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4325 reg, low1, reg);
4326 to_shift = 12;
4327 }
4328 else
4329 {
4330 to_shift += 12;
4331 }
4332 if (low2 != 0)
4333 {
4334 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4335 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4336 reg, low2, reg);
4337 to_shift = 8;
4338 }
4339 else
4340 {
4341 to_shift += 8;
4342 }
4343 fprintf (file, "\tsllx\t%s, %d, %s\n", reg, to_shift, reg);
4344 if (low3 != 0)
4345 fprintf (file, "\tor\t%s, "HOST_WIDE_INT_PRINT_DEC", %s\n",
4346 reg, low3, reg);
4347 }
4348 #endif
4349 }
4350
4351 /* Output any necessary .register pseudo-ops. */
4352 void
sparc_output_scratch_registers(FILE * file ATTRIBUTE_UNUSED)4353 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED)
4354 {
4355 #ifdef HAVE_AS_REGISTER_PSEUDO_OP
4356 int i;
4357
4358 if (TARGET_ARCH32)
4359 return;
4360
4361 /* Check if %g[2367] were used without
4362 .register being printed for them already. */
4363 for (i = 2; i < 8; i++)
4364 {
4365 if (regs_ever_live [i]
4366 && ! sparc_hard_reg_printed [i])
4367 {
4368 sparc_hard_reg_printed [i] = 1;
4369 fprintf (file, "\t.register\t%%g%d, #scratch\n", i);
4370 }
4371 if (i == 3) i = 5;
4372 }
4373 #endif
4374 }
4375
4376 /* This function generates the assembly code for function entry.
4377 FILE is a stdio stream to output the code to.
4378 SIZE is an int: how many units of temporary storage to allocate.
4379 Refer to the array `regs_ever_live' to determine which registers
4380 to save; `regs_ever_live[I]' is nonzero if register number I
4381 is ever used in the function. This macro is responsible for
4382 knowing which registers should not be saved even if used. */
4383
4384 /* On SPARC, move-double insns between fpu and cpu need an 8-byte block
4385 of memory. If any fpu reg is used in the function, we allocate
4386 such a block here, at the bottom of the frame, just in case it's needed.
4387
4388 If this function is a leaf procedure, then we may choose not
4389 to do a "save" insn. The decision about whether or not
4390 to do this is made in regclass.c. */
4391
4392 static void
sparc_output_function_prologue(FILE * file,HOST_WIDE_INT size)4393 sparc_output_function_prologue (FILE *file, HOST_WIDE_INT size)
4394 {
4395 if (TARGET_FLAT)
4396 sparc_flat_function_prologue (file, size);
4397 else
4398 sparc_nonflat_function_prologue (file, size,
4399 current_function_uses_only_leaf_regs);
4400 }
4401
4402 /* Output code for the function prologue. */
4403
4404 static void
sparc_nonflat_function_prologue(FILE * file,HOST_WIDE_INT size,int leaf_function)4405 sparc_nonflat_function_prologue (FILE *file, HOST_WIDE_INT size,
4406 int leaf_function)
4407 {
4408 sparc_output_scratch_registers (file);
4409
4410 /* Need to use actual_fsize, since we are also allocating
4411 space for our callee (and our own register save area). */
4412 actual_fsize = compute_frame_size (size, leaf_function);
4413
4414 if (leaf_function)
4415 {
4416 frame_base_name = "%sp";
4417 frame_base_offset = actual_fsize + SPARC_STACK_BIAS;
4418 }
4419 else
4420 {
4421 frame_base_name = "%fp";
4422 frame_base_offset = SPARC_STACK_BIAS;
4423 }
4424
4425 /* This is only for the human reader. */
4426 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
4427
4428 if (actual_fsize == 0)
4429 /* do nothing. */ ;
4430 else if (! leaf_function)
4431 {
4432 if (actual_fsize <= 4096)
4433 fprintf (file, "\tsave\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4434 actual_fsize);
4435 else if (actual_fsize <= 8192)
4436 {
4437 fprintf (file, "\tsave\t%%sp, -4096, %%sp\n");
4438 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4439 actual_fsize - 4096);
4440 }
4441 else
4442 {
4443 build_big_number (file, -actual_fsize, "%g1");
4444 fprintf (file, "\tsave\t%%sp, %%g1, %%sp\n");
4445 }
4446 }
4447 else /* leaf function */
4448 {
4449 if (actual_fsize <= 4096)
4450 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4451 actual_fsize);
4452 else if (actual_fsize <= 8192)
4453 {
4454 fprintf (file, "\tadd\t%%sp, -4096, %%sp\n");
4455 fprintf (file, "\tadd\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4456 actual_fsize - 4096);
4457 }
4458 else
4459 {
4460 build_big_number (file, -actual_fsize, "%g1");
4461 fprintf (file, "\tadd\t%%sp, %%g1, %%sp\n");
4462 }
4463 }
4464
4465 if (dwarf2out_do_frame () && actual_fsize)
4466 {
4467 char *label = dwarf2out_cfi_label ();
4468
4469 /* The canonical frame address refers to the top of the frame. */
4470 dwarf2out_def_cfa (label, (leaf_function ? STACK_POINTER_REGNUM
4471 : HARD_FRAME_POINTER_REGNUM),
4472 frame_base_offset);
4473
4474 if (! leaf_function)
4475 {
4476 /* Note the register window save. This tells the unwinder that
4477 it needs to restore the window registers from the previous
4478 frame's window save area at 0(cfa). */
4479 dwarf2out_window_save (label);
4480
4481 /* The return address (-8) is now in %i7. */
4482 dwarf2out_return_reg (label, 31);
4483 }
4484 }
4485
4486 /* If doing anything with PIC, do it now. */
4487 if (! flag_pic)
4488 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
4489
4490 /* Call saved registers are saved just above the outgoing argument area. */
4491 if (num_gfregs)
4492 {
4493 HOST_WIDE_INT offset, real_offset;
4494 int n_regs;
4495 const char *base;
4496
4497 real_offset = -apparent_fsize;
4498 offset = -apparent_fsize + frame_base_offset;
4499 if (offset < -4096 || offset + num_gfregs * 4 > 4096)
4500 {
4501 /* ??? This might be optimized a little as %g1 might already have a
4502 value close enough that a single add insn will do. */
4503 /* ??? Although, all of this is probably only a temporary fix
4504 because if %g1 can hold a function result, then
4505 output_function_epilogue will lose (the result will get
4506 clobbered). */
4507 build_big_number (file, offset, "%g1");
4508 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4509 base = "%g1";
4510 offset = 0;
4511 }
4512 else
4513 {
4514 base = frame_base_name;
4515 }
4516
4517 n_regs = save_regs (file, 0, 8, base, offset, 0, real_offset);
4518 save_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs,
4519 real_offset);
4520 }
4521 }
4522
4523 /* Output code to restore any call saved registers. */
4524
4525 static void
output_restore_regs(FILE * file,int leaf_function ATTRIBUTE_UNUSED)4526 output_restore_regs (FILE *file, int leaf_function ATTRIBUTE_UNUSED)
4527 {
4528 HOST_WIDE_INT offset;
4529 int n_regs;
4530 const char *base;
4531
4532 offset = -apparent_fsize + frame_base_offset;
4533 if (offset < -4096 || offset + num_gfregs * 4 > 4096 - 8 /*double*/)
4534 {
4535 build_big_number (file, offset, "%g1");
4536 fprintf (file, "\tadd\t%s, %%g1, %%g1\n", frame_base_name);
4537 base = "%g1";
4538 offset = 0;
4539 }
4540 else
4541 {
4542 base = frame_base_name;
4543 }
4544
4545 n_regs = restore_regs (file, 0, 8, base, offset, 0);
4546 restore_regs (file, 32, TARGET_V9 ? 96 : 64, base, offset, n_regs);
4547 }
4548
4549 /* This function generates the assembly code for function exit,
4550 on machines that need it.
4551
4552 The function epilogue should not depend on the current stack pointer!
4553 It should use the frame pointer only. This is mandatory because
4554 of alloca; we also take advantage of it to omit stack adjustments
4555 before returning. */
4556
4557 static void
sparc_output_function_epilogue(FILE * file,HOST_WIDE_INT size)4558 sparc_output_function_epilogue (FILE *file, HOST_WIDE_INT size)
4559 {
4560 if (TARGET_FLAT)
4561 sparc_flat_function_epilogue (file, size);
4562 else
4563 sparc_nonflat_function_epilogue (file, size,
4564 current_function_uses_only_leaf_regs);
4565 }
4566
4567 /* Output code for the function epilogue. */
4568
4569 static void
sparc_nonflat_function_epilogue(FILE * file,HOST_WIDE_INT size ATTRIBUTE_UNUSED,int leaf_function)4570 sparc_nonflat_function_epilogue (FILE *file,
4571 HOST_WIDE_INT size ATTRIBUTE_UNUSED,
4572 int leaf_function)
4573 {
4574 const char *ret;
4575
4576 if (current_function_epilogue_delay_list == 0)
4577 {
4578 /* If code does not drop into the epilogue, we need
4579 do nothing except output pending case vectors.
4580
4581 We have to still output a dummy nop for the sake of
4582 sane backtraces. Otherwise, if the last two instructions
4583 of a function were call foo; dslot; this can make the return
4584 PC of foo (ie. address of call instruction plus 8) point to
4585 the first instruction in the next function. */
4586 rtx insn, last_real_insn;
4587
4588 insn = get_last_insn ();
4589
4590 last_real_insn = prev_real_insn (insn);
4591 if (last_real_insn
4592 && GET_CODE (last_real_insn) == INSN
4593 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE)
4594 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0);
4595
4596 if (last_real_insn && GET_CODE (last_real_insn) == CALL_INSN)
4597 fputs("\tnop\n", file);
4598
4599 if (GET_CODE (insn) == NOTE)
4600 insn = prev_nonnote_insn (insn);
4601 if (insn && GET_CODE (insn) == BARRIER)
4602 goto output_vectors;
4603 }
4604
4605 if (num_gfregs)
4606 output_restore_regs (file, leaf_function);
4607
4608 /* Work out how to skip the caller's unimp instruction if required. */
4609 if (leaf_function)
4610 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%o7+12" : "retl");
4611 else
4612 ret = (SKIP_CALLERS_UNIMP_P ? "jmp\t%i7+12" : "ret");
4613
4614 if (! leaf_function)
4615 {
4616 if (current_function_calls_eh_return)
4617 {
4618 if (current_function_epilogue_delay_list)
4619 abort ();
4620 if (SKIP_CALLERS_UNIMP_P)
4621 abort ();
4622
4623 fputs ("\trestore\n\tretl\n\tadd\t%sp, %g1, %sp\n", file);
4624 }
4625 /* If we wound up with things in our delay slot, flush them here. */
4626 else if (current_function_epilogue_delay_list)
4627 {
4628 rtx delay = PATTERN (XEXP (current_function_epilogue_delay_list, 0));
4629
4630 if (TARGET_V9 && ! epilogue_renumber (&delay, 1))
4631 {
4632 epilogue_renumber (&delay, 0);
4633 fputs (SKIP_CALLERS_UNIMP_P
4634 ? "\treturn\t%i7+12\n"
4635 : "\treturn\t%i7+8\n", file);
4636 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4637 file, 1, 0, 0, NULL);
4638 }
4639 else
4640 {
4641 rtx insn, src;
4642
4643 if (GET_CODE (delay) != SET)
4644 abort();
4645
4646 src = SET_SRC (delay);
4647 if (GET_CODE (src) == ASHIFT)
4648 {
4649 if (XEXP (src, 1) != const1_rtx)
4650 abort();
4651 SET_SRC (delay)
4652 = gen_rtx_PLUS (GET_MODE (src), XEXP (src, 0),
4653 XEXP (src, 0));
4654 }
4655
4656 insn = gen_rtx_PARALLEL (VOIDmode,
4657 gen_rtvec (2, delay,
4658 gen_rtx_RETURN (VOIDmode)));
4659 insn = emit_jump_insn (insn);
4660
4661 sparc_emitting_epilogue = true;
4662 final_scan_insn (insn, file, 1, 0, 1, NULL);
4663 sparc_emitting_epilogue = false;
4664 }
4665 }
4666 else if (TARGET_V9 && ! SKIP_CALLERS_UNIMP_P)
4667 fputs ("\treturn\t%i7+8\n\tnop\n", file);
4668 else
4669 fprintf (file, "\t%s\n\trestore\n", ret);
4670 }
4671 /* All of the following cases are for leaf functions. */
4672 else if (current_function_calls_eh_return)
4673 abort ();
4674 else if (current_function_epilogue_delay_list)
4675 {
4676 /* eligible_for_epilogue_delay_slot ensures that if this is a
4677 leaf function, then we will only have insn in the delay slot
4678 if the frame size is zero, thus no adjust for the stack is
4679 needed here. */
4680 if (actual_fsize != 0)
4681 abort ();
4682 fprintf (file, "\t%s\n", ret);
4683 final_scan_insn (XEXP (current_function_epilogue_delay_list, 0),
4684 file, 1, 0, 1, NULL);
4685 }
4686 /* Output 'nop' instead of 'sub %sp,-0,%sp' when no frame, so as to
4687 avoid generating confusing assembly language output. */
4688 else if (actual_fsize == 0)
4689 fprintf (file, "\t%s\n\tnop\n", ret);
4690 else if (actual_fsize <= 4096)
4691 fprintf (file, "\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4692 ret, actual_fsize);
4693 else if (actual_fsize <= 8192)
4694 fprintf (file, "\tsub\t%%sp, -4096, %%sp\n\t%s\n\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n",
4695 ret, actual_fsize - 4096);
4696 else
4697 {
4698 build_big_number (file, actual_fsize, "%g1");
4699 fprintf (file, "\t%s\n\tadd\t%%sp, %%g1, %%sp\n", ret);
4700 }
4701
4702 output_vectors:
4703 sparc_output_deferred_case_vectors ();
4704 }
4705
4706 /* Output a sibling call. */
4707
4708 const char *
output_sibcall(rtx insn,rtx call_operand)4709 output_sibcall (rtx insn, rtx call_operand)
4710 {
4711 int leaf_regs = current_function_uses_only_leaf_regs;
4712 rtx operands[3];
4713 int delay_slot = dbr_sequence_length () > 0;
4714
4715 if (num_gfregs)
4716 {
4717 /* Call to restore global regs might clobber
4718 the delay slot. Instead of checking for this
4719 output the delay slot now. */
4720 if (delay_slot)
4721 {
4722 rtx delay = NEXT_INSN (insn);
4723
4724 if (! delay)
4725 abort ();
4726
4727 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4728 PATTERN (delay) = gen_blockage ();
4729 INSN_CODE (delay) = -1;
4730 delay_slot = 0;
4731 }
4732 output_restore_regs (asm_out_file, leaf_regs);
4733 }
4734
4735 operands[0] = call_operand;
4736
4737 if (leaf_regs)
4738 {
4739 #ifdef HAVE_AS_RELAX_OPTION
4740 /* If as and ld are relaxing tail call insns into branch always,
4741 use or %o7,%g0,X; call Y; or X,%g0,%o7 always, so that it can
4742 be optimized. With sethi/jmpl as nor ld has no easy way how to
4743 find out if somebody does not branch between the sethi and jmpl. */
4744 int spare_slot = 0;
4745 #else
4746 int spare_slot = ((TARGET_ARCH32 || TARGET_CM_MEDLOW) && ! flag_pic);
4747 #endif
4748 HOST_WIDE_INT size = 0;
4749
4750 if ((actual_fsize || ! spare_slot) && delay_slot)
4751 {
4752 rtx delay = NEXT_INSN (insn);
4753
4754 if (! delay)
4755 abort ();
4756
4757 final_scan_insn (delay, asm_out_file, 1, 0, 1, NULL);
4758 PATTERN (delay) = gen_blockage ();
4759 INSN_CODE (delay) = -1;
4760 delay_slot = 0;
4761 }
4762 if (actual_fsize)
4763 {
4764 if (actual_fsize <= 4096)
4765 size = actual_fsize;
4766 else if (actual_fsize <= 8192)
4767 {
4768 fputs ("\tsub\t%sp, -4096, %sp\n", asm_out_file);
4769 size = actual_fsize - 4096;
4770 }
4771 else
4772 {
4773 build_big_number (asm_out_file, actual_fsize, "%g1");
4774 fputs ("\tadd\t%%sp, %%g1, %%sp\n", asm_out_file);
4775 }
4776 }
4777 if (spare_slot)
4778 {
4779 output_asm_insn ("sethi\t%%hi(%a0), %%g1", operands);
4780 output_asm_insn ("jmpl\t%%g1 + %%lo(%a0), %%g0", operands);
4781 if (size)
4782 fprintf (asm_out_file, "\t sub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4783 else if (! delay_slot)
4784 fputs ("\t nop\n", asm_out_file);
4785 }
4786 else
4787 {
4788 if (size)
4789 fprintf (asm_out_file, "\tsub\t%%sp, -"HOST_WIDE_INT_PRINT_DEC", %%sp\n", size);
4790 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize
4791 it into branch if possible. */
4792 output_asm_insn ("or\t%%o7, %%g0, %%g1", operands);
4793 output_asm_insn ("call\t%a0, 0", operands);
4794 output_asm_insn (" or\t%%g1, %%g0, %%o7", operands);
4795 }
4796 return "";
4797 }
4798
4799 output_asm_insn ("call\t%a0, 0", operands);
4800 if (delay_slot)
4801 {
4802 rtx delay = NEXT_INSN (insn), pat;
4803
4804 if (! delay)
4805 abort ();
4806
4807 pat = PATTERN (delay);
4808 if (GET_CODE (pat) != SET)
4809 abort ();
4810
4811 operands[0] = SET_DEST (pat);
4812 pat = SET_SRC (pat);
4813 switch (GET_CODE (pat))
4814 {
4815 case PLUS:
4816 operands[1] = XEXP (pat, 0);
4817 operands[2] = XEXP (pat, 1);
4818 output_asm_insn (" restore %r1, %2, %Y0", operands);
4819 break;
4820 case LO_SUM:
4821 operands[1] = XEXP (pat, 0);
4822 operands[2] = XEXP (pat, 1);
4823 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands);
4824 break;
4825 case ASHIFT:
4826 operands[1] = XEXP (pat, 0);
4827 output_asm_insn (" restore %r1, %r1, %Y0", operands);
4828 break;
4829 default:
4830 operands[1] = pat;
4831 output_asm_insn (" restore %%g0, %1, %Y0", operands);
4832 break;
4833 }
4834 PATTERN (delay) = gen_blockage ();
4835 INSN_CODE (delay) = -1;
4836 }
4837 else
4838 fputs ("\t restore\n", asm_out_file);
4839 return "";
4840 }
4841
4842 /* Functions for handling argument passing.
4843
4844 For v8 the first six args are normally in registers and the rest are
4845 pushed. Any arg that starts within the first 6 words is at least
4846 partially passed in a register unless its data type forbids.
4847
4848 For v9, the argument registers are laid out as an array of 16 elements
4849 and arguments are added sequentially. The first 6 int args and up to the
4850 first 16 fp args (depending on size) are passed in regs.
4851
4852 Slot Stack Integral Float Float in structure Double Long Double
4853 ---- ----- -------- ----- ------------------ ------ -----------
4854 15 [SP+248] %f31 %f30,%f31 %d30
4855 14 [SP+240] %f29 %f28,%f29 %d28 %q28
4856 13 [SP+232] %f27 %f26,%f27 %d26
4857 12 [SP+224] %f25 %f24,%f25 %d24 %q24
4858 11 [SP+216] %f23 %f22,%f23 %d22
4859 10 [SP+208] %f21 %f20,%f21 %d20 %q20
4860 9 [SP+200] %f19 %f18,%f19 %d18
4861 8 [SP+192] %f17 %f16,%f17 %d16 %q16
4862 7 [SP+184] %f15 %f14,%f15 %d14
4863 6 [SP+176] %f13 %f12,%f13 %d12 %q12
4864 5 [SP+168] %o5 %f11 %f10,%f11 %d10
4865 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8
4866 3 [SP+152] %o3 %f7 %f6,%f7 %d6
4867 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4
4868 1 [SP+136] %o1 %f3 %f2,%f3 %d2
4869 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0
4870
4871 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise.
4872
4873 Integral arguments are always passed as 64 bit quantities appropriately
4874 extended.
4875
4876 Passing of floating point values is handled as follows.
4877 If a prototype is in scope:
4878 If the value is in a named argument (i.e. not a stdarg function or a
4879 value not part of the `...') then the value is passed in the appropriate
4880 fp reg.
4881 If the value is part of the `...' and is passed in one of the first 6
4882 slots then the value is passed in the appropriate int reg.
4883 If the value is part of the `...' and is not passed in one of the first 6
4884 slots then the value is passed in memory.
4885 If a prototype is not in scope:
4886 If the value is one of the first 6 arguments the value is passed in the
4887 appropriate integer reg and the appropriate fp reg.
4888 If the value is not one of the first 6 arguments the value is passed in
4889 the appropriate fp reg and in memory.
4890 */
4891
4892 /* Maximum number of int regs for args. */
4893 #define SPARC_INT_ARG_MAX 6
4894 /* Maximum number of fp regs for args. */
4895 #define SPARC_FP_ARG_MAX 16
4896
4897 #define ROUND_ADVANCE(SIZE) (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
4898
4899 /* Handle the INIT_CUMULATIVE_ARGS macro.
4900 Initialize a variable CUM of type CUMULATIVE_ARGS
4901 for a call to a function whose data type is FNTYPE.
4902 For a library call, FNTYPE is 0. */
4903
4904 void
init_cumulative_args(struct sparc_args * cum,tree fntype,rtx libname ATTRIBUTE_UNUSED,tree fndecl ATTRIBUTE_UNUSED)4905 init_cumulative_args (struct sparc_args *cum, tree fntype,
4906 rtx libname ATTRIBUTE_UNUSED,
4907 tree fndecl ATTRIBUTE_UNUSED)
4908 {
4909 cum->words = 0;
4910 cum->prototype_p = fntype && TYPE_ARG_TYPES (fntype);
4911 cum->libcall_p = fntype == 0;
4912 }
4913
4914 /* Scan the record type TYPE and return the following predicates:
4915 - INTREGS_P: the record contains at least one field or sub-field
4916 that is eligible for promotion in integer registers.
4917 - FP_REGS_P: the record contains at least one field or sub-field
4918 that is eligible for promotion in floating-point registers.
4919 - PACKED_P: the record contains at least one field that is packed.
4920
4921 Sub-fields are not taken into account for the PACKED_P predicate. */
4922
4923 static void
scan_record_type(tree type,int * intregs_p,int * fpregs_p,int * packed_p)4924 scan_record_type (tree type, int *intregs_p, int *fpregs_p, int *packed_p)
4925 {
4926 tree field;
4927
4928 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
4929 {
4930 if (TREE_CODE (field) == FIELD_DECL)
4931 {
4932 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
4933 scan_record_type (TREE_TYPE (field), intregs_p, fpregs_p, 0);
4934 else if (FLOAT_TYPE_P (TREE_TYPE (field)) && TARGET_FPU)
4935 *fpregs_p = 1;
4936 else
4937 *intregs_p = 1;
4938
4939 if (packed_p && DECL_PACKED (field))
4940 *packed_p = 1;
4941 }
4942 }
4943 }
4944
4945 /* Compute the slot number to pass an argument in.
4946 Return the slot number or -1 if passing on the stack.
4947
4948 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4949 the preceding args and about the function being called.
4950 MODE is the argument's machine mode.
4951 TYPE is the data type of the argument (as a tree).
4952 This is null for libcalls where that information may
4953 not be available.
4954 NAMED is nonzero if this argument is a named parameter
4955 (otherwise it is an extra parameter matching an ellipsis).
4956 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG.
4957 *PREGNO records the register number to use if scalar type.
4958 *PPADDING records the amount of padding needed in words. */
4959
4960 static int
function_arg_slotno(const struct sparc_args * cum,enum machine_mode mode,tree type,int named,int incoming_p,int * pregno,int * ppadding)4961 function_arg_slotno (const struct sparc_args *cum, enum machine_mode mode,
4962 tree type, int named, int incoming_p,
4963 int *pregno, int *ppadding)
4964 {
4965 int regbase = (incoming_p
4966 ? SPARC_INCOMING_INT_ARG_FIRST
4967 : SPARC_OUTGOING_INT_ARG_FIRST);
4968 int slotno = cum->words;
4969 int regno;
4970
4971 *ppadding = 0;
4972
4973 if (type != 0 && TREE_ADDRESSABLE (type))
4974 return -1;
4975 if (TARGET_ARCH32
4976 && type != 0 && mode == BLKmode
4977 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0)
4978 return -1;
4979
4980 switch (mode)
4981 {
4982 case VOIDmode :
4983 /* MODE is VOIDmode when generating the actual call.
4984 See emit_call_1. */
4985 return -1;
4986
4987 case TImode : case CTImode :
4988 if (TARGET_ARCH64 && (slotno & 1) != 0)
4989 slotno++, *ppadding = 1;
4990 /* fallthrough */
4991
4992 case QImode : case CQImode :
4993 case HImode : case CHImode :
4994 case SImode : case CSImode :
4995 case DImode : case CDImode :
4996 if (slotno >= SPARC_INT_ARG_MAX)
4997 return -1;
4998 regno = regbase + slotno;
4999 break;
5000
5001 case TFmode : case TCmode :
5002 if (TARGET_ARCH64 && (slotno & 1) != 0)
5003 slotno++, *ppadding = 1;
5004 /* fallthrough */
5005
5006 case SFmode : case SCmode :
5007 case DFmode : case DCmode :
5008 if (TARGET_ARCH32)
5009 {
5010 if (slotno >= SPARC_INT_ARG_MAX)
5011 return -1;
5012 regno = regbase + slotno;
5013 }
5014 else
5015 {
5016 if (TARGET_FPU && named)
5017 {
5018 if (slotno >= SPARC_FP_ARG_MAX)
5019 return -1;
5020 regno = SPARC_FP_ARG_FIRST + slotno * 2;
5021 if (mode == SFmode)
5022 regno++;
5023 }
5024 else
5025 {
5026 if (slotno >= SPARC_INT_ARG_MAX)
5027 return -1;
5028 regno = regbase + slotno;
5029 }
5030 }
5031 break;
5032
5033 case BLKmode :
5034 /* For sparc64, objects requiring 16 byte alignment get it. */
5035 if (TARGET_ARCH64)
5036 {
5037 if (type && TYPE_ALIGN (type) == 128 && (slotno & 1) != 0)
5038 slotno++, *ppadding = 1;
5039 }
5040
5041 if (TARGET_ARCH32
5042 || (type && TREE_CODE (type) == UNION_TYPE))
5043 {
5044 if (slotno >= SPARC_INT_ARG_MAX)
5045 return -1;
5046 regno = regbase + slotno;
5047 }
5048 else
5049 {
5050 int intregs_p = 0, fpregs_p = 0, packed_p = 0;
5051
5052 /* First see what kinds of registers we would need. */
5053 scan_record_type (type, &intregs_p, &fpregs_p, &packed_p);
5054
5055 /* The ABI obviously doesn't specify how packed structures
5056 are passed. These are defined to be passed in int regs
5057 if possible, otherwise memory. */
5058 if (packed_p || !named)
5059 fpregs_p = 0, intregs_p = 1;
5060
5061 /* If all arg slots are filled, then must pass on stack. */
5062 if (fpregs_p && slotno >= SPARC_FP_ARG_MAX)
5063 return -1;
5064 /* If there are only int args and all int arg slots are filled,
5065 then must pass on stack. */
5066 if (!fpregs_p && intregs_p && slotno >= SPARC_INT_ARG_MAX)
5067 return -1;
5068 /* Note that even if all int arg slots are filled, fp members may
5069 still be passed in regs if such regs are available.
5070 *PREGNO isn't set because there may be more than one, it's up
5071 to the caller to compute them. */
5072 return slotno;
5073 }
5074 break;
5075
5076 default :
5077 abort ();
5078 }
5079
5080 *pregno = regno;
5081 return slotno;
5082 }
5083
5084 /* Handle recursive register counting for structure field layout. */
5085
5086 struct function_arg_record_value_parms
5087 {
5088 rtx ret; /* return expression being built. */
5089 int slotno; /* slot number of the argument. */
5090 int named; /* whether the argument is named. */
5091 int regbase; /* regno of the base register. */
5092 int stack; /* 1 if part of the argument is on the stack. */
5093 int intoffset; /* offset of the first pending integer field. */
5094 unsigned int nregs; /* number of words passed in registers. */
5095 };
5096
5097 static void function_arg_record_value_3
5098 (HOST_WIDE_INT, struct function_arg_record_value_parms *);
5099 static void function_arg_record_value_2
5100 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5101 static void function_arg_record_value_1
5102 (tree, HOST_WIDE_INT, struct function_arg_record_value_parms *, bool);
5103 static rtx function_arg_record_value (tree, enum machine_mode, int, int, int);
5104 static rtx function_arg_union_value (int, enum machine_mode, int);
5105
5106 /* A subroutine of function_arg_record_value. Traverse the structure
5107 recursively and determine how many registers will be required. */
5108
5109 static void
function_arg_record_value_1(tree type,HOST_WIDE_INT startbitpos,struct function_arg_record_value_parms * parms,bool packed_p)5110 function_arg_record_value_1 (tree type, HOST_WIDE_INT startbitpos,
5111 struct function_arg_record_value_parms *parms,
5112 bool packed_p)
5113 {
5114 tree field;
5115
5116 /* We need to compute how many registers are needed so we can
5117 allocate the PARALLEL but before we can do that we need to know
5118 whether there are any packed fields. The ABI obviously doesn't
5119 specify how structures are passed in this case, so they are
5120 defined to be passed in int regs if possible, otherwise memory,
5121 regardless of whether there are fp values present. */
5122
5123 if (! packed_p)
5124 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5125 {
5126 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5127 {
5128 packed_p = true;
5129 break;
5130 }
5131 }
5132
5133 /* Compute how many registers we need. */
5134 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5135 {
5136 if (TREE_CODE (field) == FIELD_DECL)
5137 {
5138 HOST_WIDE_INT bitpos = startbitpos;
5139
5140 if (DECL_SIZE (field) != 0
5141 && host_integerp (bit_position (field), 1))
5142 bitpos += int_bit_position (field);
5143
5144 /* ??? FIXME: else assume zero offset. */
5145
5146 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5147 function_arg_record_value_1 (TREE_TYPE (field),
5148 bitpos,
5149 parms,
5150 packed_p);
5151 else if (FLOAT_TYPE_P (TREE_TYPE (field))
5152 && TARGET_FPU
5153 && parms->named
5154 && ! packed_p)
5155 {
5156 if (parms->intoffset != -1)
5157 {
5158 unsigned int startbit, endbit;
5159 int intslots, this_slotno;
5160
5161 startbit = parms->intoffset & -BITS_PER_WORD;
5162 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5163
5164 intslots = (endbit - startbit) / BITS_PER_WORD;
5165 this_slotno = parms->slotno + parms->intoffset
5166 / BITS_PER_WORD;
5167
5168 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5169 {
5170 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5171 /* We need to pass this field on the stack. */
5172 parms->stack = 1;
5173 }
5174
5175 parms->nregs += intslots;
5176 parms->intoffset = -1;
5177 }
5178
5179 /* There's no need to check this_slotno < SPARC_FP_ARG MAX.
5180 If it wasn't true we wouldn't be here. */
5181 parms->nregs += 1;
5182 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5183 parms->nregs += 1;
5184 }
5185 else
5186 {
5187 if (parms->intoffset == -1)
5188 parms->intoffset = bitpos;
5189 }
5190 }
5191 }
5192 }
5193
5194 /* A subroutine of function_arg_record_value. Assign the bits of the
5195 structure between parms->intoffset and bitpos to integer registers. */
5196
5197 static void
function_arg_record_value_3(HOST_WIDE_INT bitpos,struct function_arg_record_value_parms * parms)5198 function_arg_record_value_3 (HOST_WIDE_INT bitpos,
5199 struct function_arg_record_value_parms *parms)
5200 {
5201 enum machine_mode mode;
5202 unsigned int regno;
5203 unsigned int startbit, endbit;
5204 int this_slotno, intslots, intoffset;
5205 rtx reg;
5206
5207 if (parms->intoffset == -1)
5208 return;
5209
5210 intoffset = parms->intoffset;
5211 parms->intoffset = -1;
5212
5213 startbit = intoffset & -BITS_PER_WORD;
5214 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5215 intslots = (endbit - startbit) / BITS_PER_WORD;
5216 this_slotno = parms->slotno + intoffset / BITS_PER_WORD;
5217
5218 intslots = MIN (intslots, SPARC_INT_ARG_MAX - this_slotno);
5219 if (intslots <= 0)
5220 return;
5221
5222 /* If this is the trailing part of a word, only load that much into
5223 the register. Otherwise load the whole register. Note that in
5224 the latter case we may pick up unwanted bits. It's not a problem
5225 at the moment but may wish to revisit. */
5226
5227 if (intoffset % BITS_PER_WORD != 0)
5228 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5229 MODE_INT, 0);
5230 else
5231 mode = word_mode;
5232
5233 intoffset /= BITS_PER_UNIT;
5234 do
5235 {
5236 regno = parms->regbase + this_slotno;
5237 reg = gen_rtx_REG (mode, regno);
5238 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5239 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5240
5241 this_slotno += 1;
5242 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5243 mode = word_mode;
5244 parms->nregs += 1;
5245 intslots -= 1;
5246 }
5247 while (intslots > 0);
5248 }
5249
5250 /* A subroutine of function_arg_record_value. Traverse the structure
5251 recursively and assign bits to floating point registers. Track which
5252 bits in between need integer registers; invoke function_arg_record_value_3
5253 to make that happen. */
5254
5255 static void
function_arg_record_value_2(tree type,HOST_WIDE_INT startbitpos,struct function_arg_record_value_parms * parms,bool packed_p)5256 function_arg_record_value_2 (tree type, HOST_WIDE_INT startbitpos,
5257 struct function_arg_record_value_parms *parms,
5258 bool packed_p)
5259 {
5260 tree field;
5261
5262 if (! packed_p)
5263 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5264 {
5265 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field))
5266 {
5267 packed_p = true;
5268 break;
5269 }
5270 }
5271
5272 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
5273 {
5274 if (TREE_CODE (field) == FIELD_DECL)
5275 {
5276 HOST_WIDE_INT bitpos = startbitpos;
5277
5278 if (DECL_SIZE (field) != 0
5279 && host_integerp (bit_position (field), 1))
5280 bitpos += int_bit_position (field);
5281
5282 /* ??? FIXME: else assume zero offset. */
5283
5284 if (TREE_CODE (TREE_TYPE (field)) == RECORD_TYPE)
5285 function_arg_record_value_2 (TREE_TYPE (field),
5286 bitpos,
5287 parms,
5288 packed_p);
5289 else if (FLOAT_TYPE_P (TREE_TYPE (field))
5290 && TARGET_FPU
5291 && parms->named
5292 && ! packed_p)
5293 {
5294 int this_slotno = parms->slotno + bitpos / BITS_PER_WORD;
5295 int regno;
5296 enum machine_mode mode = DECL_MODE (field);
5297 rtx reg;
5298
5299 function_arg_record_value_3 (bitpos, parms);
5300 regno = SPARC_FP_ARG_FIRST + this_slotno * 2
5301 + ((mode == SFmode || mode == SCmode)
5302 && (bitpos & 32) != 0);
5303 switch (mode)
5304 {
5305 case SCmode: mode = SFmode; break;
5306 case DCmode: mode = DFmode; break;
5307 case TCmode: mode = TFmode; break;
5308 default: break;
5309 }
5310 reg = gen_rtx_REG (mode, regno);
5311 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5312 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5313 GEN_INT (bitpos / BITS_PER_UNIT));
5314 parms->nregs += 1;
5315 if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE)
5316 {
5317 regno += GET_MODE_SIZE (mode) / 4;
5318 reg = gen_rtx_REG (mode, regno);
5319 XVECEXP (parms->ret, 0, parms->stack + parms->nregs)
5320 = gen_rtx_EXPR_LIST (VOIDmode, reg,
5321 GEN_INT ((bitpos + GET_MODE_BITSIZE (mode))
5322 / BITS_PER_UNIT));
5323 parms->nregs += 1;
5324 }
5325 }
5326 else
5327 {
5328 if (parms->intoffset == -1)
5329 parms->intoffset = bitpos;
5330 }
5331 }
5332 }
5333 }
5334
5335 /* Used by function_arg and function_value to implement the complex
5336 conventions of the 64-bit ABI for passing and returning structures.
5337 Return an expression valid as a return value for the two macros
5338 FUNCTION_ARG and FUNCTION_VALUE.
5339
5340 TYPE is the data type of the argument (as a tree).
5341 This is null for libcalls where that information may
5342 not be available.
5343 MODE is the argument's machine mode.
5344 SLOTNO is the index number of the argument's slot in the parameter array.
5345 NAMED is nonzero if this argument is a named parameter
5346 (otherwise it is an extra parameter matching an ellipsis).
5347 REGBASE is the regno of the base register for the parameter array. */
5348
5349 static rtx
function_arg_record_value(tree type,enum machine_mode mode,int slotno,int named,int regbase)5350 function_arg_record_value (tree type, enum machine_mode mode,
5351 int slotno, int named, int regbase)
5352 {
5353 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5354 struct function_arg_record_value_parms parms;
5355 unsigned int nregs;
5356
5357 parms.ret = NULL_RTX;
5358 parms.slotno = slotno;
5359 parms.named = named;
5360 parms.regbase = regbase;
5361 parms.stack = 0;
5362
5363 /* Compute how many registers we need. */
5364 parms.nregs = 0;
5365 parms.intoffset = 0;
5366 function_arg_record_value_1 (type, 0, &parms, false);
5367
5368 /* Take into account pending integer fields. */
5369 if (parms.intoffset != -1)
5370 {
5371 unsigned int startbit, endbit;
5372 int intslots, this_slotno;
5373
5374 startbit = parms.intoffset & -BITS_PER_WORD;
5375 endbit = (typesize*BITS_PER_UNIT + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5376 intslots = (endbit - startbit) / BITS_PER_WORD;
5377 this_slotno = slotno + parms.intoffset / BITS_PER_WORD;
5378
5379 if (intslots > 0 && intslots > SPARC_INT_ARG_MAX - this_slotno)
5380 {
5381 intslots = MAX (0, SPARC_INT_ARG_MAX - this_slotno);
5382 /* We need to pass this field on the stack. */
5383 parms.stack = 1;
5384 }
5385
5386 parms.nregs += intslots;
5387 }
5388 nregs = parms.nregs;
5389
5390 /* Allocate the vector and handle some annoying special cases. */
5391 if (nregs == 0)
5392 {
5393 /* ??? Empty structure has no value? Duh? */
5394 if (typesize <= 0)
5395 {
5396 /* Though there's nothing really to store, return a word register
5397 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL
5398 leads to breakage due to the fact that there are zero bytes to
5399 load. */
5400 return gen_rtx_REG (mode, regbase);
5401 }
5402 else
5403 {
5404 /* ??? C++ has structures with no fields, and yet a size. Give up
5405 for now and pass everything back in integer registers. */
5406 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
5407 }
5408 if (nregs + slotno > SPARC_INT_ARG_MAX)
5409 nregs = SPARC_INT_ARG_MAX - slotno;
5410 }
5411 if (nregs == 0)
5412 abort ();
5413
5414 parms.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (parms.stack + nregs));
5415
5416 /* If at least one field must be passed on the stack, generate
5417 (parallel [(expr_list (nil) ...) ...]) so that all fields will
5418 also be passed on the stack. We can't do much better because the
5419 semantics of FUNCTION_ARG_PARTIAL_NREGS doesn't handle the case
5420 of structures for which the fields passed exclusively in registers
5421 are not at the beginning of the structure. */
5422 if (parms.stack)
5423 XVECEXP (parms.ret, 0, 0)
5424 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5425
5426 /* Fill in the entries. */
5427 parms.nregs = 0;
5428 parms.intoffset = 0;
5429 function_arg_record_value_2 (type, 0, &parms, false);
5430 function_arg_record_value_3 (typesize * BITS_PER_UNIT, &parms);
5431
5432 if (parms.nregs != nregs)
5433 abort ();
5434
5435 return parms.ret;
5436 }
5437
5438 /* Used by function_arg and function_value to implement the conventions
5439 of the 64-bit ABI for passing and returning unions.
5440 Return an expression valid as a return value for the two macros
5441 FUNCTION_ARG and FUNCTION_VALUE.
5442
5443 SIZE is the size in bytes of the union.
5444 MODE is the argument's machine mode.
5445 REGNO is the hard register the union will be passed in. */
5446
5447 static rtx
function_arg_union_value(int size,enum machine_mode mode,int regno)5448 function_arg_union_value (int size, enum machine_mode mode, int regno)
5449 {
5450 int nwords = ROUND_ADVANCE (size), i;
5451 rtx regs;
5452
5453 /* Unions are passed left-justified. */
5454 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords));
5455
5456 for (i = 0; i < nwords; i++)
5457 XVECEXP (regs, 0, i)
5458 = gen_rtx_EXPR_LIST (VOIDmode,
5459 gen_rtx_REG (word_mode, regno + i),
5460 GEN_INT (UNITS_PER_WORD * i));
5461
5462 return regs;
5463 }
5464
5465 /* Handle the FUNCTION_ARG macro.
5466 Determine where to put an argument to a function.
5467 Value is zero to push the argument on the stack,
5468 or a hard register in which to store the argument.
5469
5470 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5471 the preceding args and about the function being called.
5472 MODE is the argument's machine mode.
5473 TYPE is the data type of the argument (as a tree).
5474 This is null for libcalls where that information may
5475 not be available.
5476 NAMED is nonzero if this argument is a named parameter
5477 (otherwise it is an extra parameter matching an ellipsis).
5478 INCOMING_P is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. */
5479
5480 rtx
function_arg(const struct sparc_args * cum,enum machine_mode mode,tree type,int named,int incoming_p)5481 function_arg (const struct sparc_args *cum, enum machine_mode mode,
5482 tree type, int named, int incoming_p)
5483 {
5484 int regbase = (incoming_p
5485 ? SPARC_INCOMING_INT_ARG_FIRST
5486 : SPARC_OUTGOING_INT_ARG_FIRST);
5487 int slotno, regno, padding;
5488 rtx reg;
5489
5490 slotno = function_arg_slotno (cum, mode, type, named, incoming_p,
5491 ®no, &padding);
5492
5493 if (slotno == -1)
5494 return 0;
5495
5496 if (TARGET_ARCH32)
5497 {
5498 reg = gen_rtx_REG (mode, regno);
5499 return reg;
5500 }
5501
5502 if (type && TREE_CODE (type) == RECORD_TYPE)
5503 {
5504 /* Structures up to 16 bytes in size are passed in arg slots on the
5505 stack and are promoted to registers where possible. */
5506
5507 if (int_size_in_bytes (type) > 16)
5508 abort (); /* shouldn't get here */
5509
5510 return function_arg_record_value (type, mode, slotno, named, regbase);
5511 }
5512 else if (type && TREE_CODE (type) == UNION_TYPE)
5513 {
5514 HOST_WIDE_INT size = int_size_in_bytes (type);
5515
5516 if (size > 16)
5517 abort (); /* shouldn't get here */
5518
5519 return function_arg_union_value (size, mode, regno);
5520 }
5521 /* v9 fp args in reg slots beyond the int reg slots get passed in regs
5522 but also have the slot allocated for them.
5523 If no prototype is in scope fp values in register slots get passed
5524 in two places, either fp regs and int regs or fp regs and memory. */
5525 else if ((GET_MODE_CLASS (mode) == MODE_FLOAT
5526 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5527 && SPARC_FP_REG_P (regno))
5528 {
5529 reg = gen_rtx_REG (mode, regno);
5530 if (cum->prototype_p || cum->libcall_p)
5531 {
5532 /* "* 2" because fp reg numbers are recorded in 4 byte
5533 quantities. */
5534 #if 0
5535 /* ??? This will cause the value to be passed in the fp reg and
5536 in the stack. When a prototype exists we want to pass the
5537 value in the reg but reserve space on the stack. That's an
5538 optimization, and is deferred [for a bit]. */
5539 if ((regno - SPARC_FP_ARG_FIRST) >= SPARC_INT_ARG_MAX * 2)
5540 return gen_rtx_PARALLEL (mode,
5541 gen_rtvec (2,
5542 gen_rtx_EXPR_LIST (VOIDmode,
5543 NULL_RTX, const0_rtx),
5544 gen_rtx_EXPR_LIST (VOIDmode,
5545 reg, const0_rtx)));
5546 else
5547 #else
5548 /* ??? It seems that passing back a register even when past
5549 the area declared by REG_PARM_STACK_SPACE will allocate
5550 space appropriately, and will not copy the data onto the
5551 stack, exactly as we desire.
5552
5553 This is due to locate_and_pad_parm being called in
5554 expand_call whenever reg_parm_stack_space > 0, which
5555 while beneficial to our example here, would seem to be
5556 in error from what had been intended. Ho hum... -- r~ */
5557 #endif
5558 return reg;
5559 }
5560 else
5561 {
5562 rtx v0, v1;
5563
5564 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2)
5565 {
5566 int intreg;
5567
5568 /* On incoming, we don't need to know that the value
5569 is passed in %f0 and %i0, and it confuses other parts
5570 causing needless spillage even on the simplest cases. */
5571 if (incoming_p)
5572 return reg;
5573
5574 intreg = (SPARC_OUTGOING_INT_ARG_FIRST
5575 + (regno - SPARC_FP_ARG_FIRST) / 2);
5576
5577 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5578 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg),
5579 const0_rtx);
5580 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5581 }
5582 else
5583 {
5584 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5585 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx);
5586 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1));
5587 }
5588 }
5589 }
5590 else
5591 {
5592 /* Scalar or complex int. */
5593 reg = gen_rtx_REG (mode, regno);
5594 }
5595
5596 return reg;
5597 }
5598
5599 /* Handle the FUNCTION_ARG_PARTIAL_NREGS macro.
5600 For an arg passed partly in registers and partly in memory,
5601 this is the number of registers used.
5602 For args passed entirely in registers or entirely in memory, zero.
5603
5604 Any arg that starts in the first 6 regs but won't entirely fit in them
5605 needs partial registers on v8. On v9, structures with integer
5606 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp
5607 values that begin in the last fp reg [where "last fp reg" varies with the
5608 mode] will be split between that reg and memory. */
5609
5610 int
function_arg_partial_nregs(const struct sparc_args * cum,enum machine_mode mode,tree type,int named)5611 function_arg_partial_nregs (const struct sparc_args *cum,
5612 enum machine_mode mode, tree type, int named)
5613 {
5614 int slotno, regno, padding;
5615
5616 /* We pass 0 for incoming_p here, it doesn't matter. */
5617 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5618
5619 if (slotno == -1)
5620 return 0;
5621
5622 if (TARGET_ARCH32)
5623 {
5624 if ((slotno + (mode == BLKmode
5625 ? ROUND_ADVANCE (int_size_in_bytes (type))
5626 : ROUND_ADVANCE (GET_MODE_SIZE (mode))))
5627 > NPARM_REGS (SImode))
5628 return NPARM_REGS (SImode) - slotno;
5629 return 0;
5630 }
5631 else
5632 {
5633 if (type && AGGREGATE_TYPE_P (type))
5634 {
5635 int size = int_size_in_bytes (type);
5636 int align = TYPE_ALIGN (type);
5637
5638 if (align == 16)
5639 slotno += slotno & 1;
5640 if (size > 8 && size <= 16
5641 && slotno == SPARC_INT_ARG_MAX - 1)
5642 return 1;
5643 }
5644 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT
5645 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT
5646 && ! (TARGET_FPU && named)))
5647 {
5648 /* The complex types are passed as packed types. */
5649 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD)
5650 return 0;
5651
5652 if (GET_MODE_ALIGNMENT (mode) == 128)
5653 {
5654 slotno += slotno & 1;
5655
5656 /* ??? The mode needs 3 slots? */
5657 if (slotno == SPARC_INT_ARG_MAX - 2)
5658 return 1;
5659 }
5660 else
5661 {
5662 if (slotno == SPARC_INT_ARG_MAX - 1)
5663 return 1;
5664 }
5665 }
5666 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT)
5667 {
5668 if (GET_MODE_ALIGNMENT (mode) == 128)
5669 slotno += slotno & 1;
5670 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD)
5671 > SPARC_FP_ARG_MAX)
5672 return 1;
5673 }
5674 return 0;
5675 }
5676 }
5677
5678 /* Handle the FUNCTION_ARG_PASS_BY_REFERENCE macro.
5679 !v9: The SPARC ABI stipulates passing struct arguments (of any size) and
5680 quad-precision floats by invisible reference.
5681 v9: Aggregates greater than 16 bytes are passed by reference.
5682 For Pascal, also pass arrays by reference. */
5683
5684 int
function_arg_pass_by_reference(const struct sparc_args * cum ATTRIBUTE_UNUSED,enum machine_mode mode,tree type,int named ATTRIBUTE_UNUSED)5685 function_arg_pass_by_reference (const struct sparc_args *cum ATTRIBUTE_UNUSED,
5686 enum machine_mode mode, tree type,
5687 int named ATTRIBUTE_UNUSED)
5688 {
5689 if (TARGET_ARCH32)
5690 {
5691 return ((type && AGGREGATE_TYPE_P (type))
5692 || mode == SCmode
5693 || GET_MODE_SIZE (mode) > 8);
5694 }
5695 else
5696 {
5697 return ((type && TREE_CODE (type) == ARRAY_TYPE)
5698 /* Consider complex values as aggregates, so care
5699 for CTImode and TCmode. */
5700 || GET_MODE_SIZE (mode) > 16
5701 || (type
5702 && AGGREGATE_TYPE_P (type)
5703 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16));
5704 }
5705 }
5706
5707 /* Handle the FUNCTION_ARG_ADVANCE macro.
5708 Update the data in CUM to advance over an argument
5709 of mode MODE and data type TYPE.
5710 TYPE is null for libcalls where that information may not be available. */
5711
5712 void
function_arg_advance(struct sparc_args * cum,enum machine_mode mode,tree type,int named)5713 function_arg_advance (struct sparc_args *cum, enum machine_mode mode,
5714 tree type, int named)
5715 {
5716 int slotno, regno, padding;
5717
5718 /* We pass 0 for incoming_p here, it doesn't matter. */
5719 slotno = function_arg_slotno (cum, mode, type, named, 0, ®no, &padding);
5720
5721 /* If register required leading padding, add it. */
5722 if (slotno != -1)
5723 cum->words += padding;
5724
5725 if (TARGET_ARCH32)
5726 {
5727 cum->words += (mode != BLKmode
5728 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5729 : ROUND_ADVANCE (int_size_in_bytes (type)));
5730 }
5731 else
5732 {
5733 if (type && AGGREGATE_TYPE_P (type))
5734 {
5735 int size = int_size_in_bytes (type);
5736
5737 if (size <= 8)
5738 ++cum->words;
5739 else if (size <= 16)
5740 cum->words += 2;
5741 else /* passed by reference */
5742 ++cum->words;
5743 }
5744 else
5745 {
5746 cum->words += (mode != BLKmode
5747 ? ROUND_ADVANCE (GET_MODE_SIZE (mode))
5748 : ROUND_ADVANCE (int_size_in_bytes (type)));
5749 }
5750 }
5751 }
5752
5753 /* Handle the FUNCTION_ARG_PADDING macro.
5754 For the 64 bit ABI structs are always stored left shifted in their
5755 argument slot. */
5756
5757 enum direction
function_arg_padding(enum machine_mode mode,tree type)5758 function_arg_padding (enum machine_mode mode, tree type)
5759 {
5760 if (TARGET_ARCH64 && type != 0 && AGGREGATE_TYPE_P (type))
5761 return upward;
5762
5763 /* Fall back to the default. */
5764 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5765 }
5766
5767 /* Handle FUNCTION_VALUE, FUNCTION_OUTGOING_VALUE, and LIBCALL_VALUE macros.
5768 For v9, function return values are subject to the same rules as arguments,
5769 except that up to 32-bytes may be returned in registers. */
5770
5771 rtx
function_value(tree type,enum machine_mode mode,int incoming_p)5772 function_value (tree type, enum machine_mode mode, int incoming_p)
5773 {
5774 int regno;
5775
5776 if (TARGET_ARCH64 && type)
5777 {
5778 int regbase = (incoming_p
5779 ? SPARC_OUTGOING_INT_ARG_FIRST
5780 : SPARC_INCOMING_INT_ARG_FIRST);
5781
5782 if (TREE_CODE (type) == RECORD_TYPE)
5783 {
5784 /* Structures up to 32 bytes in size are passed in registers,
5785 promoted to fp registers where possible. */
5786
5787 if (int_size_in_bytes (type) > 32)
5788 abort (); /* shouldn't get here */
5789
5790 return function_arg_record_value (type, mode, 0, 1, regbase);
5791 }
5792 else if (TREE_CODE (type) == UNION_TYPE)
5793 {
5794 HOST_WIDE_INT size = int_size_in_bytes (type);
5795
5796 if (size > 32)
5797 abort (); /* shouldn't get here */
5798
5799 return function_arg_union_value (size, mode, regbase);
5800 }
5801 else if (AGGREGATE_TYPE_P (type))
5802 {
5803 /* All other aggregate types are passed in an integer register
5804 in a mode corresponding to the size of the type. */
5805 HOST_WIDE_INT bytes = int_size_in_bytes (type);
5806
5807 if (bytes > 32)
5808 abort ();
5809
5810 mode = mode_for_size (bytes * BITS_PER_UNIT, MODE_INT, 0);
5811
5812 /* ??? We probably should have made the same ABI change in
5813 3.4.0 as the one we made for unions. The latter was
5814 required by the SCD though, while the former is not
5815 specified, so we favored compatibility and efficiency.
5816
5817 Now we're stuck for aggregates larger than 16 bytes,
5818 because OImode vanished in the meantime. Let's not
5819 try to be unduly clever, and simply follow the ABI
5820 for unions in that case. */
5821 if (mode == BLKmode)
5822 return function_arg_union_value (bytes, mode, regbase);
5823 }
5824 else if (GET_MODE_CLASS (mode) == MODE_INT
5825 && GET_MODE_SIZE (mode) < UNITS_PER_WORD)
5826 mode = word_mode;
5827 }
5828
5829 if (incoming_p)
5830 regno = BASE_RETURN_VALUE_REG (mode);
5831 else
5832 regno = BASE_OUTGOING_VALUE_REG (mode);
5833
5834 return gen_rtx_REG (mode, regno);
5835 }
5836
5837 /* Do what is necessary for `va_start'. We look at the current function
5838 to determine if stdarg or varargs is used and return the address of
5839 the first unnamed parameter. */
5840
5841 rtx
sparc_builtin_saveregs(void)5842 sparc_builtin_saveregs (void)
5843 {
5844 int first_reg = current_function_args_info.words;
5845 rtx address;
5846 int regno;
5847
5848 for (regno = first_reg; regno < NPARM_REGS (word_mode); regno++)
5849 emit_move_insn (gen_rtx_MEM (word_mode,
5850 gen_rtx_PLUS (Pmode,
5851 frame_pointer_rtx,
5852 GEN_INT (FIRST_PARM_OFFSET (0)
5853 + (UNITS_PER_WORD
5854 * regno)))),
5855 gen_rtx_REG (word_mode,
5856 BASE_INCOMING_ARG_REG (word_mode) + regno));
5857
5858 address = gen_rtx_PLUS (Pmode,
5859 frame_pointer_rtx,
5860 GEN_INT (FIRST_PARM_OFFSET (0)
5861 + UNITS_PER_WORD * first_reg));
5862
5863 return address;
5864 }
5865
5866 /* Implement `va_start' for varargs and stdarg. */
5867
5868 void
sparc_va_start(tree valist,rtx nextarg)5869 sparc_va_start (tree valist, rtx nextarg)
5870 {
5871 nextarg = expand_builtin_saveregs ();
5872 std_expand_builtin_va_start (valist, nextarg);
5873 }
5874
5875 /* Implement `va_arg'. */
5876
5877 rtx
sparc_va_arg(tree valist,tree type)5878 sparc_va_arg (tree valist, tree type)
5879 {
5880 HOST_WIDE_INT size, rsize, align;
5881 tree addr, incr;
5882 rtx addr_rtx;
5883 int indirect = 0;
5884
5885 /* Round up sizeof(type) to a word. */
5886 size = int_size_in_bytes (type);
5887 rsize = (size + UNITS_PER_WORD - 1) & -UNITS_PER_WORD;
5888 align = 0;
5889
5890 if (TARGET_ARCH64)
5891 {
5892 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD)
5893 align = 2 * UNITS_PER_WORD;
5894
5895 /* Consider complex values as aggregates, so care
5896 for CTImode and TCmode. */
5897 if ((unsigned HOST_WIDE_INT) size > 16)
5898 {
5899 indirect = 1;
5900 size = rsize = UNITS_PER_WORD;
5901 align = 0;
5902 }
5903 else if (AGGREGATE_TYPE_P (type))
5904 {
5905 /* SPARC-V9 ABI states that structures up to 16 bytes in size
5906 are given whole slots as needed. */
5907 if (size == 0)
5908 size = rsize = UNITS_PER_WORD;
5909 else
5910 size = rsize;
5911 }
5912 }
5913 else
5914 {
5915 if (AGGREGATE_TYPE_P (type)
5916 || TYPE_MODE (type) == SCmode
5917 || GET_MODE_SIZE (TYPE_MODE (type)) > 8)
5918 {
5919 indirect = 1;
5920 size = rsize = UNITS_PER_WORD;
5921 }
5922 }
5923
5924 incr = valist;
5925 if (align)
5926 {
5927 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5928 build_int_2 (align - 1, 0)));
5929 incr = fold (build (BIT_AND_EXPR, ptr_type_node, incr,
5930 build_int_2 (-align, -1)));
5931 }
5932
5933 addr = incr = save_expr (incr);
5934 if (BYTES_BIG_ENDIAN && size < rsize)
5935 {
5936 addr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5937 build_int_2 (rsize - size, 0)));
5938 }
5939 incr = fold (build (PLUS_EXPR, ptr_type_node, incr,
5940 build_int_2 (rsize, 0)));
5941
5942 incr = build (MODIFY_EXPR, ptr_type_node, valist, incr);
5943 TREE_SIDE_EFFECTS (incr) = 1;
5944 expand_expr (incr, const0_rtx, VOIDmode, EXPAND_NORMAL);
5945
5946 addr_rtx = expand_expr (addr, NULL, Pmode, EXPAND_NORMAL);
5947
5948 /* If the address isn't aligned properly for the type,
5949 we may need to copy to a temporary.
5950 FIXME: This is inefficient. Usually we can do this
5951 in registers. */
5952 if (align == 0
5953 && TYPE_ALIGN (type) > BITS_PER_WORD
5954 && !indirect)
5955 {
5956 /* FIXME: We really need to specify that the temporary is live
5957 for the whole function because expand_builtin_va_arg wants
5958 the alias set to be get_varargs_alias_set (), but in this
5959 case the alias set is that for TYPE and if the memory gets
5960 reused it will be reused with alias set TYPE. */
5961 rtx tmp = assign_temp (type, 0, 1, 0);
5962 rtx dest_addr;
5963
5964 addr_rtx = force_reg (Pmode, addr_rtx);
5965 addr_rtx = gen_rtx_MEM (BLKmode, addr_rtx);
5966 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5967 set_mem_align (addr_rtx, BITS_PER_WORD);
5968 tmp = shallow_copy_rtx (tmp);
5969 PUT_MODE (tmp, BLKmode);
5970 set_mem_alias_set (tmp, 0);
5971
5972 dest_addr = emit_block_move (tmp, addr_rtx, GEN_INT (rsize),
5973 BLOCK_OP_NORMAL);
5974 if (dest_addr != NULL_RTX)
5975 addr_rtx = dest_addr;
5976 else
5977 addr_rtx = XCEXP (tmp, 0, MEM);
5978 }
5979
5980 if (indirect)
5981 {
5982 addr_rtx = force_reg (Pmode, addr_rtx);
5983 addr_rtx = gen_rtx_MEM (Pmode, addr_rtx);
5984 set_mem_alias_set (addr_rtx, get_varargs_alias_set ());
5985 }
5986
5987 return addr_rtx;
5988 }
5989
5990 /* Return the string to output an unconditional branch to LABEL, which is
5991 the operand number of the label.
5992
5993 DEST is the destination insn (i.e. the label), INSN is the source. */
5994
5995 const char *
output_ubranch(rtx dest,int label,rtx insn)5996 output_ubranch (rtx dest, int label, rtx insn)
5997 {
5998 static char string[64];
5999 bool noop = false;
6000 char *p;
6001
6002 /* TurboSPARC is reported to have problems with
6003 with
6004 foo: b,a foo
6005 i.e. an empty loop with the annul bit set. The workaround is to use
6006 foo: b foo; nop
6007 instead. */
6008
6009 if (! TARGET_V9 && flag_delayed_branch
6010 && (INSN_ADDRESSES (INSN_UID (dest))
6011 == INSN_ADDRESSES (INSN_UID (insn))))
6012 {
6013 strcpy (string, "b\t");
6014 noop = true;
6015 }
6016 else
6017 {
6018 bool v9_form = false;
6019
6020 if (TARGET_V9 && INSN_ADDRESSES_SET_P ())
6021 {
6022 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6023 - INSN_ADDRESSES (INSN_UID (insn)));
6024 /* Leave some instructions for "slop". */
6025 if (delta >= -260000 && delta < 260000)
6026 v9_form = true;
6027 }
6028
6029 if (v9_form)
6030 strcpy (string, "ba%*,pt\t%%xcc, ");
6031 else
6032 strcpy (string, "b%*\t");
6033 }
6034
6035 p = strchr (string, '\0');
6036 *p++ = '%';
6037 *p++ = 'l';
6038 *p++ = '0' + label;
6039 *p++ = '%';
6040 if (noop)
6041 *p++ = '#';
6042 else
6043 *p++ = '(';
6044 *p = '\0';
6045
6046 return string;
6047 }
6048
6049 /* Return the string to output a conditional branch to LABEL, which is
6050 the operand number of the label. OP is the conditional expression.
6051 XEXP (OP, 0) is assumed to be a condition code register (integer or
6052 floating point) and its mode specifies what kind of comparison we made.
6053
6054 DEST is the destination insn (i.e. the label), INSN is the source.
6055
6056 REVERSED is nonzero if we should reverse the sense of the comparison.
6057
6058 ANNUL is nonzero if we should generate an annulling branch.
6059
6060 NOOP is nonzero if we have to follow this branch by a noop. */
6061
6062 char *
output_cbranch(rtx op,rtx dest,int label,int reversed,int annul,int noop,rtx insn)6063 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul,
6064 int noop, rtx insn)
6065 {
6066 static char string[50];
6067 enum rtx_code code = GET_CODE (op);
6068 rtx cc_reg = XEXP (op, 0);
6069 enum machine_mode mode = GET_MODE (cc_reg);
6070 const char *labelno, *branch;
6071 int spaces = 8, far;
6072 char *p;
6073
6074 /* v9 branches are limited to +-1MB. If it is too far away,
6075 change
6076
6077 bne,pt %xcc, .LC30
6078
6079 to
6080
6081 be,pn %xcc, .+12
6082 nop
6083 ba .LC30
6084
6085 and
6086
6087 fbne,a,pn %fcc2, .LC29
6088
6089 to
6090
6091 fbe,pt %fcc2, .+16
6092 nop
6093 ba .LC29 */
6094
6095 far = TARGET_V9 && (get_attr_length (insn) >= 3);
6096 if (reversed ^ far)
6097 {
6098 /* Reversal of FP compares takes care -- an ordered compare
6099 becomes an unordered compare and vice versa. */
6100 if (mode == CCFPmode || mode == CCFPEmode)
6101 code = reverse_condition_maybe_unordered (code);
6102 else
6103 code = reverse_condition (code);
6104 }
6105
6106 /* Start by writing the branch condition. */
6107 if (mode == CCFPmode || mode == CCFPEmode)
6108 {
6109 switch (code)
6110 {
6111 case NE:
6112 branch = "fbne";
6113 break;
6114 case EQ:
6115 branch = "fbe";
6116 break;
6117 case GE:
6118 branch = "fbge";
6119 break;
6120 case GT:
6121 branch = "fbg";
6122 break;
6123 case LE:
6124 branch = "fble";
6125 break;
6126 case LT:
6127 branch = "fbl";
6128 break;
6129 case UNORDERED:
6130 branch = "fbu";
6131 break;
6132 case ORDERED:
6133 branch = "fbo";
6134 break;
6135 case UNGT:
6136 branch = "fbug";
6137 break;
6138 case UNLT:
6139 branch = "fbul";
6140 break;
6141 case UNEQ:
6142 branch = "fbue";
6143 break;
6144 case UNGE:
6145 branch = "fbuge";
6146 break;
6147 case UNLE:
6148 branch = "fbule";
6149 break;
6150 case LTGT:
6151 branch = "fblg";
6152 break;
6153
6154 default:
6155 abort ();
6156 }
6157
6158 /* ??? !v9: FP branches cannot be preceded by another floating point
6159 insn. Because there is currently no concept of pre-delay slots,
6160 we can fix this only by always emitting a nop before a floating
6161 point branch. */
6162
6163 string[0] = '\0';
6164 if (! TARGET_V9)
6165 strcpy (string, "nop\n\t");
6166 strcat (string, branch);
6167 }
6168 else
6169 {
6170 switch (code)
6171 {
6172 case NE:
6173 branch = "bne";
6174 break;
6175 case EQ:
6176 branch = "be";
6177 break;
6178 case GE:
6179 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6180 branch = "bpos";
6181 else
6182 branch = "bge";
6183 break;
6184 case GT:
6185 branch = "bg";
6186 break;
6187 case LE:
6188 branch = "ble";
6189 break;
6190 case LT:
6191 if (mode == CC_NOOVmode || mode == CCX_NOOVmode)
6192 branch = "bneg";
6193 else
6194 branch = "bl";
6195 break;
6196 case GEU:
6197 branch = "bgeu";
6198 break;
6199 case GTU:
6200 branch = "bgu";
6201 break;
6202 case LEU:
6203 branch = "bleu";
6204 break;
6205 case LTU:
6206 branch = "blu";
6207 break;
6208
6209 default:
6210 abort ();
6211 }
6212 strcpy (string, branch);
6213 }
6214 spaces -= strlen (branch);
6215 p = strchr (string, '\0');
6216
6217 /* Now add the annulling, the label, and a possible noop. */
6218 if (annul && ! far)
6219 {
6220 strcpy (p, ",a");
6221 p += 2;
6222 spaces -= 2;
6223 }
6224
6225 if (TARGET_V9)
6226 {
6227 rtx note;
6228 int v8 = 0;
6229
6230 if (! far && insn && INSN_ADDRESSES_SET_P ())
6231 {
6232 int delta = (INSN_ADDRESSES (INSN_UID (dest))
6233 - INSN_ADDRESSES (INSN_UID (insn)));
6234 /* Leave some instructions for "slop". */
6235 if (delta < -260000 || delta >= 260000)
6236 v8 = 1;
6237 }
6238
6239 if (mode == CCFPmode || mode == CCFPEmode)
6240 {
6241 static char v9_fcc_labelno[] = "%%fccX, ";
6242 /* Set the char indicating the number of the fcc reg to use. */
6243 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0';
6244 labelno = v9_fcc_labelno;
6245 if (v8)
6246 {
6247 if (REGNO (cc_reg) == SPARC_FCC_REG)
6248 labelno = "";
6249 else
6250 abort ();
6251 }
6252 }
6253 else if (mode == CCXmode || mode == CCX_NOOVmode)
6254 {
6255 labelno = "%%xcc, ";
6256 if (v8)
6257 abort ();
6258 }
6259 else
6260 {
6261 labelno = "%%icc, ";
6262 if (v8)
6263 labelno = "";
6264 }
6265
6266 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6267 {
6268 strcpy (p,
6269 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6270 ? ",pt" : ",pn");
6271 p += 3;
6272 spaces -= 3;
6273 }
6274 }
6275 else
6276 labelno = "";
6277
6278 if (spaces > 0)
6279 *p++ = '\t';
6280 else
6281 *p++ = ' ';
6282 strcpy (p, labelno);
6283 p = strchr (p, '\0');
6284 if (far)
6285 {
6286 strcpy (p, ".+12\n\tnop\n\tb\t");
6287 if (annul || noop)
6288 p[3] = '6';
6289 p += 13;
6290 }
6291 *p++ = '%';
6292 *p++ = 'l';
6293 /* Set the char indicating the number of the operand containing the
6294 label_ref. */
6295 *p++ = label + '0';
6296 *p = '\0';
6297 if (noop)
6298 strcpy (p, "\n\tnop");
6299
6300 return string;
6301 }
6302
6303 /* Emit a library call comparison between floating point X and Y.
6304 COMPARISON is the rtl operator to compare with (EQ, NE, GT, etc.).
6305 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode
6306 values as arguments instead of the TFmode registers themselves,
6307 that's why we cannot call emit_float_lib_cmp. */
6308 void
sparc_emit_float_lib_cmp(rtx x,rtx y,enum rtx_code comparison)6309 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison)
6310 {
6311 const char *qpfunc;
6312 rtx slot0, slot1, result, tem, tem2;
6313 enum machine_mode mode;
6314
6315 switch (comparison)
6316 {
6317 case EQ:
6318 qpfunc = (TARGET_ARCH64) ? "_Qp_feq" : "_Q_feq";
6319 break;
6320
6321 case NE:
6322 qpfunc = (TARGET_ARCH64) ? "_Qp_fne" : "_Q_fne";
6323 break;
6324
6325 case GT:
6326 qpfunc = (TARGET_ARCH64) ? "_Qp_fgt" : "_Q_fgt";
6327 break;
6328
6329 case GE:
6330 qpfunc = (TARGET_ARCH64) ? "_Qp_fge" : "_Q_fge";
6331 break;
6332
6333 case LT:
6334 qpfunc = (TARGET_ARCH64) ? "_Qp_flt" : "_Q_flt";
6335 break;
6336
6337 case LE:
6338 qpfunc = (TARGET_ARCH64) ? "_Qp_fle" : "_Q_fle";
6339 break;
6340
6341 case ORDERED:
6342 case UNORDERED:
6343 case UNGT:
6344 case UNLT:
6345 case UNEQ:
6346 case UNGE:
6347 case UNLE:
6348 case LTGT:
6349 qpfunc = (TARGET_ARCH64) ? "_Qp_cmp" : "_Q_cmp";
6350 break;
6351
6352 default:
6353 abort();
6354 break;
6355 }
6356
6357 if (TARGET_ARCH64)
6358 {
6359 if (GET_CODE (x) != MEM)
6360 {
6361 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6362 emit_insn (gen_rtx_SET (VOIDmode, slot0, x));
6363 }
6364 else
6365 slot0 = x;
6366
6367 if (GET_CODE (y) != MEM)
6368 {
6369 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode), 0);
6370 emit_insn (gen_rtx_SET (VOIDmode, slot1, y));
6371 }
6372 else
6373 slot1 = y;
6374
6375 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6376 DImode, 2,
6377 XEXP (slot0, 0), Pmode,
6378 XEXP (slot1, 0), Pmode);
6379
6380 mode = DImode;
6381 }
6382 else
6383 {
6384 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, qpfunc), LCT_NORMAL,
6385 SImode, 2,
6386 x, TFmode, y, TFmode);
6387
6388 mode = SImode;
6389 }
6390
6391
6392 /* Immediately move the result of the libcall into a pseudo
6393 register so reload doesn't clobber the value if it needs
6394 the return register for a spill reg. */
6395 result = gen_reg_rtx (mode);
6396 emit_move_insn (result, hard_libcall_value (mode));
6397
6398 switch (comparison)
6399 {
6400 default:
6401 emit_cmp_insn (result, const0_rtx, NE, NULL_RTX, mode, 0);
6402 break;
6403 case ORDERED:
6404 case UNORDERED:
6405 emit_cmp_insn (result, GEN_INT(3), comparison == UNORDERED ? EQ : NE,
6406 NULL_RTX, mode, 0);
6407 break;
6408 case UNGT:
6409 case UNGE:
6410 emit_cmp_insn (result, const1_rtx,
6411 comparison == UNGT ? GT : NE, NULL_RTX, mode, 0);
6412 break;
6413 case UNLE:
6414 emit_cmp_insn (result, const2_rtx, NE, NULL_RTX, mode, 0);
6415 break;
6416 case UNLT:
6417 tem = gen_reg_rtx (mode);
6418 if (TARGET_ARCH32)
6419 emit_insn (gen_andsi3 (tem, result, const1_rtx));
6420 else
6421 emit_insn (gen_anddi3 (tem, result, const1_rtx));
6422 emit_cmp_insn (tem, const0_rtx, NE, NULL_RTX, mode, 0);
6423 break;
6424 case UNEQ:
6425 case LTGT:
6426 tem = gen_reg_rtx (mode);
6427 if (TARGET_ARCH32)
6428 emit_insn (gen_addsi3 (tem, result, const1_rtx));
6429 else
6430 emit_insn (gen_adddi3 (tem, result, const1_rtx));
6431 tem2 = gen_reg_rtx (mode);
6432 if (TARGET_ARCH32)
6433 emit_insn (gen_andsi3 (tem2, tem, const2_rtx));
6434 else
6435 emit_insn (gen_anddi3 (tem2, tem, const2_rtx));
6436 emit_cmp_insn (tem2, const0_rtx, comparison == UNEQ ? EQ : NE,
6437 NULL_RTX, mode, 0);
6438 break;
6439 }
6440 }
6441
6442 /* Generate an unsigned DImode to FP conversion. This is the same code
6443 optabs would emit if we didn't have TFmode patterns. */
6444
6445 void
sparc_emit_floatunsdi(rtx * operands)6446 sparc_emit_floatunsdi (rtx *operands)
6447 {
6448 rtx neglab, donelab, i0, i1, f0, in, out;
6449 enum machine_mode mode;
6450
6451 out = operands[0];
6452 in = force_reg (DImode, operands[1]);
6453 mode = GET_MODE (out);
6454 neglab = gen_label_rtx ();
6455 donelab = gen_label_rtx ();
6456 i0 = gen_reg_rtx (DImode);
6457 i1 = gen_reg_rtx (DImode);
6458 f0 = gen_reg_rtx (mode);
6459
6460 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab);
6461
6462 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_FLOAT (mode, in)));
6463 emit_jump_insn (gen_jump (donelab));
6464 emit_barrier ();
6465
6466 emit_label (neglab);
6467
6468 emit_insn (gen_lshrdi3 (i0, in, const1_rtx));
6469 emit_insn (gen_anddi3 (i1, in, const1_rtx));
6470 emit_insn (gen_iordi3 (i0, i0, i1));
6471 emit_insn (gen_rtx_SET (VOIDmode, f0, gen_rtx_FLOAT (mode, i0)));
6472 emit_insn (gen_rtx_SET (VOIDmode, out, gen_rtx_PLUS (mode, f0, f0)));
6473
6474 emit_label (donelab);
6475 }
6476
6477 /* Return the string to output a conditional branch to LABEL, testing
6478 register REG. LABEL is the operand number of the label; REG is the
6479 operand number of the reg. OP is the conditional expression. The mode
6480 of REG says what kind of comparison we made.
6481
6482 DEST is the destination insn (i.e. the label), INSN is the source.
6483
6484 REVERSED is nonzero if we should reverse the sense of the comparison.
6485
6486 ANNUL is nonzero if we should generate an annulling branch.
6487
6488 NOOP is nonzero if we have to follow this branch by a noop. */
6489
6490 char *
output_v9branch(rtx op,rtx dest,int reg,int label,int reversed,int annul,int noop,rtx insn)6491 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed,
6492 int annul, int noop, rtx insn)
6493 {
6494 static char string[50];
6495 enum rtx_code code = GET_CODE (op);
6496 enum machine_mode mode = GET_MODE (XEXP (op, 0));
6497 rtx note;
6498 int far;
6499 char *p;
6500
6501 /* branch on register are limited to +-128KB. If it is too far away,
6502 change
6503
6504 brnz,pt %g1, .LC30
6505
6506 to
6507
6508 brz,pn %g1, .+12
6509 nop
6510 ba,pt %xcc, .LC30
6511
6512 and
6513
6514 brgez,a,pn %o1, .LC29
6515
6516 to
6517
6518 brlz,pt %o1, .+16
6519 nop
6520 ba,pt %xcc, .LC29 */
6521
6522 far = get_attr_length (insn) >= 3;
6523
6524 /* If not floating-point or if EQ or NE, we can just reverse the code. */
6525 if (reversed ^ far)
6526 code = reverse_condition (code);
6527
6528 /* Only 64 bit versions of these instructions exist. */
6529 if (mode != DImode)
6530 abort ();
6531
6532 /* Start by writing the branch condition. */
6533
6534 switch (code)
6535 {
6536 case NE:
6537 strcpy (string, "brnz");
6538 break;
6539
6540 case EQ:
6541 strcpy (string, "brz");
6542 break;
6543
6544 case GE:
6545 strcpy (string, "brgez");
6546 break;
6547
6548 case LT:
6549 strcpy (string, "brlz");
6550 break;
6551
6552 case LE:
6553 strcpy (string, "brlez");
6554 break;
6555
6556 case GT:
6557 strcpy (string, "brgz");
6558 break;
6559
6560 default:
6561 abort ();
6562 }
6563
6564 p = strchr (string, '\0');
6565
6566 /* Now add the annulling, reg, label, and nop. */
6567 if (annul && ! far)
6568 {
6569 strcpy (p, ",a");
6570 p += 2;
6571 }
6572
6573 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX)))
6574 {
6575 strcpy (p,
6576 ((INTVAL (XEXP (note, 0)) >= REG_BR_PROB_BASE / 2) ^ far)
6577 ? ",pt" : ",pn");
6578 p += 3;
6579 }
6580
6581 *p = p < string + 8 ? '\t' : ' ';
6582 p++;
6583 *p++ = '%';
6584 *p++ = '0' + reg;
6585 *p++ = ',';
6586 *p++ = ' ';
6587 if (far)
6588 {
6589 int veryfar = 1, delta;
6590
6591 if (INSN_ADDRESSES_SET_P ())
6592 {
6593 delta = (INSN_ADDRESSES (INSN_UID (dest))
6594 - INSN_ADDRESSES (INSN_UID (insn)));
6595 /* Leave some instructions for "slop". */
6596 if (delta >= -260000 && delta < 260000)
6597 veryfar = 0;
6598 }
6599
6600 strcpy (p, ".+12\n\tnop\n\t");
6601 if (annul || noop)
6602 p[3] = '6';
6603 p += 11;
6604 if (veryfar)
6605 {
6606 strcpy (p, "b\t");
6607 p += 2;
6608 }
6609 else
6610 {
6611 strcpy (p, "ba,pt\t%%xcc, ");
6612 p += 13;
6613 }
6614 }
6615 *p++ = '%';
6616 *p++ = 'l';
6617 *p++ = '0' + label;
6618 *p = '\0';
6619
6620 if (noop)
6621 strcpy (p, "\n\tnop");
6622
6623 return string;
6624 }
6625
6626 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7].
6627 Such instructions cannot be used in the delay slot of return insn on v9.
6628 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts.
6629 */
6630
6631 static int
epilogue_renumber(register rtx * where,int test)6632 epilogue_renumber (register rtx *where, int test)
6633 {
6634 register const char *fmt;
6635 register int i;
6636 register enum rtx_code code;
6637
6638 if (*where == 0)
6639 return 0;
6640
6641 code = GET_CODE (*where);
6642
6643 switch (code)
6644 {
6645 case REG:
6646 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */
6647 return 1;
6648 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32)
6649 *where = gen_rtx (REG, GET_MODE (*where), OUTGOING_REGNO (REGNO(*where)));
6650 case SCRATCH:
6651 case CC0:
6652 case PC:
6653 case CONST_INT:
6654 case CONST_DOUBLE:
6655 return 0;
6656
6657 /* Do not replace the frame pointer with the stack pointer because
6658 it can cause the delayed instruction to load below the stack.
6659 This occurs when instructions like:
6660
6661 (set (reg/i:SI 24 %i0)
6662 (mem/f:SI (plus:SI (reg/f:SI 30 %fp)
6663 (const_int -20 [0xffffffec])) 0))
6664
6665 are in the return delayed slot. */
6666 case PLUS:
6667 if (GET_CODE (XEXP (*where, 0)) == REG
6668 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
6669 && (GET_CODE (XEXP (*where, 1)) != CONST_INT
6670 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
6671 return 1;
6672 break;
6673
6674 case MEM:
6675 if (SPARC_STACK_BIAS
6676 && GET_CODE (XEXP (*where, 0)) == REG
6677 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
6678 return 1;
6679 break;
6680
6681 default:
6682 break;
6683 }
6684
6685 fmt = GET_RTX_FORMAT (code);
6686
6687 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6688 {
6689 if (fmt[i] == 'E')
6690 {
6691 register int j;
6692 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
6693 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test))
6694 return 1;
6695 }
6696 else if (fmt[i] == 'e'
6697 && epilogue_renumber (&(XEXP (*where, i)), test))
6698 return 1;
6699 }
6700 return 0;
6701 }
6702
6703 /* Leaf functions and non-leaf functions have different needs. */
6704
6705 static const int
6706 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER;
6707
6708 static const int
6709 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER;
6710
6711 static const int *const reg_alloc_orders[] = {
6712 reg_leaf_alloc_order,
6713 reg_nonleaf_alloc_order};
6714
6715 void
order_regs_for_local_alloc(void)6716 order_regs_for_local_alloc (void)
6717 {
6718 static int last_order_nonleaf = 1;
6719
6720 if (regs_ever_live[15] != last_order_nonleaf)
6721 {
6722 last_order_nonleaf = !last_order_nonleaf;
6723 memcpy ((char *) reg_alloc_order,
6724 (const char *) reg_alloc_orders[last_order_nonleaf],
6725 FIRST_PSEUDO_REGISTER * sizeof (int));
6726 }
6727 }
6728
6729 /* Return 1 if REG and MEM are legitimate enough to allow the various
6730 mem<-->reg splits to be run. */
6731
6732 int
sparc_splitdi_legitimate(rtx reg,rtx mem)6733 sparc_splitdi_legitimate (rtx reg, rtx mem)
6734 {
6735 /* Punt if we are here by mistake. */
6736 if (! reload_completed)
6737 abort ();
6738
6739 /* We must have an offsettable memory reference. */
6740 if (! offsettable_memref_p (mem))
6741 return 0;
6742
6743 /* If we have legitimate args for ldd/std, we do not want
6744 the split to happen. */
6745 if ((REGNO (reg) % 2) == 0
6746 && mem_min_alignment (mem, 8))
6747 return 0;
6748
6749 /* Success. */
6750 return 1;
6751 }
6752
6753 /* Return 1 if x and y are some kind of REG and they refer to
6754 different hard registers. This test is guaranteed to be
6755 run after reload. */
6756
6757 int
sparc_absnegfloat_split_legitimate(rtx x,rtx y)6758 sparc_absnegfloat_split_legitimate (rtx x, rtx y)
6759 {
6760 if (GET_CODE (x) != REG)
6761 return 0;
6762 if (GET_CODE (y) != REG)
6763 return 0;
6764 if (REGNO (x) == REGNO (y))
6765 return 0;
6766 return 1;
6767 }
6768
6769 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1.
6770 This makes them candidates for using ldd and std insns.
6771
6772 Note reg1 and reg2 *must* be hard registers. */
6773
6774 int
registers_ok_for_ldd_peep(rtx reg1,rtx reg2)6775 registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
6776 {
6777 /* We might have been passed a SUBREG. */
6778 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
6779 return 0;
6780
6781 if (REGNO (reg1) % 2 != 0)
6782 return 0;
6783
6784 /* Integer ldd is deprecated in SPARC V9 */
6785 if (TARGET_V9 && REGNO (reg1) < 32)
6786 return 0;
6787
6788 return (REGNO (reg1) == REGNO (reg2) - 1);
6789 }
6790
6791 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in
6792 an ldd or std insn.
6793
6794 This can only happen when addr1 and addr2, the addresses in mem1
6795 and mem2, are consecutive memory locations (addr1 + 4 == addr2).
6796 addr1 must also be aligned on a 64-bit boundary.
6797
6798 Also iff dependent_reg_rtx is not null it should not be used to
6799 compute the address for mem1, i.e. we cannot optimize a sequence
6800 like:
6801 ld [%o0], %o0
6802 ld [%o0 + 4], %o1
6803 to
6804 ldd [%o0], %o0
6805 nor:
6806 ld [%g3 + 4], %g3
6807 ld [%g3], %g2
6808 to
6809 ldd [%g3], %g2
6810
6811 But, note that the transformation from:
6812 ld [%g2 + 4], %g3
6813 ld [%g2], %g2
6814 to
6815 ldd [%g2], %g2
6816 is perfectly fine. Thus, the peephole2 patterns always pass us
6817 the destination register of the first load, never the second one.
6818
6819 For stores we don't have a similar problem, so dependent_reg_rtx is
6820 NULL_RTX. */
6821
6822 int
mems_ok_for_ldd_peep(rtx mem1,rtx mem2,rtx dependent_reg_rtx)6823 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
6824 {
6825 rtx addr1, addr2;
6826 unsigned int reg1;
6827 HOST_WIDE_INT offset1;
6828
6829 /* The mems cannot be volatile. */
6830 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
6831 return 0;
6832
6833 /* MEM1 should be aligned on a 64-bit boundary. */
6834 if (MEM_ALIGN (mem1) < 64)
6835 return 0;
6836
6837 addr1 = XEXP (mem1, 0);
6838 addr2 = XEXP (mem2, 0);
6839
6840 /* Extract a register number and offset (if used) from the first addr. */
6841 if (GET_CODE (addr1) == PLUS)
6842 {
6843 /* If not a REG, return zero. */
6844 if (GET_CODE (XEXP (addr1, 0)) != REG)
6845 return 0;
6846 else
6847 {
6848 reg1 = REGNO (XEXP (addr1, 0));
6849 /* The offset must be constant! */
6850 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
6851 return 0;
6852 offset1 = INTVAL (XEXP (addr1, 1));
6853 }
6854 }
6855 else if (GET_CODE (addr1) != REG)
6856 return 0;
6857 else
6858 {
6859 reg1 = REGNO (addr1);
6860 /* This was a simple (mem (reg)) expression. Offset is 0. */
6861 offset1 = 0;
6862 }
6863
6864 /* Make sure the second address is a (mem (plus (reg) (const_int). */
6865 if (GET_CODE (addr2) != PLUS)
6866 return 0;
6867
6868 if (GET_CODE (XEXP (addr2, 0)) != REG
6869 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
6870 return 0;
6871
6872 if (reg1 != REGNO (XEXP (addr2, 0)))
6873 return 0;
6874
6875 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx))
6876 return 0;
6877
6878 /* The first offset must be evenly divisible by 8 to ensure the
6879 address is 64 bit aligned. */
6880 if (offset1 % 8 != 0)
6881 return 0;
6882
6883 /* The offset for the second addr must be 4 more than the first addr. */
6884 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4)
6885 return 0;
6886
6887 /* All the tests passed. addr1 and addr2 are valid for ldd and std
6888 instructions. */
6889 return 1;
6890 }
6891
6892 /* Return 1 if reg is a pseudo, or is the first register in
6893 a hard register pair. This makes it a candidate for use in
6894 ldd and std insns. */
6895
6896 int
register_ok_for_ldd(rtx reg)6897 register_ok_for_ldd (rtx reg)
6898 {
6899 /* We might have been passed a SUBREG. */
6900 if (GET_CODE (reg) != REG)
6901 return 0;
6902
6903 if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
6904 return (REGNO (reg) % 2 == 0);
6905 else
6906 return 1;
6907 }
6908
6909 /* Print operand X (an rtx) in assembler syntax to file FILE.
6910 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
6911 For `%' followed by punctuation, CODE is the punctuation and X is null. */
6912
6913 void
print_operand(FILE * file,rtx x,int code)6914 print_operand (FILE *file, rtx x, int code)
6915 {
6916 switch (code)
6917 {
6918 case '#':
6919 /* Output a 'nop' if there's nothing for the delay slot. */
6920 if (dbr_sequence_length () == 0)
6921 fputs ("\n\t nop", file);
6922 return;
6923 case '*':
6924 /* Output an annul flag if there's nothing for the delay slot and we
6925 are optimizing. This is always used with '(' below. */
6926 /* Sun OS 4.1.1 dbx can't handle an annulled unconditional branch;
6927 this is a dbx bug. So, we only do this when optimizing. */
6928 /* On UltraSPARC, a branch in a delay slot causes a pipeline flush.
6929 Always emit a nop in case the next instruction is a branch. */
6930 if (dbr_sequence_length () == 0
6931 && (optimize && (int)sparc_cpu < PROCESSOR_V9))
6932 fputs (",a", file);
6933 return;
6934 case '(':
6935 /* Output a 'nop' if there's nothing for the delay slot and we are
6936 not optimizing. This is always used with '*' above. */
6937 if (dbr_sequence_length () == 0
6938 && ! (optimize && (int)sparc_cpu < PROCESSOR_V9))
6939 fputs ("\n\t nop", file);
6940 return;
6941 case '_':
6942 /* Output the Embedded Medium/Anywhere code model base register. */
6943 fputs (EMBMEDANY_BASE_REG, file);
6944 return;
6945 case '@':
6946 /* Print out what we are using as the frame pointer. This might
6947 be %fp, or might be %sp+offset. */
6948 /* ??? What if offset is too big? Perhaps the caller knows it isn't? */
6949 fprintf (file, "%s+"HOST_WIDE_INT_PRINT_DEC, frame_base_name, frame_base_offset);
6950 return;
6951 case '&':
6952 /* Print some local dynamic TLS name. */
6953 assemble_name (file, get_some_local_dynamic_name ());
6954 return;
6955 case 'Y':
6956 /* Adjust the operand to take into account a RESTORE operation. */
6957 if (GET_CODE (x) == CONST_INT)
6958 break;
6959 else if (GET_CODE (x) != REG)
6960 output_operand_lossage ("invalid %%Y operand");
6961 else if (REGNO (x) < 8)
6962 fputs (reg_names[REGNO (x)], file);
6963 else if (REGNO (x) >= 24 && REGNO (x) < 32)
6964 fputs (reg_names[REGNO (x)-16], file);
6965 else
6966 output_operand_lossage ("invalid %%Y operand");
6967 return;
6968 case 'L':
6969 /* Print out the low order register name of a register pair. */
6970 if (WORDS_BIG_ENDIAN)
6971 fputs (reg_names[REGNO (x)+1], file);
6972 else
6973 fputs (reg_names[REGNO (x)], file);
6974 return;
6975 case 'H':
6976 /* Print out the high order register name of a register pair. */
6977 if (WORDS_BIG_ENDIAN)
6978 fputs (reg_names[REGNO (x)], file);
6979 else
6980 fputs (reg_names[REGNO (x)+1], file);
6981 return;
6982 case 'R':
6983 /* Print out the second register name of a register pair or quad.
6984 I.e., R (%o0) => %o1. */
6985 fputs (reg_names[REGNO (x)+1], file);
6986 return;
6987 case 'S':
6988 /* Print out the third register name of a register quad.
6989 I.e., S (%o0) => %o2. */
6990 fputs (reg_names[REGNO (x)+2], file);
6991 return;
6992 case 'T':
6993 /* Print out the fourth register name of a register quad.
6994 I.e., T (%o0) => %o3. */
6995 fputs (reg_names[REGNO (x)+3], file);
6996 return;
6997 case 'x':
6998 /* Print a condition code register. */
6999 if (REGNO (x) == SPARC_ICC_REG)
7000 {
7001 /* We don't handle CC[X]_NOOVmode because they're not supposed
7002 to occur here. */
7003 if (GET_MODE (x) == CCmode)
7004 fputs ("%icc", file);
7005 else if (GET_MODE (x) == CCXmode)
7006 fputs ("%xcc", file);
7007 else
7008 abort ();
7009 }
7010 else
7011 /* %fccN register */
7012 fputs (reg_names[REGNO (x)], file);
7013 return;
7014 case 'm':
7015 /* Print the operand's address only. */
7016 output_address (XEXP (x, 0));
7017 return;
7018 case 'r':
7019 /* In this case we need a register. Use %g0 if the
7020 operand is const0_rtx. */
7021 if (x == const0_rtx
7022 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x))))
7023 {
7024 fputs ("%g0", file);
7025 return;
7026 }
7027 else
7028 break;
7029
7030 case 'A':
7031 switch (GET_CODE (x))
7032 {
7033 case IOR: fputs ("or", file); break;
7034 case AND: fputs ("and", file); break;
7035 case XOR: fputs ("xor", file); break;
7036 default: output_operand_lossage ("invalid %%A operand");
7037 }
7038 return;
7039
7040 case 'B':
7041 switch (GET_CODE (x))
7042 {
7043 case IOR: fputs ("orn", file); break;
7044 case AND: fputs ("andn", file); break;
7045 case XOR: fputs ("xnor", file); break;
7046 default: output_operand_lossage ("invalid %%B operand");
7047 }
7048 return;
7049
7050 /* These are used by the conditional move instructions. */
7051 case 'c' :
7052 case 'C':
7053 {
7054 enum rtx_code rc = GET_CODE (x);
7055
7056 if (code == 'c')
7057 {
7058 enum machine_mode mode = GET_MODE (XEXP (x, 0));
7059 if (mode == CCFPmode || mode == CCFPEmode)
7060 rc = reverse_condition_maybe_unordered (GET_CODE (x));
7061 else
7062 rc = reverse_condition (GET_CODE (x));
7063 }
7064 switch (rc)
7065 {
7066 case NE: fputs ("ne", file); break;
7067 case EQ: fputs ("e", file); break;
7068 case GE: fputs ("ge", file); break;
7069 case GT: fputs ("g", file); break;
7070 case LE: fputs ("le", file); break;
7071 case LT: fputs ("l", file); break;
7072 case GEU: fputs ("geu", file); break;
7073 case GTU: fputs ("gu", file); break;
7074 case LEU: fputs ("leu", file); break;
7075 case LTU: fputs ("lu", file); break;
7076 case LTGT: fputs ("lg", file); break;
7077 case UNORDERED: fputs ("u", file); break;
7078 case ORDERED: fputs ("o", file); break;
7079 case UNLT: fputs ("ul", file); break;
7080 case UNLE: fputs ("ule", file); break;
7081 case UNGT: fputs ("ug", file); break;
7082 case UNGE: fputs ("uge", file); break;
7083 case UNEQ: fputs ("ue", file); break;
7084 default: output_operand_lossage (code == 'c'
7085 ? "invalid %%c operand"
7086 : "invalid %%C operand");
7087 }
7088 return;
7089 }
7090
7091 /* These are used by the movr instruction pattern. */
7092 case 'd':
7093 case 'D':
7094 {
7095 enum rtx_code rc = (code == 'd'
7096 ? reverse_condition (GET_CODE (x))
7097 : GET_CODE (x));
7098 switch (rc)
7099 {
7100 case NE: fputs ("ne", file); break;
7101 case EQ: fputs ("e", file); break;
7102 case GE: fputs ("gez", file); break;
7103 case LT: fputs ("lz", file); break;
7104 case LE: fputs ("lez", file); break;
7105 case GT: fputs ("gz", file); break;
7106 default: output_operand_lossage (code == 'd'
7107 ? "invalid %%d operand"
7108 : "invalid %%D operand");
7109 }
7110 return;
7111 }
7112
7113 case 'b':
7114 {
7115 /* Print a sign-extended character. */
7116 int i = trunc_int_for_mode (INTVAL (x), QImode);
7117 fprintf (file, "%d", i);
7118 return;
7119 }
7120
7121 case 'f':
7122 /* Operand must be a MEM; write its address. */
7123 if (GET_CODE (x) != MEM)
7124 output_operand_lossage ("invalid %%f operand");
7125 output_address (XEXP (x, 0));
7126 return;
7127
7128 case 's':
7129 {
7130 /* Print a sign-extended 32-bit value. */
7131 HOST_WIDE_INT i;
7132 if (GET_CODE(x) == CONST_INT)
7133 i = INTVAL (x);
7134 else if (GET_CODE(x) == CONST_DOUBLE)
7135 i = CONST_DOUBLE_LOW (x);
7136 else
7137 {
7138 output_operand_lossage ("invalid %%s operand");
7139 return;
7140 }
7141 i = trunc_int_for_mode (i, SImode);
7142 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i);
7143 return;
7144 }
7145
7146 case 0:
7147 /* Do nothing special. */
7148 break;
7149
7150 default:
7151 /* Undocumented flag. */
7152 output_operand_lossage ("invalid operand output code");
7153 }
7154
7155 if (GET_CODE (x) == REG)
7156 fputs (reg_names[REGNO (x)], file);
7157 else if (GET_CODE (x) == MEM)
7158 {
7159 fputc ('[', file);
7160 /* Poor Sun assembler doesn't understand absolute addressing. */
7161 if (CONSTANT_P (XEXP (x, 0)))
7162 fputs ("%g0+", file);
7163 output_address (XEXP (x, 0));
7164 fputc (']', file);
7165 }
7166 else if (GET_CODE (x) == HIGH)
7167 {
7168 fputs ("%hi(", file);
7169 output_addr_const (file, XEXP (x, 0));
7170 fputc (')', file);
7171 }
7172 else if (GET_CODE (x) == LO_SUM)
7173 {
7174 print_operand (file, XEXP (x, 0), 0);
7175 if (TARGET_CM_MEDMID)
7176 fputs ("+%l44(", file);
7177 else
7178 fputs ("+%lo(", file);
7179 output_addr_const (file, XEXP (x, 1));
7180 fputc (')', file);
7181 }
7182 else if (GET_CODE (x) == CONST_DOUBLE
7183 && (GET_MODE (x) == VOIDmode
7184 || GET_MODE_CLASS (GET_MODE (x)) == MODE_INT))
7185 {
7186 if (CONST_DOUBLE_HIGH (x) == 0)
7187 fprintf (file, "%u", (unsigned int) CONST_DOUBLE_LOW (x));
7188 else if (CONST_DOUBLE_HIGH (x) == -1
7189 && CONST_DOUBLE_LOW (x) < 0)
7190 fprintf (file, "%d", (int) CONST_DOUBLE_LOW (x));
7191 else
7192 output_operand_lossage ("long long constant not a valid immediate operand");
7193 }
7194 else if (GET_CODE (x) == CONST_DOUBLE)
7195 output_operand_lossage ("floating point constant not a valid immediate operand");
7196 else { output_addr_const (file, x); }
7197 }
7198
7199 /* Target hook for assembling integer objects. The sparc version has
7200 special handling for aligned DI-mode objects. */
7201
7202 static bool
sparc_assemble_integer(rtx x,unsigned int size,int aligned_p)7203 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
7204 {
7205 /* ??? We only output .xword's for symbols and only then in environments
7206 where the assembler can handle them. */
7207 if (aligned_p && size == 8
7208 && (GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE))
7209 {
7210 if (TARGET_V9)
7211 {
7212 assemble_integer_with_op ("\t.xword\t", x);
7213 return true;
7214 }
7215 else
7216 {
7217 assemble_aligned_integer (4, const0_rtx);
7218 assemble_aligned_integer (4, x);
7219 return true;
7220 }
7221 }
7222 return default_assemble_integer (x, size, aligned_p);
7223 }
7224
7225 /* Return the value of a code used in the .proc pseudo-op that says
7226 what kind of result this function returns. For non-C types, we pick
7227 the closest C type. */
7228
7229 #ifndef SHORT_TYPE_SIZE
7230 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2)
7231 #endif
7232
7233 #ifndef INT_TYPE_SIZE
7234 #define INT_TYPE_SIZE BITS_PER_WORD
7235 #endif
7236
7237 #ifndef LONG_TYPE_SIZE
7238 #define LONG_TYPE_SIZE BITS_PER_WORD
7239 #endif
7240
7241 #ifndef LONG_LONG_TYPE_SIZE
7242 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2)
7243 #endif
7244
7245 #ifndef FLOAT_TYPE_SIZE
7246 #define FLOAT_TYPE_SIZE BITS_PER_WORD
7247 #endif
7248
7249 #ifndef DOUBLE_TYPE_SIZE
7250 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7251 #endif
7252
7253 #ifndef LONG_DOUBLE_TYPE_SIZE
7254 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2)
7255 #endif
7256
7257 unsigned long
sparc_type_code(register tree type)7258 sparc_type_code (register tree type)
7259 {
7260 register unsigned long qualifiers = 0;
7261 register unsigned shift;
7262
7263 /* Only the first 30 bits of the qualifier are valid. We must refrain from
7264 setting more, since some assemblers will give an error for this. Also,
7265 we must be careful to avoid shifts of 32 bits or more to avoid getting
7266 unpredictable results. */
7267
7268 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type))
7269 {
7270 switch (TREE_CODE (type))
7271 {
7272 case ERROR_MARK:
7273 return qualifiers;
7274
7275 case ARRAY_TYPE:
7276 qualifiers |= (3 << shift);
7277 break;
7278
7279 case FUNCTION_TYPE:
7280 case METHOD_TYPE:
7281 qualifiers |= (2 << shift);
7282 break;
7283
7284 case POINTER_TYPE:
7285 case REFERENCE_TYPE:
7286 case OFFSET_TYPE:
7287 qualifiers |= (1 << shift);
7288 break;
7289
7290 case RECORD_TYPE:
7291 return (qualifiers | 8);
7292
7293 case UNION_TYPE:
7294 case QUAL_UNION_TYPE:
7295 return (qualifiers | 9);
7296
7297 case ENUMERAL_TYPE:
7298 return (qualifiers | 10);
7299
7300 case VOID_TYPE:
7301 return (qualifiers | 16);
7302
7303 case INTEGER_TYPE:
7304 /* If this is a range type, consider it to be the underlying
7305 type. */
7306 if (TREE_TYPE (type) != 0)
7307 break;
7308
7309 /* Carefully distinguish all the standard types of C,
7310 without messing up if the language is not C. We do this by
7311 testing TYPE_PRECISION and TREE_UNSIGNED. The old code used to
7312 look at both the names and the above fields, but that's redundant.
7313 Any type whose size is between two C types will be considered
7314 to be the wider of the two types. Also, we do not have a
7315 special code to use for "long long", so anything wider than
7316 long is treated the same. Note that we can't distinguish
7317 between "int" and "long" in this code if they are the same
7318 size, but that's fine, since neither can the assembler. */
7319
7320 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE)
7321 return (qualifiers | (TREE_UNSIGNED (type) ? 12 : 2));
7322
7323 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE)
7324 return (qualifiers | (TREE_UNSIGNED (type) ? 13 : 3));
7325
7326 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE)
7327 return (qualifiers | (TREE_UNSIGNED (type) ? 14 : 4));
7328
7329 else
7330 return (qualifiers | (TREE_UNSIGNED (type) ? 15 : 5));
7331
7332 case REAL_TYPE:
7333 /* If this is a range type, consider it to be the underlying
7334 type. */
7335 if (TREE_TYPE (type) != 0)
7336 break;
7337
7338 /* Carefully distinguish all the standard types of C,
7339 without messing up if the language is not C. */
7340
7341 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE)
7342 return (qualifiers | 6);
7343
7344 else
7345 return (qualifiers | 7);
7346
7347 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */
7348 /* ??? We need to distinguish between double and float complex types,
7349 but I don't know how yet because I can't reach this code from
7350 existing front-ends. */
7351 return (qualifiers | 7); /* Who knows? */
7352
7353 case CHAR_TYPE: /* GNU Pascal CHAR type. Not used in C. */
7354 case BOOLEAN_TYPE: /* GNU Fortran BOOLEAN type. */
7355 case FILE_TYPE: /* GNU Pascal FILE type. */
7356 case SET_TYPE: /* GNU Pascal SET type. */
7357 case LANG_TYPE: /* ? */
7358 return qualifiers;
7359
7360 default:
7361 abort (); /* Not a type! */
7362 }
7363 }
7364
7365 return qualifiers;
7366 }
7367
7368 /* Nested function support. */
7369
7370 /* Emit RTL insns to initialize the variable parts of a trampoline.
7371 FNADDR is an RTX for the address of the function's pure code.
7372 CXT is an RTX for the static chain value for the function.
7373
7374 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi
7375 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes
7376 (to store insns). This is a bit excessive. Perhaps a different
7377 mechanism would be better here.
7378
7379 Emit enough FLUSH insns to synchronize the data and instruction caches. */
7380
7381 void
sparc_initialize_trampoline(rtx tramp,rtx fnaddr,rtx cxt)7382 sparc_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7383 {
7384 /* SPARC 32-bit trampoline:
7385
7386 sethi %hi(fn), %g1
7387 sethi %hi(static), %g2
7388 jmp %g1+%lo(fn)
7389 or %g2, %lo(static), %g2
7390
7391 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii
7392 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii
7393 */
7394
7395 emit_move_insn
7396 (gen_rtx_MEM (SImode, plus_constant (tramp, 0)),
7397 expand_binop (SImode, ior_optab,
7398 expand_shift (RSHIFT_EXPR, SImode, fnaddr,
7399 size_int (10), 0, 1),
7400 GEN_INT (trunc_int_for_mode (0x03000000, SImode)),
7401 NULL_RTX, 1, OPTAB_DIRECT));
7402
7403 emit_move_insn
7404 (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7405 expand_binop (SImode, ior_optab,
7406 expand_shift (RSHIFT_EXPR, SImode, cxt,
7407 size_int (10), 0, 1),
7408 GEN_INT (trunc_int_for_mode (0x05000000, SImode)),
7409 NULL_RTX, 1, OPTAB_DIRECT));
7410
7411 emit_move_insn
7412 (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7413 expand_binop (SImode, ior_optab,
7414 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX),
7415 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)),
7416 NULL_RTX, 1, OPTAB_DIRECT));
7417
7418 emit_move_insn
7419 (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7420 expand_binop (SImode, ior_optab,
7421 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX),
7422 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)),
7423 NULL_RTX, 1, OPTAB_DIRECT));
7424
7425 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is
7426 aligned on a 16 byte boundary so one flush clears it all. */
7427 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
7428 if (sparc_cpu != PROCESSOR_ULTRASPARC
7429 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7430 emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
7431 plus_constant (tramp, 8)))));
7432
7433 /* Call __enable_execute_stack after writing onto the stack to make sure
7434 the stack address is accessible. */
7435 #ifdef ENABLE_EXECUTE_STACK
7436 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7437 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7438 #endif
7439
7440 }
7441
7442 /* The 64-bit version is simpler because it makes more sense to load the
7443 values as "immediate" data out of the trampoline. It's also easier since
7444 we can read the PC without clobbering a register. */
7445
7446 void
sparc64_initialize_trampoline(rtx tramp,rtx fnaddr,rtx cxt)7447 sparc64_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt)
7448 {
7449 /* SPARC 64-bit trampoline:
7450
7451 rd %pc, %g1
7452 ldx [%g1+24], %g5
7453 jmp %g5
7454 ldx [%g1+16], %g5
7455 +16 bytes data
7456 */
7457
7458 emit_move_insn (gen_rtx_MEM (SImode, tramp),
7459 GEN_INT (trunc_int_for_mode (0x83414000, SImode)));
7460 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 4)),
7461 GEN_INT (trunc_int_for_mode (0xca586018, SImode)));
7462 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 8)),
7463 GEN_INT (trunc_int_for_mode (0x81c14000, SImode)));
7464 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (tramp, 12)),
7465 GEN_INT (trunc_int_for_mode (0xca586010, SImode)));
7466 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 16)), cxt);
7467 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (tramp, 24)), fnaddr);
7468 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
7469
7470 if (sparc_cpu != PROCESSOR_ULTRASPARC
7471 && sparc_cpu != PROCESSOR_ULTRASPARC3)
7472 emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
7473
7474 /* Call __enable_execute_stack after writing onto the stack to make sure
7475 the stack address is accessible. */
7476 #ifdef ENABLE_EXECUTE_STACK
7477 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"),
7478 LCT_NORMAL, VOIDmode, 1, tramp, Pmode);
7479 #endif
7480 }
7481
7482 /* Subroutines to support a flat (single) register window calling
7483 convention. */
7484
7485 /* Single-register window sparc stack frames look like:
7486
7487 Before call After call
7488 +-----------------------+ +-----------------------+
7489 high | | | |
7490 mem | caller's temps. | | caller's temps. |
7491 | | | |
7492 +-----------------------+ +-----------------------+
7493 | | | |
7494 | arguments on stack. | | arguments on stack. |
7495 | | | |
7496 +-----------------------+FP+92->+-----------------------+
7497 | 6 words to save | | 6 words to save |
7498 | arguments passed | | arguments passed |
7499 | in registers, even | | in registers, even |
7500 | if not passed. | | if not passed. |
7501 SP+68->+-----------------------+FP+68->+-----------------------+
7502 | 1 word struct addr | | 1 word struct addr |
7503 +-----------------------+FP+64->+-----------------------+
7504 | | | |
7505 | 16 word reg save area | | 16 word reg save area |
7506 | | | |
7507 SP->+-----------------------+ FP->+-----------------------+
7508 | 4 word area for |
7509 | fp/alu reg moves |
7510 FP-16->+-----------------------+
7511 | |
7512 | local variables |
7513 | |
7514 +-----------------------+
7515 | |
7516 | fp register save |
7517 | |
7518 +-----------------------+
7519 | |
7520 | gp register save |
7521 | |
7522 +-----------------------+
7523 | |
7524 | alloca allocations |
7525 | |
7526 +-----------------------+
7527 | |
7528 | arguments on stack |
7529 | |
7530 SP+92->+-----------------------+
7531 | 6 words to save |
7532 | arguments passed |
7533 | in registers, even |
7534 low | if not passed. |
7535 memory SP+68->+-----------------------+
7536 | 1 word struct addr |
7537 SP+64->+-----------------------+
7538 | |
7539 I 16 word reg save area |
7540 | |
7541 SP->+-----------------------+ */
7542
7543 /* Structure to be filled in by sparc_flat_compute_frame_size with register
7544 save masks, and offsets for the current function. */
7545
7546 struct sparc_frame_info
7547 {
7548 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7549 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7550 int args_size; /* # bytes that outgoing arguments take up. */
7551 int extra_size; /* # bytes of extra gunk. */
7552 int gp_reg_size; /* # bytes needed to store gp regs. */
7553 int fp_reg_size; /* # bytes needed to store fp regs. */
7554 unsigned long gmask; /* Mask of saved gp registers. */
7555 unsigned long fmask; /* Mask of saved fp registers. */
7556 int reg_offset; /* Offset from new sp to store regs. */
7557 int initialized; /* Nonzero if frame size already calculated. */
7558 };
7559
7560 /* Current frame information calculated by sparc_flat_compute_frame_size. */
7561 struct sparc_frame_info current_frame_info;
7562
7563 /* Zero structure to initialize current_frame_info. */
7564 struct sparc_frame_info zero_frame_info;
7565
7566 #define RETURN_ADDR_REGNUM 15
7567 #define HARD_FRAME_POINTER_MASK (1 << (HARD_FRAME_POINTER_REGNUM))
7568 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM))
7569
7570 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
7571
7572 static bool
sparc_flat_must_save_register_p(int regno)7573 sparc_flat_must_save_register_p (int regno)
7574 {
7575 /* General case: call-saved registers live at some point. */
7576 if (!call_used_regs[regno] && regs_ever_live[regno])
7577 return true;
7578
7579 /* Frame pointer register (%i7) if needed. */
7580 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed)
7581 return true;
7582
7583 /* PIC register (%l7) if needed. */
7584 if (regno == (int) PIC_OFFSET_TABLE_REGNUM
7585 && flag_pic && current_function_uses_pic_offset_table)
7586 return true;
7587
7588 /* Return address register (%o7) if needed. */
7589 if (regno == RETURN_ADDR_REGNUM
7590 && (regs_ever_live[RETURN_ADDR_REGNUM]
7591 /* When the PIC offset table is used, the PIC register
7592 is set by using a bare call that clobbers %o7. */
7593 || (flag_pic && current_function_uses_pic_offset_table)))
7594 return true;
7595
7596 return false;
7597 }
7598
7599 /* Return the bytes needed to compute the frame pointer from the current
7600 stack pointer. */
7601
7602 HOST_WIDE_INT
sparc_flat_compute_frame_size(HOST_WIDE_INT size)7603 sparc_flat_compute_frame_size (HOST_WIDE_INT size)
7604 /* # of var. bytes allocated. */
7605 {
7606 int regno;
7607 HOST_WIDE_INT total_size; /* # bytes that the entire frame takes up. */
7608 HOST_WIDE_INT var_size; /* # bytes that variables take up. */
7609 int args_size; /* # bytes that outgoing arguments take up. */
7610 int extra_size; /* # extra bytes. */
7611 int gp_reg_size; /* # bytes needed to store gp regs. */
7612 int fp_reg_size; /* # bytes needed to store fp regs. */
7613 unsigned long gmask; /* Mask of saved gp registers. */
7614 unsigned long fmask; /* Mask of saved fp registers. */
7615 int reg_offset; /* Offset to register save area. */
7616 int need_aligned_p; /* 1 if need the save area 8 byte aligned. */
7617
7618 /* This is the size of the 16 word reg save area, 1 word struct addr
7619 area, and 4 word fp/alu register copy area. */
7620 extra_size = -STARTING_FRAME_OFFSET + FIRST_PARM_OFFSET(0);
7621 var_size = size;
7622 gp_reg_size = 0;
7623 fp_reg_size = 0;
7624 gmask = 0;
7625 fmask = 0;
7626 reg_offset = 0;
7627 need_aligned_p = 0;
7628
7629 args_size = 0;
7630 if (!leaf_function_p ())
7631 {
7632 /* Also include the size needed for the 6 parameter registers. */
7633 args_size = current_function_outgoing_args_size + 24;
7634 }
7635 total_size = var_size + args_size;
7636
7637 /* Calculate space needed for gp registers. */
7638 for (regno = 1; regno <= 31; regno++)
7639 {
7640 if (sparc_flat_must_save_register_p (regno))
7641 {
7642 /* If we need to save two regs in a row, ensure there's room to bump
7643 up the address to align it to a doubleword boundary. */
7644 if ((regno & 0x1) == 0 && sparc_flat_must_save_register_p (regno+1))
7645 {
7646 if (gp_reg_size % 8 != 0)
7647 gp_reg_size += 4;
7648 gp_reg_size += 2 * UNITS_PER_WORD;
7649 gmask |= 3 << regno;
7650 regno++;
7651 need_aligned_p = 1;
7652 }
7653 else
7654 {
7655 gp_reg_size += UNITS_PER_WORD;
7656 gmask |= 1 << regno;
7657 }
7658 }
7659 }
7660
7661 /* Calculate space needed for fp registers. */
7662 for (regno = 32; regno <= 63; regno++)
7663 {
7664 if (regs_ever_live[regno] && !call_used_regs[regno])
7665 {
7666 fp_reg_size += UNITS_PER_WORD;
7667 fmask |= 1 << (regno - 32);
7668 }
7669 }
7670
7671 if (gmask || fmask)
7672 {
7673 int n;
7674 reg_offset = FIRST_PARM_OFFSET(0) + args_size;
7675 /* Ensure save area is 8 byte aligned if we need it. */
7676 n = reg_offset % 8;
7677 if (need_aligned_p && n != 0)
7678 {
7679 total_size += 8 - n;
7680 reg_offset += 8 - n;
7681 }
7682 total_size += gp_reg_size + fp_reg_size;
7683 }
7684
7685 /* If we must allocate a stack frame at all, we must also allocate
7686 room for register window spillage, so as to be binary compatible
7687 with libraries and operating systems that do not use -mflat. */
7688 if (total_size > 0)
7689 total_size += extra_size;
7690 else
7691 extra_size = 0;
7692
7693 total_size = SPARC_STACK_ALIGN (total_size);
7694
7695 /* Save other computed information. */
7696 current_frame_info.total_size = total_size;
7697 current_frame_info.var_size = var_size;
7698 current_frame_info.args_size = args_size;
7699 current_frame_info.extra_size = extra_size;
7700 current_frame_info.gp_reg_size = gp_reg_size;
7701 current_frame_info.fp_reg_size = fp_reg_size;
7702 current_frame_info.gmask = gmask;
7703 current_frame_info.fmask = fmask;
7704 current_frame_info.reg_offset = reg_offset;
7705 current_frame_info.initialized = reload_completed;
7706
7707 /* Ok, we're done. */
7708 return total_size;
7709 }
7710
7711 /* Save/restore registers in GMASK and FMASK at register BASE_REG plus offset
7712 OFFSET.
7713
7714 BASE_REG must be 8 byte aligned. This allows us to test OFFSET for
7715 appropriate alignment and use DOUBLEWORD_OP when we can. We assume
7716 [BASE_REG+OFFSET] will always be a valid address.
7717
7718 WORD_OP is either "st" for save, "ld" for restore.
7719 DOUBLEWORD_OP is either "std" for save, "ldd" for restore. */
7720
7721 static void
sparc_flat_save_restore(FILE * file,const char * base_reg,int offset,unsigned long gmask,unsigned long fmask,const char * word_op,const char * doubleword_op,HOST_WIDE_INT base_offset)7722 sparc_flat_save_restore (FILE *file, const char *base_reg, int offset,
7723 unsigned long gmask, unsigned long fmask,
7724 const char *word_op, const char *doubleword_op,
7725 HOST_WIDE_INT base_offset)
7726 {
7727 int regno;
7728
7729 if (gmask == 0 && fmask == 0)
7730 return;
7731
7732 /* Save registers starting from high to low. We've already saved the
7733 previous frame pointer and previous return address for the debugger's
7734 sake. The debugger allows us to not need a nop in the epilog if at least
7735 one register is reloaded in addition to return address. */
7736
7737 if (gmask)
7738 {
7739 for (regno = 1; regno <= 31; regno++)
7740 {
7741 if ((gmask & (1L << regno)) != 0)
7742 {
7743 if ((regno & 0x1) == 0 && ((gmask & (1L << (regno+1))) != 0))
7744 {
7745 /* We can save two registers in a row. If we're not at a
7746 double word boundary, move to one.
7747 sparc_flat_compute_frame_size ensures there's room to do
7748 this. */
7749 if (offset % 8 != 0)
7750 offset += UNITS_PER_WORD;
7751
7752 if (word_op[0] == 's')
7753 {
7754 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7755 doubleword_op, reg_names[regno],
7756 base_reg, offset);
7757 if (dwarf2out_do_frame ())
7758 {
7759 char *l = dwarf2out_cfi_label ();
7760 dwarf2out_reg_save (l, regno, offset + base_offset);
7761 dwarf2out_reg_save
7762 (l, regno+1, offset+base_offset + UNITS_PER_WORD);
7763 }
7764 }
7765 else
7766 fprintf (file, "\t%s\t[%s+%d], %s\n",
7767 doubleword_op, base_reg, offset,
7768 reg_names[regno]);
7769
7770 offset += 2 * UNITS_PER_WORD;
7771 regno++;
7772 }
7773 else
7774 {
7775 if (word_op[0] == 's')
7776 {
7777 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7778 word_op, reg_names[regno],
7779 base_reg, offset);
7780 if (dwarf2out_do_frame ())
7781 dwarf2out_reg_save ("", regno, offset + base_offset);
7782 }
7783 else
7784 fprintf (file, "\t%s\t[%s+%d], %s\n",
7785 word_op, base_reg, offset, reg_names[regno]);
7786
7787 offset += UNITS_PER_WORD;
7788 }
7789 }
7790 }
7791 }
7792
7793 if (fmask)
7794 {
7795 for (regno = 32; regno <= 63; regno++)
7796 {
7797 if ((fmask & (1L << (regno - 32))) != 0)
7798 {
7799 if (word_op[0] == 's')
7800 {
7801 fprintf (file, "\t%s\t%s, [%s+%d]\n",
7802 word_op, reg_names[regno],
7803 base_reg, offset);
7804 if (dwarf2out_do_frame ())
7805 dwarf2out_reg_save ("", regno, offset + base_offset);
7806 }
7807 else
7808 fprintf (file, "\t%s\t[%s+%d], %s\n",
7809 word_op, base_reg, offset, reg_names[regno]);
7810
7811 offset += UNITS_PER_WORD;
7812 }
7813 }
7814 }
7815 }
7816
7817 /* Set up the stack and frame (if desired) for the function. */
7818
7819 static void
sparc_flat_function_prologue(FILE * file,HOST_WIDE_INT size)7820 sparc_flat_function_prologue (FILE *file, HOST_WIDE_INT size)
7821 {
7822 const char *sp_str = reg_names[STACK_POINTER_REGNUM];
7823 unsigned long gmask = current_frame_info.gmask;
7824
7825 sparc_output_scratch_registers (file);
7826
7827 /* This is only for the human reader. */
7828 fprintf (file, "\t%s#PROLOGUE# 0\n", ASM_COMMENT_START);
7829 fprintf (file, "\t%s# vars= "HOST_WIDE_INT_PRINT_DEC", "
7830 "regs= %d/%d, args= %d, extra= %d\n",
7831 ASM_COMMENT_START,
7832 current_frame_info.var_size,
7833 current_frame_info.gp_reg_size / 4,
7834 current_frame_info.fp_reg_size / 4,
7835 current_function_outgoing_args_size,
7836 current_frame_info.extra_size);
7837
7838 size = SPARC_STACK_ALIGN (size);
7839 size = (! current_frame_info.initialized
7840 ? sparc_flat_compute_frame_size (size)
7841 : current_frame_info.total_size);
7842
7843 /* These cases shouldn't happen. Catch them now. */
7844 if (size == 0 && (gmask || current_frame_info.fmask))
7845 abort ();
7846
7847 /* Allocate our stack frame by decrementing %sp.
7848 At present, the only algorithm gdb can use to determine if this is a
7849 flat frame is if we always set %i7 if we set %sp. This can be optimized
7850 in the future by putting in some sort of debugging information that says
7851 this is a `flat' function. However, there is still the case of debugging
7852 code without such debugging information (including cases where most fns
7853 have such info, but there is one that doesn't). So, always do this now
7854 so we don't get a lot of code out there that gdb can't handle.
7855 If the frame pointer isn't needn't then that's ok - gdb won't be able to
7856 distinguish us from a non-flat function but there won't (and shouldn't)
7857 be any differences anyway. The return pc is saved (if necessary) right
7858 after %i7 so gdb won't have to look too far to find it. */
7859 if (size > 0)
7860 {
7861 int reg_offset = current_frame_info.reg_offset;
7862 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
7863 static const char *const t1_str = "%g1";
7864
7865 /* Things get a little tricky if local variables take up more than ~4096
7866 bytes and outgoing arguments take up more than ~4096 bytes. When that
7867 happens, the register save area can't be accessed from either end of
7868 the frame. Handle this by decrementing %sp to the start of the gp
7869 register save area, save the regs, update %i7, and then set %sp to its
7870 final value. Given that we only have one scratch register to play
7871 with it is the cheapest solution, and it helps gdb out as it won't
7872 slow down recognition of flat functions.
7873 Don't change the order of insns emitted here without checking with
7874 the gdb folk first. */
7875
7876 /* Is the entire register save area offsettable from %sp? */
7877 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
7878 {
7879 if (size <= 4096)
7880 {
7881 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7882 sp_str, size, sp_str);
7883 if (gmask & HARD_FRAME_POINTER_MASK)
7884 {
7885 fprintf (file, "\tst\t%s, [%s+%d]\n",
7886 fp_str, sp_str, reg_offset);
7887 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7888 "\t%s# set up frame pointer\n",
7889 sp_str, size, fp_str, ASM_COMMENT_START);
7890 reg_offset += 4;
7891 }
7892 }
7893 else
7894 {
7895 build_big_number (file, size, t1_str);
7896 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7897 if (gmask & HARD_FRAME_POINTER_MASK)
7898 {
7899 fprintf (file, "\tst\t%s, [%s+%d]\n",
7900 fp_str, sp_str, reg_offset);
7901 fprintf (file, "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7902 sp_str, t1_str, fp_str, ASM_COMMENT_START);
7903 reg_offset += 4;
7904 }
7905 }
7906 if (dwarf2out_do_frame ())
7907 {
7908 char *l = dwarf2out_cfi_label ();
7909 if (gmask & HARD_FRAME_POINTER_MASK)
7910 {
7911 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7912 reg_offset - 4 - size);
7913 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7914 }
7915 else
7916 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size);
7917 }
7918 if (gmask & RETURN_ADDR_MASK)
7919 {
7920 fprintf (file, "\tst\t%s, [%s+%d]\n",
7921 reg_names[RETURN_ADDR_REGNUM], sp_str, reg_offset);
7922 if (dwarf2out_do_frame ())
7923 dwarf2out_return_save ("", reg_offset - size);
7924 reg_offset += 4;
7925 }
7926 sparc_flat_save_restore (file, sp_str, reg_offset,
7927 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7928 current_frame_info.fmask,
7929 "st", "std", -size);
7930 }
7931 else
7932 {
7933 /* Subtract %sp in two steps, but make sure there is always a
7934 64-byte register save area, and %sp is properly aligned. */
7935
7936 /* Amount to decrement %sp by, the first time. */
7937 HOST_WIDE_INT size1 = ((size - reg_offset + 64) + 15) & -16;
7938
7939 /* Amount to decrement %sp by, the second time. */
7940 HOST_WIDE_INT size2 = size - size1;
7941
7942 /* Offset to register save area from %sp after first decrement. */
7943 int offset = (int)(size1 - (size - reg_offset));
7944
7945 if (size1 <= 4096)
7946 {
7947 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
7948 sp_str, size1, sp_str);
7949 if (gmask & HARD_FRAME_POINTER_MASK)
7950 {
7951 fprintf (file, "\tst\t%s, [%s+%d]\n"
7952 "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
7953 "\t%s# set up frame pointer\n",
7954 fp_str, sp_str, offset, sp_str, size1,
7955 fp_str, ASM_COMMENT_START);
7956 offset += 4;
7957 }
7958 }
7959 else
7960 {
7961 build_big_number (file, size1, t1_str);
7962 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
7963 if (gmask & HARD_FRAME_POINTER_MASK)
7964 {
7965 fprintf (file, "\tst\t%s, [%s+%d]\n"
7966 "\tadd\t%s, %s, %s\t%s# set up frame pointer\n",
7967 fp_str, sp_str, offset, sp_str, t1_str,
7968 fp_str, ASM_COMMENT_START);
7969 offset += 4;
7970 }
7971 }
7972 if (dwarf2out_do_frame ())
7973 {
7974 char *l = dwarf2out_cfi_label ();
7975 if (gmask & HARD_FRAME_POINTER_MASK)
7976 {
7977 dwarf2out_reg_save (l, HARD_FRAME_POINTER_REGNUM,
7978 offset - 4 - size1);
7979 dwarf2out_def_cfa (l, HARD_FRAME_POINTER_REGNUM, 0);
7980 }
7981 else
7982 dwarf2out_def_cfa (l, STACK_POINTER_REGNUM, size1);
7983 }
7984 if (gmask & RETURN_ADDR_MASK)
7985 {
7986 fprintf (file, "\tst\t%s, [%s+%d]\n",
7987 reg_names[RETURN_ADDR_REGNUM], sp_str, offset);
7988 if (dwarf2out_do_frame ())
7989 /* offset - size1 == reg_offset - size
7990 if reg_offset were updated above like offset. */
7991 dwarf2out_return_save ("", offset - size1);
7992 offset += 4;
7993 }
7994 sparc_flat_save_restore (file, sp_str, offset,
7995 gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
7996 current_frame_info.fmask,
7997 "st", "std", -size1);
7998 if (size2 <= 4096)
7999 fprintf (file, "\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
8000 sp_str, size2, sp_str);
8001 else
8002 {
8003 build_big_number (file, size2, t1_str);
8004 fprintf (file, "\tsub\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8005 }
8006 if (dwarf2out_do_frame ())
8007 if (! (gmask & HARD_FRAME_POINTER_MASK))
8008 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, size);
8009 }
8010 }
8011
8012 fprintf (file, "\t%s#PROLOGUE# 1\n", ASM_COMMENT_START);
8013 }
8014
8015 /* Do any necessary cleanup after a function to restore stack, frame,
8016 and regs. */
8017
8018 static void
sparc_flat_function_epilogue(FILE * file,HOST_WIDE_INT size)8019 sparc_flat_function_epilogue (FILE *file, HOST_WIDE_INT size)
8020 {
8021 rtx epilogue_delay = current_function_epilogue_delay_list;
8022 int noepilogue = FALSE;
8023
8024 /* This is only for the human reader. */
8025 fprintf (file, "\t%s#EPILOGUE#\n", ASM_COMMENT_START);
8026
8027 /* The epilogue does not depend on any registers, but the stack
8028 registers, so we assume that if we have 1 pending nop, it can be
8029 ignored, and 2 it must be filled (2 nops occur for integer
8030 multiply and divide). */
8031
8032 size = SPARC_STACK_ALIGN (size);
8033 size = (!current_frame_info.initialized
8034 ? sparc_flat_compute_frame_size (size)
8035 : current_frame_info.total_size);
8036
8037 if (size == 0 && epilogue_delay == 0)
8038 {
8039 rtx insn = get_last_insn ();
8040
8041 /* If the last insn was a BARRIER, we don't have to write any code
8042 because a jump (aka return) was put there. */
8043 if (GET_CODE (insn) == NOTE)
8044 insn = prev_nonnote_insn (insn);
8045 if (insn && GET_CODE (insn) == BARRIER)
8046 noepilogue = TRUE;
8047 }
8048
8049 if (!noepilogue)
8050 {
8051 int reg_offset = current_frame_info.reg_offset;
8052 int reg_offset1;
8053 const char *const sp_str = reg_names[STACK_POINTER_REGNUM];
8054 const char *const fp_str = reg_names[HARD_FRAME_POINTER_REGNUM];
8055 static const char *const t1_str = "%g1";
8056
8057 /* In the reload sequence, we don't need to fill the load delay
8058 slots for most of the loads, also see if we can fill the final
8059 delay slot if not otherwise filled by the reload sequence. */
8060
8061 if (size > 4096)
8062 build_big_number (file, size, t1_str);
8063
8064 if (frame_pointer_needed)
8065 {
8066 if (size > 4096)
8067 fprintf (file,"\tsub\t%s, %s, %s\t\t%s# sp not trusted here\n",
8068 fp_str, t1_str, sp_str, ASM_COMMENT_START);
8069 else
8070 fprintf (file,"\tadd\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s"
8071 "\t\t%s# sp not trusted here\n",
8072 fp_str, size, sp_str, ASM_COMMENT_START);
8073 }
8074
8075 /* Is the entire register save area offsettable from %sp? */
8076 if (reg_offset < 4096 - 64 * UNITS_PER_WORD)
8077 {
8078 reg_offset1 = 0;
8079 }
8080 else
8081 {
8082 /* Restore %sp in two steps, but make sure there is always a
8083 64-byte register save area, and %sp is properly aligned. */
8084
8085 /* Amount to increment %sp by, the first time. */
8086 reg_offset1 = ((reg_offset - 64 - 16) + 15) & -16;
8087
8088 /* Offset to register save area from %sp. */
8089 reg_offset = reg_offset1 - reg_offset;
8090
8091 if (reg_offset1 > 4096)
8092 {
8093 build_big_number (file, reg_offset1, t1_str);
8094 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8095 }
8096 else
8097 fprintf (file, "\tsub\t%s, -%d, %s\n", sp_str, reg_offset1, sp_str);
8098 }
8099
8100 /* We must restore the frame pointer and return address reg first
8101 because they are treated specially by the prologue output code. */
8102 if (current_frame_info.gmask & HARD_FRAME_POINTER_MASK)
8103 {
8104 fprintf (file, "\tld\t[%s+%d], %s\n",
8105 sp_str, reg_offset, fp_str);
8106 reg_offset += 4;
8107 }
8108 if (current_frame_info.gmask & RETURN_ADDR_MASK)
8109 {
8110 fprintf (file, "\tld\t[%s+%d], %s\n",
8111 sp_str, reg_offset, reg_names[RETURN_ADDR_REGNUM]);
8112 reg_offset += 4;
8113 }
8114
8115 /* Restore any remaining saved registers. */
8116 sparc_flat_save_restore (file, sp_str, reg_offset,
8117 current_frame_info.gmask & ~(HARD_FRAME_POINTER_MASK | RETURN_ADDR_MASK),
8118 current_frame_info.fmask,
8119 "ld", "ldd", 0);
8120
8121 /* If we had to increment %sp in two steps, record it so the second
8122 restoration in the epilogue finishes up. */
8123 if (reg_offset1 > 0)
8124 {
8125 size -= reg_offset1;
8126 if (size > 4096)
8127 build_big_number (file, size, t1_str);
8128 }
8129
8130 if (current_function_returns_struct)
8131 fprintf (file, "\tjmp\t%%o7+12\n");
8132 else
8133 fprintf (file, "\tretl\n");
8134
8135 /* If the only register saved is the return address, we need a
8136 nop, unless we have an instruction to put into it. Otherwise
8137 we don't since reloading multiple registers doesn't reference
8138 the register being loaded. */
8139
8140 if (epilogue_delay)
8141 {
8142 if (size)
8143 abort ();
8144 final_scan_insn (XEXP (epilogue_delay, 0), file, 1, -2, 1, NULL);
8145 }
8146
8147 else if (size > 4096)
8148 fprintf (file, "\tadd\t%s, %s, %s\n", sp_str, t1_str, sp_str);
8149
8150 else if (size > 0)
8151 fprintf (file, "\tsub\t%s, -"HOST_WIDE_INT_PRINT_DEC", %s\n",
8152 sp_str, size, sp_str);
8153
8154 else
8155 fprintf (file, "\tnop\n");
8156 }
8157
8158 /* Reset state info for each function. */
8159 current_frame_info = zero_frame_info;
8160
8161 sparc_output_deferred_case_vectors ();
8162 }
8163
8164 /* Define the number of delay slots needed for the function epilogue.
8165
8166 On the sparc, we need a slot if either no stack has been allocated,
8167 or the only register saved is the return register. */
8168
8169 int
sparc_flat_epilogue_delay_slots(void)8170 sparc_flat_epilogue_delay_slots (void)
8171 {
8172 if (!current_frame_info.initialized)
8173 (void) sparc_flat_compute_frame_size (get_frame_size ());
8174
8175 if (current_frame_info.total_size == 0)
8176 return 1;
8177
8178 return 0;
8179 }
8180
8181 /* Return true if TRIAL is a valid insn for the epilogue delay slot.
8182 Any single length instruction which doesn't reference the stack or frame
8183 pointer is OK. */
8184
8185 int
sparc_flat_eligible_for_epilogue_delay(rtx trial,int slot ATTRIBUTE_UNUSED)8186 sparc_flat_eligible_for_epilogue_delay (rtx trial, int slot ATTRIBUTE_UNUSED)
8187 {
8188 rtx pat = PATTERN (trial);
8189
8190 if (get_attr_length (trial) != 1)
8191 return 0;
8192
8193 if (! reg_mentioned_p (stack_pointer_rtx, pat)
8194 && ! reg_mentioned_p (frame_pointer_rtx, pat))
8195 return 1;
8196
8197 return 0;
8198 }
8199
8200 /* Adjust the cost of a scheduling dependency. Return the new cost of
8201 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
8202
8203 static int
supersparc_adjust_cost(rtx insn,rtx link,rtx dep_insn,int cost)8204 supersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8205 {
8206 enum attr_type insn_type;
8207
8208 if (! recog_memoized (insn))
8209 return 0;
8210
8211 insn_type = get_attr_type (insn);
8212
8213 if (REG_NOTE_KIND (link) == 0)
8214 {
8215 /* Data dependency; DEP_INSN writes a register that INSN reads some
8216 cycles later. */
8217
8218 /* if a load, then the dependence must be on the memory address;
8219 add an extra "cycle". Note that the cost could be two cycles
8220 if the reg was written late in an instruction group; we ca not tell
8221 here. */
8222 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD)
8223 return cost + 3;
8224
8225 /* Get the delay only if the address of the store is the dependence. */
8226 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE)
8227 {
8228 rtx pat = PATTERN(insn);
8229 rtx dep_pat = PATTERN (dep_insn);
8230
8231 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8232 return cost; /* This should not happen! */
8233
8234 /* The dependency between the two instructions was on the data that
8235 is being stored. Assume that this implies that the address of the
8236 store is not dependent. */
8237 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8238 return cost;
8239
8240 return cost + 3; /* An approximation. */
8241 }
8242
8243 /* A shift instruction cannot receive its data from an instruction
8244 in the same cycle; add a one cycle penalty. */
8245 if (insn_type == TYPE_SHIFT)
8246 return cost + 3; /* Split before cascade into shift. */
8247 }
8248 else
8249 {
8250 /* Anti- or output- dependency; DEP_INSN reads/writes a register that
8251 INSN writes some cycles later. */
8252
8253 /* These are only significant for the fpu unit; writing a fp reg before
8254 the fpu has finished with it stalls the processor. */
8255
8256 /* Reusing an integer register causes no problems. */
8257 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8258 return 0;
8259 }
8260
8261 return cost;
8262 }
8263
8264 static int
hypersparc_adjust_cost(rtx insn,rtx link,rtx dep_insn,int cost)8265 hypersparc_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
8266 {
8267 enum attr_type insn_type, dep_type;
8268 rtx pat = PATTERN(insn);
8269 rtx dep_pat = PATTERN (dep_insn);
8270
8271 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0)
8272 return cost;
8273
8274 insn_type = get_attr_type (insn);
8275 dep_type = get_attr_type (dep_insn);
8276
8277 switch (REG_NOTE_KIND (link))
8278 {
8279 case 0:
8280 /* Data dependency; DEP_INSN writes a register that INSN reads some
8281 cycles later. */
8282
8283 switch (insn_type)
8284 {
8285 case TYPE_STORE:
8286 case TYPE_FPSTORE:
8287 /* Get the delay iff the address of the store is the dependence. */
8288 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
8289 return cost;
8290
8291 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat)))
8292 return cost;
8293 return cost + 3;
8294
8295 case TYPE_LOAD:
8296 case TYPE_SLOAD:
8297 case TYPE_FPLOAD:
8298 /* If a load, then the dependence must be on the memory address. If
8299 the addresses aren't equal, then it might be a false dependency */
8300 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
8301 {
8302 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
8303 || GET_CODE (SET_DEST (dep_pat)) != MEM
8304 || GET_CODE (SET_SRC (pat)) != MEM
8305 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
8306 XEXP (SET_SRC (pat), 0)))
8307 return cost + 2;
8308
8309 return cost + 8;
8310 }
8311 break;
8312
8313 case TYPE_BRANCH:
8314 /* Compare to branch latency is 0. There is no benefit from
8315 separating compare and branch. */
8316 if (dep_type == TYPE_COMPARE)
8317 return 0;
8318 /* Floating point compare to branch latency is less than
8319 compare to conditional move. */
8320 if (dep_type == TYPE_FPCMP)
8321 return cost - 1;
8322 break;
8323 default:
8324 break;
8325 }
8326 break;
8327
8328 case REG_DEP_ANTI:
8329 /* Anti-dependencies only penalize the fpu unit. */
8330 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT)
8331 return 0;
8332 break;
8333
8334 default:
8335 break;
8336 }
8337
8338 return cost;
8339 }
8340
8341 static int
sparc_adjust_cost(rtx insn,rtx link,rtx dep,int cost)8342 sparc_adjust_cost(rtx insn, rtx link, rtx dep, int cost)
8343 {
8344 switch (sparc_cpu)
8345 {
8346 case PROCESSOR_SUPERSPARC:
8347 cost = supersparc_adjust_cost (insn, link, dep, cost);
8348 break;
8349 case PROCESSOR_HYPERSPARC:
8350 case PROCESSOR_SPARCLITE86X:
8351 cost = hypersparc_adjust_cost (insn, link, dep, cost);
8352 break;
8353 default:
8354 break;
8355 }
8356 return cost;
8357 }
8358
8359 static void
sparc_sched_init(FILE * dump ATTRIBUTE_UNUSED,int sched_verbose ATTRIBUTE_UNUSED,int max_ready ATTRIBUTE_UNUSED)8360 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED,
8361 int sched_verbose ATTRIBUTE_UNUSED,
8362 int max_ready ATTRIBUTE_UNUSED)
8363 {
8364 }
8365
8366 static int
sparc_use_dfa_pipeline_interface(void)8367 sparc_use_dfa_pipeline_interface (void)
8368 {
8369 if ((1 << sparc_cpu) &
8370 ((1 << PROCESSOR_ULTRASPARC) | (1 << PROCESSOR_CYPRESS) |
8371 (1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8372 (1 << PROCESSOR_SPARCLITE86X) | (1 << PROCESSOR_TSC701) |
8373 (1 << PROCESSOR_ULTRASPARC3)))
8374 return 1;
8375 return 0;
8376 }
8377
8378 static int
sparc_use_sched_lookahead(void)8379 sparc_use_sched_lookahead (void)
8380 {
8381 if (sparc_cpu == PROCESSOR_ULTRASPARC
8382 || sparc_cpu == PROCESSOR_ULTRASPARC3)
8383 return 4;
8384 if ((1 << sparc_cpu) &
8385 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) |
8386 (1 << PROCESSOR_SPARCLITE86X)))
8387 return 3;
8388 return 0;
8389 }
8390
8391 static int
sparc_issue_rate(void)8392 sparc_issue_rate (void)
8393 {
8394 switch (sparc_cpu)
8395 {
8396 default:
8397 return 1;
8398 case PROCESSOR_V9:
8399 /* Assume V9 processors are capable of at least dual-issue. */
8400 return 2;
8401 case PROCESSOR_SUPERSPARC:
8402 return 3;
8403 case PROCESSOR_HYPERSPARC:
8404 case PROCESSOR_SPARCLITE86X:
8405 return 2;
8406 case PROCESSOR_ULTRASPARC:
8407 case PROCESSOR_ULTRASPARC3:
8408 return 4;
8409 }
8410 }
8411
8412 static int
set_extends(rtx insn)8413 set_extends (rtx insn)
8414 {
8415 register rtx pat = PATTERN (insn);
8416
8417 switch (GET_CODE (SET_SRC (pat)))
8418 {
8419 /* Load and some shift instructions zero extend. */
8420 case MEM:
8421 case ZERO_EXTEND:
8422 /* sethi clears the high bits */
8423 case HIGH:
8424 /* LO_SUM is used with sethi. sethi cleared the high
8425 bits and the values used with lo_sum are positive */
8426 case LO_SUM:
8427 /* Store flag stores 0 or 1 */
8428 case LT: case LTU:
8429 case GT: case GTU:
8430 case LE: case LEU:
8431 case GE: case GEU:
8432 case EQ:
8433 case NE:
8434 return 1;
8435 case AND:
8436 {
8437 rtx op0 = XEXP (SET_SRC (pat), 0);
8438 rtx op1 = XEXP (SET_SRC (pat), 1);
8439 if (GET_CODE (op1) == CONST_INT)
8440 return INTVAL (op1) >= 0;
8441 if (GET_CODE (op0) != REG)
8442 return 0;
8443 if (sparc_check_64 (op0, insn) == 1)
8444 return 1;
8445 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8446 }
8447 case IOR:
8448 case XOR:
8449 {
8450 rtx op0 = XEXP (SET_SRC (pat), 0);
8451 rtx op1 = XEXP (SET_SRC (pat), 1);
8452 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
8453 return 0;
8454 if (GET_CODE (op1) == CONST_INT)
8455 return INTVAL (op1) >= 0;
8456 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
8457 }
8458 case LSHIFTRT:
8459 return GET_MODE (SET_SRC (pat)) == SImode;
8460 /* Positive integers leave the high bits zero. */
8461 case CONST_DOUBLE:
8462 return ! (CONST_DOUBLE_LOW (SET_SRC (pat)) & 0x80000000);
8463 case CONST_INT:
8464 return ! (INTVAL (SET_SRC (pat)) & 0x80000000);
8465 case ASHIFTRT:
8466 case SIGN_EXTEND:
8467 return - (GET_MODE (SET_SRC (pat)) == SImode);
8468 case REG:
8469 return sparc_check_64 (SET_SRC (pat), insn);
8470 default:
8471 return 0;
8472 }
8473 }
8474
8475 /* We _ought_ to have only one kind per function, but... */
8476 static GTY(()) rtx sparc_addr_diff_list;
8477 static GTY(()) rtx sparc_addr_list;
8478
8479 void
sparc_defer_case_vector(rtx lab,rtx vec,int diff)8480 sparc_defer_case_vector (rtx lab, rtx vec, int diff)
8481 {
8482 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec);
8483 if (diff)
8484 sparc_addr_diff_list
8485 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list);
8486 else
8487 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list);
8488 }
8489
8490 static void
sparc_output_addr_vec(rtx vec)8491 sparc_output_addr_vec (rtx vec)
8492 {
8493 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8494 int idx, vlen = XVECLEN (body, 0);
8495
8496 #ifdef ASM_OUTPUT_ADDR_VEC_START
8497 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8498 #endif
8499
8500 #ifdef ASM_OUTPUT_CASE_LABEL
8501 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8502 NEXT_INSN (lab));
8503 #else
8504 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8505 #endif
8506
8507 for (idx = 0; idx < vlen; idx++)
8508 {
8509 ASM_OUTPUT_ADDR_VEC_ELT
8510 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0)));
8511 }
8512
8513 #ifdef ASM_OUTPUT_ADDR_VEC_END
8514 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8515 #endif
8516 }
8517
8518 static void
sparc_output_addr_diff_vec(rtx vec)8519 sparc_output_addr_diff_vec (rtx vec)
8520 {
8521 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1);
8522 rtx base = XEXP (XEXP (body, 0), 0);
8523 int idx, vlen = XVECLEN (body, 1);
8524
8525 #ifdef ASM_OUTPUT_ADDR_VEC_START
8526 ASM_OUTPUT_ADDR_VEC_START (asm_out_file);
8527 #endif
8528
8529 #ifdef ASM_OUTPUT_CASE_LABEL
8530 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab),
8531 NEXT_INSN (lab));
8532 #else
8533 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab));
8534 #endif
8535
8536 for (idx = 0; idx < vlen; idx++)
8537 {
8538 ASM_OUTPUT_ADDR_DIFF_ELT
8539 (asm_out_file,
8540 body,
8541 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)),
8542 CODE_LABEL_NUMBER (base));
8543 }
8544
8545 #ifdef ASM_OUTPUT_ADDR_VEC_END
8546 ASM_OUTPUT_ADDR_VEC_END (asm_out_file);
8547 #endif
8548 }
8549
8550 static void
sparc_output_deferred_case_vectors(void)8551 sparc_output_deferred_case_vectors (void)
8552 {
8553 rtx t;
8554 int align;
8555
8556 if (sparc_addr_list == NULL_RTX
8557 && sparc_addr_diff_list == NULL_RTX)
8558 return;
8559
8560 /* Align to cache line in the function's code section. */
8561 function_section (current_function_decl);
8562
8563 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT);
8564 if (align > 0)
8565 ASM_OUTPUT_ALIGN (asm_out_file, align);
8566
8567 for (t = sparc_addr_list; t ; t = XEXP (t, 1))
8568 sparc_output_addr_vec (XEXP (t, 0));
8569 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1))
8570 sparc_output_addr_diff_vec (XEXP (t, 0));
8571
8572 sparc_addr_list = sparc_addr_diff_list = NULL_RTX;
8573 }
8574
8575 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are
8576 unknown. Return 1 if the high bits are zero, -1 if the register is
8577 sign extended. */
8578 int
sparc_check_64(rtx x,rtx insn)8579 sparc_check_64 (rtx x, rtx insn)
8580 {
8581 /* If a register is set only once it is safe to ignore insns this
8582 code does not know how to handle. The loop will either recognize
8583 the single set and return the correct value or fail to recognize
8584 it and return 0. */
8585 int set_once = 0;
8586 rtx y = x;
8587
8588 if (GET_CODE (x) != REG)
8589 abort ();
8590
8591 if (GET_MODE (x) == DImode)
8592 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
8593
8594 if (flag_expensive_optimizations
8595 && REG_N_SETS (REGNO (y)) == 1)
8596 set_once = 1;
8597
8598 if (insn == 0)
8599 {
8600 if (set_once)
8601 insn = get_last_insn_anywhere ();
8602 else
8603 return 0;
8604 }
8605
8606 while ((insn = PREV_INSN (insn)))
8607 {
8608 switch (GET_CODE (insn))
8609 {
8610 case JUMP_INSN:
8611 case NOTE:
8612 break;
8613 case CODE_LABEL:
8614 case CALL_INSN:
8615 default:
8616 if (! set_once)
8617 return 0;
8618 break;
8619 case INSN:
8620 {
8621 rtx pat = PATTERN (insn);
8622 if (GET_CODE (pat) != SET)
8623 return 0;
8624 if (rtx_equal_p (x, SET_DEST (pat)))
8625 return set_extends (insn);
8626 if (y && rtx_equal_p (y, SET_DEST (pat)))
8627 return set_extends (insn);
8628 if (reg_overlap_mentioned_p (SET_DEST (pat), y))
8629 return 0;
8630 }
8631 }
8632 }
8633 return 0;
8634 }
8635
8636 /* Returns assembly code to perform a DImode shift using
8637 a 64-bit global or out register on SPARC-V8+. */
8638 char *
sparc_v8plus_shift(rtx * operands,rtx insn,const char * opcode)8639 sparc_v8plus_shift (rtx *operands, rtx insn, const char *opcode)
8640 {
8641 static char asm_code[60];
8642
8643 /* The scratch register is only required when the destination
8644 register is not a 64-bit global or out register. */
8645 if (which_alternative != 2)
8646 operands[3] = operands[0];
8647
8648 /* We can only shift by constants <= 63. */
8649 if (GET_CODE (operands[2]) == CONST_INT)
8650 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
8651
8652 if (GET_CODE (operands[1]) == CONST_INT)
8653 {
8654 output_asm_insn ("mov\t%1, %3", operands);
8655 }
8656 else
8657 {
8658 output_asm_insn ("sllx\t%H1, 32, %3", operands);
8659 if (sparc_check_64 (operands[1], insn) <= 0)
8660 output_asm_insn ("srl\t%L1, 0, %L1", operands);
8661 output_asm_insn ("or\t%L1, %3, %3", operands);
8662 }
8663
8664 strcpy(asm_code, opcode);
8665
8666 if (which_alternative != 2)
8667 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0");
8668 else
8669 return strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0");
8670 }
8671
8672 /* Output rtl to increment the profiler label LABELNO
8673 for profiling a function entry. */
8674
8675 void
sparc_profile_hook(int labelno)8676 sparc_profile_hook (int labelno)
8677 {
8678 char buf[32];
8679 rtx lab, fun;
8680
8681 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
8682 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
8683 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION);
8684
8685 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode);
8686 }
8687
8688 #ifdef OBJECT_FORMAT_ELF
8689 static void
sparc_elf_asm_named_section(const char * name,unsigned int flags)8690 sparc_elf_asm_named_section (const char *name, unsigned int flags)
8691 {
8692 if (flags & SECTION_MERGE)
8693 {
8694 /* entsize cannot be expressed in this section attributes
8695 encoding style. */
8696 default_elf_asm_named_section (name, flags);
8697 return;
8698 }
8699
8700 fprintf (asm_out_file, "\t.section\t\"%s\"", name);
8701
8702 if (!(flags & SECTION_DEBUG))
8703 fputs (",#alloc", asm_out_file);
8704 if (flags & SECTION_WRITE)
8705 fputs (",#write", asm_out_file);
8706 if (flags & SECTION_TLS)
8707 fputs (",#tls", asm_out_file);
8708 if (flags & SECTION_CODE)
8709 fputs (",#execinstr", asm_out_file);
8710
8711 /* ??? Handle SECTION_BSS. */
8712
8713 fputc ('\n', asm_out_file);
8714 }
8715 #endif /* OBJECT_FORMAT_ELF */
8716
8717 /* We do not allow sibling calls if -mflat, nor
8718 we do not allow indirect calls to be optimized into sibling calls.
8719
8720 Also, on sparc 32-bit we cannot emit a sibling call when the
8721 current function returns a structure. This is because the "unimp
8722 after call" convention would cause the callee to return to the
8723 wrong place. The generic code already disallows cases where the
8724 function being called returns a structure.
8725
8726 It may seem strange how this last case could occur. Usually there
8727 is code after the call which jumps to epilogue code which dumps the
8728 return value into the struct return area. That ought to invalidate
8729 the sibling call right? Well, in the c++ case we can end up passing
8730 the pointer to the struct return area to a constructor (which returns
8731 void) and then nothing else happens. Such a sibling call would look
8732 valid without the added check here. */
8733 static bool
sparc_function_ok_for_sibcall(tree decl,tree exp ATTRIBUTE_UNUSED)8734 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8735 {
8736 return (decl
8737 && ! TARGET_FLAT
8738 && (TARGET_ARCH64 || ! current_function_returns_struct));
8739 }
8740
8741 /* libfunc renaming. */
8742 #include "config/gofast.h"
8743
8744 static void
sparc_init_libfuncs(void)8745 sparc_init_libfuncs (void)
8746 {
8747 if (TARGET_ARCH32)
8748 {
8749 /* Use the subroutines that Sun's library provides for integer
8750 multiply and divide. The `*' prevents an underscore from
8751 being prepended by the compiler. .umul is a little faster
8752 than .mul. */
8753 set_optab_libfunc (smul_optab, SImode, "*.umul");
8754 set_optab_libfunc (sdiv_optab, SImode, "*.div");
8755 set_optab_libfunc (udiv_optab, SImode, "*.udiv");
8756 set_optab_libfunc (smod_optab, SImode, "*.rem");
8757 set_optab_libfunc (umod_optab, SImode, "*.urem");
8758
8759 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */
8760 set_optab_libfunc (add_optab, TFmode, "_Q_add");
8761 set_optab_libfunc (sub_optab, TFmode, "_Q_sub");
8762 set_optab_libfunc (neg_optab, TFmode, "_Q_neg");
8763 set_optab_libfunc (smul_optab, TFmode, "_Q_mul");
8764 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div");
8765
8766 /* We can define the TFmode sqrt optab only if TARGET_FPU. This
8767 is because with soft-float, the SFmode and DFmode sqrt
8768 instructions will be absent, and the compiler will notice and
8769 try to use the TFmode sqrt instruction for calls to the
8770 builtin function sqrt, but this fails. */
8771 if (TARGET_FPU)
8772 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt");
8773
8774 set_optab_libfunc (eq_optab, TFmode, "_Q_feq");
8775 set_optab_libfunc (ne_optab, TFmode, "_Q_fne");
8776 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt");
8777 set_optab_libfunc (ge_optab, TFmode, "_Q_fge");
8778 set_optab_libfunc (lt_optab, TFmode, "_Q_flt");
8779 set_optab_libfunc (le_optab, TFmode, "_Q_fle");
8780
8781 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq");
8782 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq");
8783 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos");
8784 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod");
8785
8786 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi");
8787 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou");
8788 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq");
8789
8790 if (DITF_CONVERSION_LIBFUNCS)
8791 {
8792 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll");
8793 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull");
8794 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq");
8795 }
8796
8797 if (SUN_CONVERSION_LIBFUNCS)
8798 {
8799 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll");
8800 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull");
8801 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll");
8802 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull");
8803 }
8804 }
8805 if (TARGET_ARCH64)
8806 {
8807 /* In the SPARC 64bit ABI, SImode multiply and divide functions
8808 do not exist in the library. Make sure the compiler does not
8809 emit calls to them by accident. (It should always use the
8810 hardware instructions.) */
8811 set_optab_libfunc (smul_optab, SImode, 0);
8812 set_optab_libfunc (sdiv_optab, SImode, 0);
8813 set_optab_libfunc (udiv_optab, SImode, 0);
8814 set_optab_libfunc (smod_optab, SImode, 0);
8815 set_optab_libfunc (umod_optab, SImode, 0);
8816
8817 if (SUN_INTEGER_MULTIPLY_64)
8818 {
8819 set_optab_libfunc (smul_optab, DImode, "__mul64");
8820 set_optab_libfunc (sdiv_optab, DImode, "__div64");
8821 set_optab_libfunc (udiv_optab, DImode, "__udiv64");
8822 set_optab_libfunc (smod_optab, DImode, "__rem64");
8823 set_optab_libfunc (umod_optab, DImode, "__urem64");
8824 }
8825
8826 if (SUN_CONVERSION_LIBFUNCS)
8827 {
8828 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol");
8829 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul");
8830 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol");
8831 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul");
8832 }
8833 }
8834
8835 gofast_maybe_init_libfuncs ();
8836 }
8837
8838 /* ??? Similar to the standard section selection, but force reloc-y-ness
8839 if SUNOS4_SHARED_LIBRARIES. Unclear why this helps (as opposed to
8840 pretending PIC always on), but that's what the old code did. */
8841
8842 static void
sparc_aout_select_section(tree t,int reloc,unsigned HOST_WIDE_INT align)8843 sparc_aout_select_section (tree t, int reloc, unsigned HOST_WIDE_INT align)
8844 {
8845 default_select_section (t, reloc | SUNOS4_SHARED_LIBRARIES, align);
8846 }
8847
8848 /* Use text section for a constant unless we need more alignment than
8849 that offers. */
8850
8851 static void
sparc_aout_select_rtx_section(enum machine_mode mode,rtx x,unsigned HOST_WIDE_INT align)8852 sparc_aout_select_rtx_section (enum machine_mode mode, rtx x,
8853 unsigned HOST_WIDE_INT align)
8854 {
8855 if (align <= MAX_TEXT_ALIGN
8856 && ! (flag_pic && (symbolic_operand (x, mode)
8857 || SUNOS4_SHARED_LIBRARIES)))
8858 readonly_data_section ();
8859 else
8860 data_section ();
8861 }
8862
8863 int
sparc_extra_constraint_check(rtx op,int c,int strict)8864 sparc_extra_constraint_check (rtx op, int c, int strict)
8865 {
8866 int reload_ok_mem;
8867
8868 if (TARGET_ARCH64
8869 && (c == 'T' || c == 'U'))
8870 return 0;
8871
8872 switch (c)
8873 {
8874 case 'Q':
8875 return fp_sethi_p (op);
8876
8877 case 'R':
8878 return fp_mov_p (op);
8879
8880 case 'S':
8881 return fp_high_losum_p (op);
8882
8883 case 'U':
8884 if (! strict
8885 || (GET_CODE (op) == REG
8886 && (REGNO (op) < FIRST_PSEUDO_REGISTER
8887 || reg_renumber[REGNO (op)] >= 0)))
8888 return register_ok_for_ldd (op);
8889
8890 return 0;
8891
8892 case 'W':
8893 case 'T':
8894 break;
8895
8896 default:
8897 return 0;
8898 }
8899
8900 /* Our memory extra constraints have to emulate the
8901 behavior of 'm' and 'o' in order for reload to work
8902 correctly. */
8903 if (GET_CODE (op) == MEM)
8904 {
8905 reload_ok_mem = 0;
8906 if ((TARGET_ARCH64 || mem_min_alignment (op, 8))
8907 && (! strict
8908 || strict_memory_address_p (Pmode, XEXP (op, 0))))
8909 reload_ok_mem = 1;
8910 }
8911 else
8912 {
8913 reload_ok_mem = (reload_in_progress
8914 && GET_CODE (op) == REG
8915 && REGNO (op) >= FIRST_PSEUDO_REGISTER
8916 && reg_renumber [REGNO (op)] < 0);
8917 }
8918
8919 return reload_ok_mem;
8920 }
8921
8922 /* ??? This duplicates information provided to the compiler by the
8923 ??? scheduler description. Some day, teach genautomata to output
8924 ??? the latencies and then CSE will just use that. */
8925
8926 static bool
sparc_rtx_costs(rtx x,int code,int outer_code,int * total)8927 sparc_rtx_costs (rtx x, int code, int outer_code, int *total)
8928 {
8929 switch (code)
8930 {
8931 case PLUS: case MINUS: case ABS: case NEG:
8932 case FLOAT: case UNSIGNED_FLOAT:
8933 case FIX: case UNSIGNED_FIX:
8934 case FLOAT_EXTEND: case FLOAT_TRUNCATE:
8935 if (FLOAT_MODE_P (GET_MODE (x)))
8936 {
8937 switch (sparc_cpu)
8938 {
8939 case PROCESSOR_ULTRASPARC:
8940 case PROCESSOR_ULTRASPARC3:
8941 *total = COSTS_N_INSNS (4);
8942 return true;
8943
8944 case PROCESSOR_SUPERSPARC:
8945 *total = COSTS_N_INSNS (3);
8946 return true;
8947
8948 case PROCESSOR_CYPRESS:
8949 *total = COSTS_N_INSNS (5);
8950 return true;
8951
8952 case PROCESSOR_HYPERSPARC:
8953 case PROCESSOR_SPARCLITE86X:
8954 default:
8955 *total = COSTS_N_INSNS (1);
8956 return true;
8957 }
8958 }
8959
8960 *total = COSTS_N_INSNS (1);
8961 return true;
8962
8963 case SQRT:
8964 switch (sparc_cpu)
8965 {
8966 case PROCESSOR_ULTRASPARC:
8967 if (GET_MODE (x) == SFmode)
8968 *total = COSTS_N_INSNS (13);
8969 else
8970 *total = COSTS_N_INSNS (23);
8971 return true;
8972
8973 case PROCESSOR_ULTRASPARC3:
8974 if (GET_MODE (x) == SFmode)
8975 *total = COSTS_N_INSNS (20);
8976 else
8977 *total = COSTS_N_INSNS (29);
8978 return true;
8979
8980 case PROCESSOR_SUPERSPARC:
8981 *total = COSTS_N_INSNS (12);
8982 return true;
8983
8984 case PROCESSOR_CYPRESS:
8985 *total = COSTS_N_INSNS (63);
8986 return true;
8987
8988 case PROCESSOR_HYPERSPARC:
8989 case PROCESSOR_SPARCLITE86X:
8990 *total = COSTS_N_INSNS (17);
8991 return true;
8992
8993 default:
8994 *total = COSTS_N_INSNS (30);
8995 return true;
8996 }
8997
8998 case COMPARE:
8999 if (FLOAT_MODE_P (GET_MODE (x)))
9000 {
9001 switch (sparc_cpu)
9002 {
9003 case PROCESSOR_ULTRASPARC:
9004 case PROCESSOR_ULTRASPARC3:
9005 *total = COSTS_N_INSNS (1);
9006 return true;
9007
9008 case PROCESSOR_SUPERSPARC:
9009 *total = COSTS_N_INSNS (3);
9010 return true;
9011
9012 case PROCESSOR_CYPRESS:
9013 *total = COSTS_N_INSNS (5);
9014 return true;
9015
9016 case PROCESSOR_HYPERSPARC:
9017 case PROCESSOR_SPARCLITE86X:
9018 default:
9019 *total = COSTS_N_INSNS (1);
9020 return true;
9021 }
9022 }
9023
9024 /* ??? Maybe mark integer compares as zero cost on
9025 ??? all UltraSPARC processors because the result
9026 ??? can be bypassed to a branch in the same group. */
9027
9028 *total = COSTS_N_INSNS (1);
9029 return true;
9030
9031 case MULT:
9032 if (FLOAT_MODE_P (GET_MODE (x)))
9033 {
9034 switch (sparc_cpu)
9035 {
9036 case PROCESSOR_ULTRASPARC:
9037 case PROCESSOR_ULTRASPARC3:
9038 *total = COSTS_N_INSNS (4);
9039 return true;
9040
9041 case PROCESSOR_SUPERSPARC:
9042 *total = COSTS_N_INSNS (3);
9043 return true;
9044
9045 case PROCESSOR_CYPRESS:
9046 *total = COSTS_N_INSNS (7);
9047 return true;
9048
9049 case PROCESSOR_HYPERSPARC:
9050 case PROCESSOR_SPARCLITE86X:
9051 *total = COSTS_N_INSNS (1);
9052 return true;
9053
9054 default:
9055 *total = COSTS_N_INSNS (5);
9056 return true;
9057 }
9058 }
9059
9060 /* The latency is actually variable for Ultra-I/II
9061 And if one of the inputs have a known constant
9062 value, we could calculate this precisely.
9063
9064 However, for that to be useful we would need to
9065 add some machine description changes which would
9066 make sure small constants ended up in rs1 of the
9067 multiply instruction. This is because the multiply
9068 latency is determined by the number of clear (or
9069 set if the value is negative) bits starting from
9070 the most significant bit of the first input.
9071
9072 The algorithm for computing num_cycles of a multiply
9073 on Ultra-I/II is:
9074
9075 if (rs1 < 0)
9076 highest_bit = highest_clear_bit(rs1);
9077 else
9078 highest_bit = highest_set_bit(rs1);
9079 if (num_bits < 3)
9080 highest_bit = 3;
9081 num_cycles = 4 + ((highest_bit - 3) / 2);
9082
9083 If we did that we would have to also consider register
9084 allocation issues that would result from forcing such
9085 a value into a register.
9086
9087 There are other similar tricks we could play if we
9088 knew, for example, that one input was an array index.
9089
9090 Since we do not play any such tricks currently the
9091 safest thing to do is report the worst case latency. */
9092 if (sparc_cpu == PROCESSOR_ULTRASPARC)
9093 {
9094 *total = (GET_MODE (x) == DImode
9095 ? COSTS_N_INSNS (34) : COSTS_N_INSNS (19));
9096 return true;
9097 }
9098
9099 /* Multiply latency on Ultra-III, fortunately, is constant. */
9100 if (sparc_cpu == PROCESSOR_ULTRASPARC3)
9101 {
9102 *total = COSTS_N_INSNS (6);
9103 return true;
9104 }
9105
9106 if (sparc_cpu == PROCESSOR_HYPERSPARC
9107 || sparc_cpu == PROCESSOR_SPARCLITE86X)
9108 {
9109 *total = COSTS_N_INSNS (17);
9110 return true;
9111 }
9112
9113 *total = (TARGET_HARD_MUL ? COSTS_N_INSNS (5) : COSTS_N_INSNS (25));
9114 return true;
9115
9116 case DIV:
9117 case UDIV:
9118 case MOD:
9119 case UMOD:
9120 if (FLOAT_MODE_P (GET_MODE (x)))
9121 {
9122 switch (sparc_cpu)
9123 {
9124 case PROCESSOR_ULTRASPARC:
9125 if (GET_MODE (x) == SFmode)
9126 *total = COSTS_N_INSNS (13);
9127 else
9128 *total = COSTS_N_INSNS (23);
9129 return true;
9130
9131 case PROCESSOR_ULTRASPARC3:
9132 if (GET_MODE (x) == SFmode)
9133 *total = COSTS_N_INSNS (17);
9134 else
9135 *total = COSTS_N_INSNS (20);
9136 return true;
9137
9138 case PROCESSOR_SUPERSPARC:
9139 if (GET_MODE (x) == SFmode)
9140 *total = COSTS_N_INSNS (6);
9141 else
9142 *total = COSTS_N_INSNS (9);
9143 return true;
9144
9145 case PROCESSOR_HYPERSPARC:
9146 case PROCESSOR_SPARCLITE86X:
9147 if (GET_MODE (x) == SFmode)
9148 *total = COSTS_N_INSNS (8);
9149 else
9150 *total = COSTS_N_INSNS (12);
9151 return true;
9152
9153 default:
9154 *total = COSTS_N_INSNS (7);
9155 return true;
9156 }
9157 }
9158
9159 if (sparc_cpu == PROCESSOR_ULTRASPARC)
9160 *total = (GET_MODE (x) == DImode
9161 ? COSTS_N_INSNS (68) : COSTS_N_INSNS (37));
9162 else if (sparc_cpu == PROCESSOR_ULTRASPARC3)
9163 *total = (GET_MODE (x) == DImode
9164 ? COSTS_N_INSNS (71) : COSTS_N_INSNS (40));
9165 else
9166 *total = COSTS_N_INSNS (25);
9167 return true;
9168
9169 case IF_THEN_ELSE:
9170 /* Conditional moves. */
9171 switch (sparc_cpu)
9172 {
9173 case PROCESSOR_ULTRASPARC:
9174 *total = COSTS_N_INSNS (2);
9175 return true;
9176
9177 case PROCESSOR_ULTRASPARC3:
9178 if (FLOAT_MODE_P (GET_MODE (x)))
9179 *total = COSTS_N_INSNS (3);
9180 else
9181 *total = COSTS_N_INSNS (2);
9182 return true;
9183
9184 default:
9185 *total = COSTS_N_INSNS (1);
9186 return true;
9187 }
9188
9189 case MEM:
9190 /* If outer-code is SIGN/ZERO extension we have to subtract
9191 out COSTS_N_INSNS (1) from whatever we return in determining
9192 the cost. */
9193 switch (sparc_cpu)
9194 {
9195 case PROCESSOR_ULTRASPARC:
9196 if (outer_code == ZERO_EXTEND)
9197 *total = COSTS_N_INSNS (1);
9198 else
9199 *total = COSTS_N_INSNS (2);
9200 return true;
9201
9202 case PROCESSOR_ULTRASPARC3:
9203 if (outer_code == ZERO_EXTEND)
9204 {
9205 if (GET_MODE (x) == QImode
9206 || GET_MODE (x) == HImode
9207 || outer_code == SIGN_EXTEND)
9208 *total = COSTS_N_INSNS (2);
9209 else
9210 *total = COSTS_N_INSNS (1);
9211 }
9212 else
9213 {
9214 /* This handles sign extension (3 cycles)
9215 and everything else (2 cycles). */
9216 *total = COSTS_N_INSNS (2);
9217 }
9218 return true;
9219
9220 case PROCESSOR_SUPERSPARC:
9221 if (FLOAT_MODE_P (GET_MODE (x))
9222 || outer_code == ZERO_EXTEND
9223 || outer_code == SIGN_EXTEND)
9224 *total = COSTS_N_INSNS (0);
9225 else
9226 *total = COSTS_N_INSNS (1);
9227 return true;
9228
9229 case PROCESSOR_TSC701:
9230 if (outer_code == ZERO_EXTEND
9231 || outer_code == SIGN_EXTEND)
9232 *total = COSTS_N_INSNS (2);
9233 else
9234 *total = COSTS_N_INSNS (3);
9235 return true;
9236
9237 case PROCESSOR_CYPRESS:
9238 if (outer_code == ZERO_EXTEND
9239 || outer_code == SIGN_EXTEND)
9240 *total = COSTS_N_INSNS (1);
9241 else
9242 *total = COSTS_N_INSNS (2);
9243 return true;
9244
9245 case PROCESSOR_HYPERSPARC:
9246 case PROCESSOR_SPARCLITE86X:
9247 default:
9248 if (outer_code == ZERO_EXTEND
9249 || outer_code == SIGN_EXTEND)
9250 *total = COSTS_N_INSNS (0);
9251 else
9252 *total = COSTS_N_INSNS (1);
9253 return true;
9254 }
9255
9256 case CONST_INT:
9257 if (INTVAL (x) < 0x1000 && INTVAL (x) >= -0x1000)
9258 {
9259 *total = 0;
9260 return true;
9261 }
9262 /* FALLTHRU */
9263
9264 case HIGH:
9265 *total = 2;
9266 return true;
9267
9268 case CONST:
9269 case LABEL_REF:
9270 case SYMBOL_REF:
9271 *total = 4;
9272 return true;
9273
9274 case CONST_DOUBLE:
9275 if (GET_MODE (x) == DImode
9276 && ((XINT (x, 3) == 0
9277 && (unsigned HOST_WIDE_INT) XINT (x, 2) < 0x1000)
9278 || (XINT (x, 3) == -1
9279 && XINT (x, 2) < 0
9280 && XINT (x, 2) >= -0x1000)))
9281 *total = 0;
9282 else
9283 *total = 8;
9284 return true;
9285
9286 default:
9287 return false;
9288 }
9289 }
9290
9291 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
9292 Used for C++ multiple inheritance. */
9293
9294 static void
sparc_output_mi_thunk(FILE * file,tree thunk_fndecl ATTRIBUTE_UNUSED,HOST_WIDE_INT delta,HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,tree function)9295 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
9296 HOST_WIDE_INT delta,
9297 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
9298 tree function)
9299 {
9300 rtx this, insn, funexp, delta_rtx, tmp;
9301
9302 reload_completed = 1;
9303 epilogue_completed = 1;
9304 no_new_pseudos = 1;
9305 current_function_uses_only_leaf_regs = 1;
9306
9307 emit_note (NOTE_INSN_PROLOGUE_END);
9308
9309 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function
9310 returns a structure, the structure return pointer is there instead. */
9311 if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
9312 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
9313 else
9314 this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
9315
9316 /* Add DELTA. When possible use a plain add, otherwise load it into
9317 a register first. */
9318 delta_rtx = GEN_INT (delta);
9319 if (!SPARC_SIMM13_P (delta))
9320 {
9321 rtx scratch = gen_rtx_REG (Pmode, 1);
9322
9323 if (input_operand (delta_rtx, GET_MODE (scratch)))
9324 emit_insn (gen_rtx_SET (VOIDmode, scratch, delta_rtx));
9325 else
9326 {
9327 if (TARGET_ARCH64)
9328 sparc_emit_set_const64 (scratch, delta_rtx);
9329 else
9330 sparc_emit_set_const32 (scratch, delta_rtx);
9331 }
9332
9333 delta_rtx = scratch;
9334 }
9335
9336 tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
9337 emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
9338
9339 /* Generate a tail call to the target function. */
9340 if (! TREE_USED (function))
9341 {
9342 assemble_external (function);
9343 TREE_USED (function) = 1;
9344 }
9345 funexp = XEXP (DECL_RTL (function), 0);
9346 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
9347 insn = emit_call_insn (gen_sibcall (funexp));
9348 SIBLING_CALL_P (insn) = 1;
9349 emit_barrier ();
9350
9351 /* Run just enough of rest_of_compilation to get the insns emitted.
9352 There's not really enough bulk here to make other passes such as
9353 instruction scheduling worth while. Note that use_thunk calls
9354 assemble_start_function and assemble_end_function. */
9355 insn = get_insns ();
9356 insn_locators_initialize ();
9357 shorten_branches (insn);
9358 final_start_function (insn, file, 1);
9359 final (insn, file, 1, 0);
9360 final_end_function ();
9361
9362 reload_completed = 0;
9363 epilogue_completed = 0;
9364 no_new_pseudos = 0;
9365 }
9366
9367 /* How to allocate a 'struct machine_function'. */
9368
9369 static struct machine_function *
sparc_init_machine_status(void)9370 sparc_init_machine_status (void)
9371 {
9372 return ggc_alloc_cleared (sizeof (struct machine_function));
9373 }
9374
9375 /* Locate some local-dynamic symbol still in use by this function
9376 so that we can print its name in local-dynamic base patterns. */
9377
9378 static const char *
get_some_local_dynamic_name(void)9379 get_some_local_dynamic_name (void)
9380 {
9381 rtx insn;
9382
9383 if (cfun->machine->some_ld_name)
9384 return cfun->machine->some_ld_name;
9385
9386 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9387 if (INSN_P (insn)
9388 && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0))
9389 return cfun->machine->some_ld_name;
9390
9391 abort ();
9392 }
9393
9394 static int
get_some_local_dynamic_name_1(rtx * px,void * data ATTRIBUTE_UNUSED)9395 get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9396 {
9397 rtx x = *px;
9398
9399 if (x
9400 && GET_CODE (x) == SYMBOL_REF
9401 && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9402 {
9403 cfun->machine->some_ld_name = XSTR (x, 0);
9404 return 1;
9405 }
9406
9407 return 0;
9408 }
9409
9410 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
9411 We need to emit DTP-relative relocations. */
9412
9413 void
sparc_output_dwarf_dtprel(FILE * file,int size,rtx x)9414 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x)
9415 {
9416 switch (size)
9417 {
9418 case 4:
9419 fputs ("\t.word\t%r_tls_dtpoff32(", file);
9420 break;
9421 case 8:
9422 fputs ("\t.xword\t%r_tls_dtpoff64(", file);
9423 break;
9424 default:
9425 abort ();
9426 }
9427 output_addr_const (file, x);
9428 fputs (")", file);
9429 }
9430
9431 #include "gt-sparc.h"
9432