1# frv testcase to generate interrupt for st $GRk,@($GRi,$GRj) 2# mach: fr500 frv 3 .include "testutils.inc" 4 5 start 6 7 .global align 8align: 9 and_spr_immed -4081,tbr ; clear tbr.tt 10 set_gr_spr tbr,gr17 11 inc_gr_immed 0x100,gr17 ; address of exception handler 12 set_bctrlr_0_0 gr17 13 set_spr_immed 128,lcr 14 set_spr_addr ok1,lr 15 set_psr_et 1 16 set_gr_immed 0xdeadbeef,gr17 17 set_gr_immed 0,gr15 18 inc_gr_immed 2,sp ; out of alignment 19 20 test_spr_bits 1,0,1,isr ; mem_address_not_aligned is masked 21 sti gr17,@(sp,0) ; no exception 22 ldi @(sp,-2),gr18 ; stored at aligned address 23 test_gr_immed 0xdeadbeef,gr18 24 ldi @(sp,0),gr19 ; no exception 25 test_gr_immed 0xdeadbeef,gr19 26 27 and_spr_immed 0xfffffffe,isr ; turn off ISR.EMAM 28 set_gr_addr bad1,gr16 29bad1: sti gr17,@(sp,0) ; misaligned write in slot I1 30 test_gr_immed 1,gr15 31 32 set_gr_addr bad3,gr16 33 set_gr_gr sp,gr20 34 set_gr_immed 1,gr21 35 set_gr_immed 0x10101010,gr10 36bad2: nop.p 37bad3: ldu @(sp,gr21),gr10 ; misaligned read in slot I2 38 test_gr_immed 2,gr15 ; handler was called 39 test_gr_immed 0x10101010,gr10 ; gr10 not updated 40 test_gr_immed 1,gr21 ; gr21 not updated 41 inc_gr_immed 1,gr20 42 test_gr_gr gr20,sp ; sp updated 43 44 pass 45 46; exception handler 47ok1: 48 cmpi gr15,0,icc0 49 bne icc0,0,load 50 ; handle interrupt on store 51 test_spr_immed 0x100,esfr1 ; esr8 is active 52 test_spr_gr epcr8,gr16 53 test_spr_bits 0x0001,0,0x1,esr8 ; esr8 is valid 54 test_spr_bits 0x003e,1,0xb,esr8 ; esr8.ec is set 55 test_spr_bits 0x0800,11,0x1,esr8 ; esr8.eav is set 56 test_spr_gr ear8,sp 57 test_spr_bits 0x01000,12,0x1,esr8 ; esr8.edv is set 58 test_spr_bits 0x1e000,13,0x3,esr8 ; esr8.edn is 3 59 test_spr_gr edr3,gr17 ; edr3 is set 60 bra ret 61load: 62 ; handle interrupt on load 63 test_spr_immed 0x200,esfr1 ; esr9 is active 64 test_spr_gr epcr9,gr16 65 test_spr_bits 0x0001,0,0x1,esr9 ; esr9 is valid 66 test_spr_bits 0x003e,1,0xb,esr9 ; esr9.ec is set 67 test_spr_bits 0x0800,11,0x1,esr9 ; esr9.eav is set 68 test_spr_gr ear9,sp 69 test_spr_bits 0x1000,12,0x0,esr9 ; esr9.edv is not set 70ret: 71 inc_gr_immed 1,gr15 72 rett 0 73 fail 74