1 /* Semantic operand instances for m32r.
2 
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
5 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
6 
7 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13 
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 GNU General Public License for more details.
18 
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
23 */
24 
25 #include "sysdep.h"
26 #include "ansidecl.h"
27 #include "bfd.h"
28 #include "symcat.h"
29 #include "m32r-desc.h"
30 #include "m32r-opc.h"
31 
32 /* Operand references.  */
33 
34 #if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
35 #define OP_ENT(op) M32R_OPERAND_##op
36 #else
37 #define OP_ENT(op) M32R_OPERAND_/**/op
38 #endif
39 #define INPUT CGEN_OPINST_INPUT
40 #define OUTPUT CGEN_OPINST_OUTPUT
41 #define END CGEN_OPINST_END
42 #define COND_REF CGEN_OPINST_COND_REF
43 
44 static const CGEN_OPINST sfmt_empty_ops[] = {
45   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
46 };
47 
48 static const CGEN_OPINST sfmt_add_ops[] = {
49   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
50   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
51   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
52   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
53 };
54 
55 static const CGEN_OPINST sfmt_add3_ops[] = {
56   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
57   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
58   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
59   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
60 };
61 
62 static const CGEN_OPINST sfmt_and3_ops[] = {
63   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
64   { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
65   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
66   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
67 };
68 
69 static const CGEN_OPINST sfmt_or3_ops[] = {
70   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
71   { INPUT, "ulo16", HW_H_ULO16, CGEN_MODE_UINT, OP_ENT (ULO16), 0, 0 },
72   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
73   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
74 };
75 
76 static const CGEN_OPINST sfmt_addi_ops[] = {
77   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
78   { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
79   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
80   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
81 };
82 
83 static const CGEN_OPINST sfmt_addv_ops[] = {
84   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
85   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
86   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
87   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
88   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
89 };
90 
91 static const CGEN_OPINST sfmt_addv3_ops[] = {
92   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
93   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
94   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
95   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
96   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
97 };
98 
99 static const CGEN_OPINST sfmt_addx_ops[] = {
100   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
101   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
102   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
103   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
104   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
105   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
106 };
107 
108 static const CGEN_OPINST sfmt_bc8_ops[] = {
109   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
110   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
111   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
112   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
113 };
114 
115 static const CGEN_OPINST sfmt_bc24_ops[] = {
116   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
117   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
118   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
119   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
120 };
121 
122 static const CGEN_OPINST sfmt_beq_ops[] = {
123   { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
124   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
125   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
126   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
127   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
128 };
129 
130 static const CGEN_OPINST sfmt_beqz_ops[] = {
131   { INPUT, "disp16", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP16), 0, COND_REF },
132   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
133   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
134   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
135 };
136 
137 static const CGEN_OPINST sfmt_bl8_ops[] = {
138   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
139   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
140   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
141   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
142   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
143 };
144 
145 static const CGEN_OPINST sfmt_bl24_ops[] = {
146   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
147   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
148   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
149   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
150   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
151 };
152 
153 static const CGEN_OPINST sfmt_bcl8_ops[] = {
154   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
155   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, COND_REF },
156   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
157   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
158   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
159   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
160 };
161 
162 static const CGEN_OPINST sfmt_bcl24_ops[] = {
163   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
164   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, COND_REF },
165   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
166   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, COND_REF },
167   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
168   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
169 };
170 
171 static const CGEN_OPINST sfmt_bra8_ops[] = {
172   { INPUT, "disp8", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP8), 0, 0 },
173   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
174   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
175 };
176 
177 static const CGEN_OPINST sfmt_bra24_ops[] = {
178   { INPUT, "disp24", HW_H_IADDR, CGEN_MODE_USI, OP_ENT (DISP24), 0, 0 },
179   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
180   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
181 };
182 
183 static const CGEN_OPINST sfmt_cmp_ops[] = {
184   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
185   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
186   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
187   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
188 };
189 
190 static const CGEN_OPINST sfmt_cmpi_ops[] = {
191   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
192   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
193   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
194   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
195 };
196 
197 static const CGEN_OPINST sfmt_cmpz_ops[] = {
198   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
199   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
200   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
201 };
202 
203 static const CGEN_OPINST sfmt_div_ops[] = {
204   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
205   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
206   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, COND_REF },
207   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
208 };
209 
210 static const CGEN_OPINST sfmt_jc_ops[] = {
211   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
212   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
213   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, COND_REF },
214   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
215 };
216 
217 static const CGEN_OPINST sfmt_jl_ops[] = {
218   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
219   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
220   { OUTPUT, "h_gr_SI_14", HW_H_GR, CGEN_MODE_SI, 0, 14, 0 },
221   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
222   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
223 };
224 
225 static const CGEN_OPINST sfmt_jmp_ops[] = {
226   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
227   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
228   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
229 };
230 
231 static const CGEN_OPINST sfmt_ld_ops[] = {
232   { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
233   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
234   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
235   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
236 };
237 
238 static const CGEN_OPINST sfmt_ld_d_ops[] = {
239   { INPUT, "h_memory_SI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
240   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
241   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
242   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
243   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
244 };
245 
246 static const CGEN_OPINST sfmt_ldb_ops[] = {
247   { INPUT, "h_memory_QI_sr", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
248   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
249   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
250   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
251 };
252 
253 static const CGEN_OPINST sfmt_ldb_d_ops[] = {
254   { INPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
255   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
256   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
257   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
258   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
259 };
260 
261 static const CGEN_OPINST sfmt_ldh_ops[] = {
262   { INPUT, "h_memory_HI_sr", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
263   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
264   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
265   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
266 };
267 
268 static const CGEN_OPINST sfmt_ldh_d_ops[] = {
269   { INPUT, "h_memory_HI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
270   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
271   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
272   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
273   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
274 };
275 
276 static const CGEN_OPINST sfmt_ld_plus_ops[] = {
277   { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
278   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
279   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
280   { OUTPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
281   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
282 };
283 
284 static const CGEN_OPINST sfmt_ld24_ops[] = {
285   { INPUT, "uimm24", HW_H_ADDR, CGEN_MODE_USI, OP_ENT (UIMM24), 0, 0 },
286   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
287   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
288 };
289 
290 static const CGEN_OPINST sfmt_ldi8_ops[] = {
291   { INPUT, "simm8", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM8), 0, 0 },
292   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
293   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
294 };
295 
296 static const CGEN_OPINST sfmt_ldi16_ops[] = {
297   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
298   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
299   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
300 };
301 
302 static const CGEN_OPINST sfmt_lock_ops[] = {
303   { INPUT, "h_memory_SI_sr", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
304   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
305   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
306   { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
307   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
308 };
309 
310 static const CGEN_OPINST sfmt_machi_ops[] = {
311   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
312   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
313   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
314   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
315   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
316 };
317 
318 static const CGEN_OPINST sfmt_machi_a_ops[] = {
319   { INPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
320   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
321   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
322   { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
323   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
324 };
325 
326 static const CGEN_OPINST sfmt_mulhi_ops[] = {
327   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
328   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
329   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
330   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
331 };
332 
333 static const CGEN_OPINST sfmt_mulhi_a_ops[] = {
334   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
335   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
336   { OUTPUT, "acc", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACC), 0, 0 },
337   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
338 };
339 
340 static const CGEN_OPINST sfmt_mv_ops[] = {
341   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
342   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
343   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
344 };
345 
346 static const CGEN_OPINST sfmt_mvfachi_ops[] = {
347   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
348   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
349   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
350 };
351 
352 static const CGEN_OPINST sfmt_mvfachi_a_ops[] = {
353   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
354   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
355   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
356 };
357 
358 static const CGEN_OPINST sfmt_mvfc_ops[] = {
359   { INPUT, "scr", HW_H_CR, CGEN_MODE_USI, OP_ENT (SCR), 0, 0 },
360   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
361   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
362 };
363 
364 static const CGEN_OPINST sfmt_mvtachi_ops[] = {
365   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
366   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
367   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
368   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
369 };
370 
371 static const CGEN_OPINST sfmt_mvtachi_a_ops[] = {
372   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
373   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
374   { OUTPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
375   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
376 };
377 
378 static const CGEN_OPINST sfmt_mvtc_ops[] = {
379   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
380   { OUTPUT, "dcr", HW_H_CR, CGEN_MODE_USI, OP_ENT (DCR), 0, 0 },
381   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
382 };
383 
384 static const CGEN_OPINST sfmt_nop_ops[] = {
385   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
386 };
387 
388 static const CGEN_OPINST sfmt_rac_ops[] = {
389   { INPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
390   { OUTPUT, "accum", HW_H_ACCUM, CGEN_MODE_DI, 0, 0, 0 },
391   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
392 };
393 
394 static const CGEN_OPINST sfmt_rac_dsi_ops[] = {
395   { INPUT, "accs", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCS), 0, 0 },
396   { INPUT, "imm1", HW_H_UINT, CGEN_MODE_INT, OP_ENT (IMM1), 0, 0 },
397   { OUTPUT, "accd", HW_H_ACCUMS, CGEN_MODE_DI, OP_ENT (ACCD), 0, 0 },
398   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
399 };
400 
401 static const CGEN_OPINST sfmt_rte_ops[] = {
402   { INPUT, "h_bbpsw_UQI", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
403   { INPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
404   { INPUT, "h_cr_USI_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
405   { INPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
406   { OUTPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
407   { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
408   { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
409   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
410   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
411 };
412 
413 static const CGEN_OPINST sfmt_seth_ops[] = {
414   { INPUT, "hi16", HW_H_HI16, CGEN_MODE_SI, OP_ENT (HI16), 0, 0 },
415   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
416   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
417 };
418 
419 static const CGEN_OPINST sfmt_sll3_ops[] = {
420   { INPUT, "simm16", HW_H_SINT, CGEN_MODE_SI, OP_ENT (SIMM16), 0, 0 },
421   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
422   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
423   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
424 };
425 
426 static const CGEN_OPINST sfmt_slli_ops[] = {
427   { INPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
428   { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_INT, OP_ENT (UIMM5), 0, 0 },
429   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
430   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
431 };
432 
433 static const CGEN_OPINST sfmt_st_ops[] = {
434   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
435   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
436   { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
437   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
438 };
439 
440 static const CGEN_OPINST sfmt_st_d_ops[] = {
441   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
442   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
443   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
444   { OUTPUT, "h_memory_SI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
445   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
446 };
447 
448 static const CGEN_OPINST sfmt_stb_ops[] = {
449   { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
450   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
451   { OUTPUT, "h_memory_QI_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
452   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
453 };
454 
455 static const CGEN_OPINST sfmt_stb_d_ops[] = {
456   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
457   { INPUT, "src1", HW_H_GR, CGEN_MODE_QI, OP_ENT (SRC1), 0, 0 },
458   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
459   { OUTPUT, "h_memory_QI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
460   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
461 };
462 
463 static const CGEN_OPINST sfmt_sth_ops[] = {
464   { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
465   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, 0 },
466   { OUTPUT, "h_memory_HI_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
467   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
468 };
469 
470 static const CGEN_OPINST sfmt_sth_d_ops[] = {
471   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
472   { INPUT, "src1", HW_H_GR, CGEN_MODE_HI, OP_ENT (SRC1), 0, 0 },
473   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
474   { OUTPUT, "h_memory_HI_add__DFLT_src2_slo16", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
475   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
476 };
477 
478 static const CGEN_OPINST sfmt_st_plus_ops[] = {
479   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
480   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
481   { OUTPUT, "h_memory_SI_new_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, 0 },
482   { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
483   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
484 };
485 
486 static const CGEN_OPINST sfmt_sth_plus_ops[] = {
487   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
488   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
489   { OUTPUT, "h_memory_HI_new_src2", HW_H_MEMORY, CGEN_MODE_HI, 0, 0, 0 },
490   { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
491   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
492 };
493 
494 static const CGEN_OPINST sfmt_stb_plus_ops[] = {
495   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
496   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
497   { OUTPUT, "h_memory_QI_new_src2", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
498   { OUTPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
499   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
500 };
501 
502 static const CGEN_OPINST sfmt_trap_ops[] = {
503   { INPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
504   { INPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
505   { INPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
506   { INPUT, "pc", HW_H_PC, CGEN_MODE_USI, 0, 0, 0 },
507   { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
508   { OUTPUT, "h_bbpsw_UQI", HW_H_BBPSW, CGEN_MODE_UQI, 0, 0, 0 },
509   { OUTPUT, "h_bpsw_UQI", HW_H_BPSW, CGEN_MODE_UQI, 0, 0, 0 },
510   { OUTPUT, "h_cr_USI_14", HW_H_CR, CGEN_MODE_USI, 0, 14, 0 },
511   { OUTPUT, "h_cr_USI_6", HW_H_CR, CGEN_MODE_USI, 0, 6, 0 },
512   { OUTPUT, "h_psw_UQI", HW_H_PSW, CGEN_MODE_UQI, 0, 0, 0 },
513   { OUTPUT, "pc", HW_H_PC, CGEN_MODE_SI, 0, 0, 0 },
514   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
515 };
516 
517 static const CGEN_OPINST sfmt_unlock_ops[] = {
518   { INPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
519   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, COND_REF },
520   { INPUT, "src2", HW_H_GR, CGEN_MODE_USI, OP_ENT (SRC2), 0, COND_REF },
521   { OUTPUT, "h_lock_BI", HW_H_LOCK, CGEN_MODE_BI, 0, 0, 0 },
522   { OUTPUT, "h_memory_SI_src2", HW_H_MEMORY, CGEN_MODE_SI, 0, 0, COND_REF },
523   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
524 };
525 
526 static const CGEN_OPINST sfmt_satb_ops[] = {
527   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
528   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
529   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
530 };
531 
532 static const CGEN_OPINST sfmt_sat_ops[] = {
533   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
534   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, COND_REF },
535   { OUTPUT, "dr", HW_H_GR, CGEN_MODE_SI, OP_ENT (DR), 0, 0 },
536   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
537 };
538 
539 static const CGEN_OPINST sfmt_sadd_ops[] = {
540   { INPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
541   { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
542   { OUTPUT, "h_accums_DI_0", HW_H_ACCUMS, CGEN_MODE_DI, 0, 0, 0 },
543   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
544 };
545 
546 static const CGEN_OPINST sfmt_macwu1_ops[] = {
547   { INPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
548   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
549   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
550   { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
551   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
552 };
553 
554 static const CGEN_OPINST sfmt_mulwu1_ops[] = {
555   { INPUT, "src1", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC1), 0, 0 },
556   { INPUT, "src2", HW_H_GR, CGEN_MODE_SI, OP_ENT (SRC2), 0, 0 },
557   { OUTPUT, "h_accums_DI_1", HW_H_ACCUMS, CGEN_MODE_DI, 0, 1, 0 },
558   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
559 };
560 
561 static const CGEN_OPINST sfmt_sc_ops[] = {
562   { INPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
563   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
564 };
565 
566 static const CGEN_OPINST sfmt_clrpsw_ops[] = {
567   { INPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
568   { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_BI, OP_ENT (UIMM8), 0, 0 },
569   { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
570   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
571 };
572 
573 static const CGEN_OPINST sfmt_setpsw_ops[] = {
574   { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_USI, OP_ENT (UIMM8), 0, 0 },
575   { OUTPUT, "h_cr_USI_0", HW_H_CR, CGEN_MODE_USI, 0, 0, 0 },
576   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
577 };
578 
579 static const CGEN_OPINST sfmt_bset_ops[] = {
580   { INPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
581   { INPUT, "slo16", HW_H_SLO16, CGEN_MODE_INT, OP_ENT (SLO16), 0, 0 },
582   { INPUT, "sr", HW_H_GR, CGEN_MODE_SI, OP_ENT (SR), 0, 0 },
583   { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
584   { OUTPUT, "h_memory_QI_add__DFLT_sr_slo16", HW_H_MEMORY, CGEN_MODE_QI, 0, 0, 0 },
585   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
586 };
587 
588 static const CGEN_OPINST sfmt_btst_ops[] = {
589   { INPUT, "sr", HW_H_GR, CGEN_MODE_USI, OP_ENT (SR), 0, 0 },
590   { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
591   { OUTPUT, "condbit", HW_H_COND, CGEN_MODE_BI, 0, 0, 0 },
592   { END, (const char *)0, (enum cgen_hw_type)0, (enum cgen_mode)0, (enum cgen_operand_type)0, 0, 0 }
593 };
594 
595 #undef OP_ENT
596 #undef INPUT
597 #undef OUTPUT
598 #undef END
599 #undef COND_REF
600 
601 /* Operand instance lookup table.  */
602 
603 static const CGEN_OPINST *m32r_cgen_opinst_table[MAX_INSNS] = {
604   0,
605   & sfmt_add_ops[0],
606   & sfmt_add3_ops[0],
607   & sfmt_add_ops[0],
608   & sfmt_and3_ops[0],
609   & sfmt_add_ops[0],
610   & sfmt_or3_ops[0],
611   & sfmt_add_ops[0],
612   & sfmt_and3_ops[0],
613   & sfmt_addi_ops[0],
614   & sfmt_addv_ops[0],
615   & sfmt_addv3_ops[0],
616   & sfmt_addx_ops[0],
617   & sfmt_bc8_ops[0],
618   & sfmt_bc24_ops[0],
619   & sfmt_beq_ops[0],
620   & sfmt_beqz_ops[0],
621   & sfmt_beqz_ops[0],
622   & sfmt_beqz_ops[0],
623   & sfmt_beqz_ops[0],
624   & sfmt_beqz_ops[0],
625   & sfmt_beqz_ops[0],
626   & sfmt_bl8_ops[0],
627   & sfmt_bl24_ops[0],
628   & sfmt_bcl8_ops[0],
629   & sfmt_bcl24_ops[0],
630   & sfmt_bc8_ops[0],
631   & sfmt_bc24_ops[0],
632   & sfmt_beq_ops[0],
633   & sfmt_bra8_ops[0],
634   & sfmt_bra24_ops[0],
635   & sfmt_bcl8_ops[0],
636   & sfmt_bcl24_ops[0],
637   & sfmt_cmp_ops[0],
638   & sfmt_cmpi_ops[0],
639   & sfmt_cmp_ops[0],
640   & sfmt_cmpi_ops[0],
641   & sfmt_cmp_ops[0],
642   & sfmt_cmpz_ops[0],
643   & sfmt_div_ops[0],
644   & sfmt_div_ops[0],
645   & sfmt_div_ops[0],
646   & sfmt_div_ops[0],
647   & sfmt_div_ops[0],
648   & sfmt_div_ops[0],
649   & sfmt_div_ops[0],
650   & sfmt_div_ops[0],
651   & sfmt_div_ops[0],
652   & sfmt_div_ops[0],
653   & sfmt_div_ops[0],
654   & sfmt_div_ops[0],
655   & sfmt_jc_ops[0],
656   & sfmt_jc_ops[0],
657   & sfmt_jl_ops[0],
658   & sfmt_jmp_ops[0],
659   & sfmt_ld_ops[0],
660   & sfmt_ld_d_ops[0],
661   & sfmt_ldb_ops[0],
662   & sfmt_ldb_d_ops[0],
663   & sfmt_ldh_ops[0],
664   & sfmt_ldh_d_ops[0],
665   & sfmt_ldb_ops[0],
666   & sfmt_ldb_d_ops[0],
667   & sfmt_ldh_ops[0],
668   & sfmt_ldh_d_ops[0],
669   & sfmt_ld_plus_ops[0],
670   & sfmt_ld24_ops[0],
671   & sfmt_ldi8_ops[0],
672   & sfmt_ldi16_ops[0],
673   & sfmt_lock_ops[0],
674   & sfmt_machi_ops[0],
675   & sfmt_machi_a_ops[0],
676   & sfmt_machi_ops[0],
677   & sfmt_machi_a_ops[0],
678   & sfmt_machi_ops[0],
679   & sfmt_machi_a_ops[0],
680   & sfmt_machi_ops[0],
681   & sfmt_machi_a_ops[0],
682   & sfmt_add_ops[0],
683   & sfmt_mulhi_ops[0],
684   & sfmt_mulhi_a_ops[0],
685   & sfmt_mulhi_ops[0],
686   & sfmt_mulhi_a_ops[0],
687   & sfmt_mulhi_ops[0],
688   & sfmt_mulhi_a_ops[0],
689   & sfmt_mulhi_ops[0],
690   & sfmt_mulhi_a_ops[0],
691   & sfmt_mv_ops[0],
692   & sfmt_mvfachi_ops[0],
693   & sfmt_mvfachi_a_ops[0],
694   & sfmt_mvfachi_ops[0],
695   & sfmt_mvfachi_a_ops[0],
696   & sfmt_mvfachi_ops[0],
697   & sfmt_mvfachi_a_ops[0],
698   & sfmt_mvfc_ops[0],
699   & sfmt_mvtachi_ops[0],
700   & sfmt_mvtachi_a_ops[0],
701   & sfmt_mvtachi_ops[0],
702   & sfmt_mvtachi_a_ops[0],
703   & sfmt_mvtc_ops[0],
704   & sfmt_mv_ops[0],
705   & sfmt_nop_ops[0],
706   & sfmt_mv_ops[0],
707   & sfmt_rac_ops[0],
708   & sfmt_rac_dsi_ops[0],
709   & sfmt_rac_ops[0],
710   & sfmt_rac_dsi_ops[0],
711   & sfmt_rte_ops[0],
712   & sfmt_seth_ops[0],
713   & sfmt_add_ops[0],
714   & sfmt_sll3_ops[0],
715   & sfmt_slli_ops[0],
716   & sfmt_add_ops[0],
717   & sfmt_sll3_ops[0],
718   & sfmt_slli_ops[0],
719   & sfmt_add_ops[0],
720   & sfmt_sll3_ops[0],
721   & sfmt_slli_ops[0],
722   & sfmt_st_ops[0],
723   & sfmt_st_d_ops[0],
724   & sfmt_stb_ops[0],
725   & sfmt_stb_d_ops[0],
726   & sfmt_sth_ops[0],
727   & sfmt_sth_d_ops[0],
728   & sfmt_st_plus_ops[0],
729   & sfmt_sth_plus_ops[0],
730   & sfmt_stb_plus_ops[0],
731   & sfmt_st_plus_ops[0],
732   & sfmt_add_ops[0],
733   & sfmt_addv_ops[0],
734   & sfmt_addx_ops[0],
735   & sfmt_trap_ops[0],
736   & sfmt_unlock_ops[0],
737   & sfmt_satb_ops[0],
738   & sfmt_satb_ops[0],
739   & sfmt_sat_ops[0],
740   & sfmt_cmpz_ops[0],
741   & sfmt_sadd_ops[0],
742   & sfmt_macwu1_ops[0],
743   & sfmt_machi_ops[0],
744   & sfmt_mulwu1_ops[0],
745   & sfmt_macwu1_ops[0],
746   & sfmt_sc_ops[0],
747   & sfmt_sc_ops[0],
748   & sfmt_clrpsw_ops[0],
749   & sfmt_setpsw_ops[0],
750   & sfmt_bset_ops[0],
751   & sfmt_bset_ops[0],
752   & sfmt_btst_ops[0],
753 };
754 
755 /* Function to call before using the operand instance table.  */
756 
757 void
m32r_cgen_init_opinst_table(cd)758 m32r_cgen_init_opinst_table (cd)
759      CGEN_CPU_DESC cd;
760 {
761   int i;
762   const CGEN_OPINST **oi = & m32r_cgen_opinst_table[0];
763   CGEN_INSN *insns = (CGEN_INSN *) cd->insn_table.init_entries;
764   for (i = 0; i < MAX_INSNS; ++i)
765     insns[i].opinst = oi[i];
766 }
767