1# frv testcase for cmqmachu $GRi,$GRj,$GRk,$CCi,$cond 2# mach: frv fr500 fr400 3 4 .include "testutils.inc" 5 6 start 7 8 .global cmqmachu 9cmqmachu: 10 set_spr_immed 0x1b1b,cccr 11 12 set_spr_immed 0,msr0 13 set_spr_immed 0,msr1 14 set_accg_immed 0,accg0 15 set_acc_immed 0,acc0 16 set_accg_immed 0,accg1 17 set_acc_immed 0,acc1 18 set_accg_immed 0,accg2 19 set_acc_immed 0,acc2 20 set_accg_immed 0,accg3 21 set_acc_immed 0,acc3 22 set_fr_iimmed 3,2,fr8 ; multiply small numbers 23 set_fr_iimmed 2,3,fr10 24 set_fr_iimmed 1,2,fr9 ; multiply by 1 25 set_fr_iimmed 2,1,fr11 26 cmqmachu fr8,fr10,acc0,cc0,1 27 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 28 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 29 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 30 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 31 test_accg_immed 0,accg0 32 test_acc_immed 6,acc0 33 test_accg_immed 0,accg1 34 test_acc_immed 6,acc1 35 test_accg_immed 0,accg2 36 test_acc_immed 2,acc2 37 test_accg_immed 0,accg3 38 test_acc_immed 2,acc3 39 40 set_fr_iimmed 0,2,fr8 ; multiply by 0 41 set_fr_iimmed 2,0,fr10 42 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 43 set_fr_iimmed 2,0x3fff,fr11 44 cmqmachu fr8,fr10,acc0,cc0,1 45 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 46 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 47 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 48 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 49 test_accg_immed 0,accg0 50 test_acc_immed 6,acc0 51 test_accg_immed 0,accg1 52 test_acc_immed 6,acc1 53 test_accg_immed 0,accg2 54 test_acc_limmed 0x0000,0x8000,acc2 55 test_accg_immed 0,accg3 56 test_acc_limmed 0x0000,0x8000,acc3 57 58 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 59 set_fr_iimmed 2,0x4000,fr10 60 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 61 set_fr_iimmed 2,0x8000,fr11 62 cmqmachu fr8,fr10,acc0,cc0,1 63 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 64 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 65 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 66 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 67 test_accg_immed 0,accg0 68 test_acc_limmed 0x0000,0x8006,acc0 69 test_accg_immed 0,accg1 70 test_acc_limmed 0x0000,0x8006,acc1 71 test_accg_immed 0,accg2 72 test_acc_immed 0x00018000,acc2 73 test_accg_immed 0,accg3 74 test_acc_immed 0x00018000,acc3 75 76 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 77 set_fr_iimmed 0x7fff,0x7fff,fr10 78 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 79 set_fr_iimmed 0x8000,0x8000,fr11 80 cmqmachu fr8,fr10,acc0,cc4,1 81 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 82 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 83 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 84 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 85 test_accg_immed 0,accg0 86 test_acc_immed 0x3fff8007,acc0 87 test_accg_immed 0,accg1 88 test_acc_immed 0x3fff8007,acc1 89 test_accg_immed 0,accg2 90 test_acc_limmed 0x4001,0x8000,acc2 91 test_accg_immed 0,accg3 92 test_acc_limmed 0x4001,0x8000,acc3 93 94 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 95 set_fr_iimmed 0xffff,0xffff,fr10 96 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 97 set_fr_iimmed 0xffff,0xffff,fr11 98 cmqmachu fr8,fr10,acc0,cc4,1 99 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 100 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 101 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 102 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 103 test_accg_immed 1,accg0 104 test_acc_limmed 0x3ffd,0x8008,acc0 105 test_accg_immed 1,accg1 106 test_acc_limmed 0x3ffd,0x8008,acc1 107 test_accg_immed 1,accg2 108 test_acc_limmed 0x3fff,0x8001,acc2 109 test_accg_immed 1,accg3 110 test_acc_limmed 0x3fff,0x8001,acc3 111 112 set_accg_immed 0xff,accg0 ; saturation 113 set_acc_immed 0xffffffff,acc0 114 set_accg_immed 0xff,accg1 115 set_acc_immed 0xffffffff,acc1 116 set_accg_immed 0xff,accg2 ; saturation 117 set_acc_immed 0xffffffff,acc2 118 set_accg_immed 0xff,accg3 119 set_acc_immed 0xffffffff,acc3 120 set_fr_iimmed 1,1,fr8 121 set_fr_iimmed 1,1,fr10 122 set_fr_iimmed 1,1,fr9 123 set_fr_iimmed 1,1,fr11 124 cmqmachu fr8,fr10,acc0,cc4,1 125 test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set 126 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 127 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 128 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 129 test_accg_immed 0xff,accg0 130 test_acc_limmed 0xffff,0xffff,acc0 131 test_accg_immed 0xff,accg1 132 test_acc_limmed 0xffff,0xffff,acc1 133 test_accg_immed 0xff,accg2 134 test_acc_limmed 0xffff,0xffff,acc2 135 test_accg_immed 0xff,accg3 136 test_acc_limmed 0xffff,0xffff,acc3 137 138 set_fr_iimmed 0xffff,0x0000,fr8 139 set_fr_iimmed 0xffff,0xffff,fr10 140 set_fr_iimmed 0x0000,0xffff,fr9 141 set_fr_iimmed 0xffff,0xffff,fr11 142 cmqmachu fr8,fr10,acc0,cc4,1 143 test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set 144 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 145 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 146 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 147 test_accg_immed 0xff,accg0 148 test_acc_limmed 0xffff,0xffff,acc0 149 test_accg_immed 0xff,accg1 150 test_acc_limmed 0xffff,0xffff,acc1 151 test_accg_immed 0xff,accg2 152 test_acc_limmed 0xffff,0xffff,acc2 153 test_accg_immed 0xff,accg3 154 test_acc_limmed 0xffff,0xffff,acc3 155 156 set_spr_immed 0,msr0 157 set_spr_immed 0,msr1 158 set_accg_immed 0,accg0 159 set_acc_immed 0,acc0 160 set_accg_immed 0,accg1 161 set_acc_immed 0,acc1 162 set_accg_immed 0,accg2 163 set_acc_immed 0,acc2 164 set_accg_immed 0,accg3 165 set_acc_immed 0,acc3 166 set_fr_iimmed 3,2,fr8 ; multiply small numbers 167 set_fr_iimmed 2,3,fr10 168 set_fr_iimmed 1,2,fr9 ; multiply by 1 169 set_fr_iimmed 2,1,fr11 170 cmqmachu fr8,fr10,acc0,cc1,0 171 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 172 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 173 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 174 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 175 test_accg_immed 0,accg0 176 test_acc_immed 6,acc0 177 test_accg_immed 0,accg1 178 test_acc_immed 6,acc1 179 test_accg_immed 0,accg2 180 test_acc_immed 2,acc2 181 test_accg_immed 0,accg3 182 test_acc_immed 2,acc3 183 184 set_fr_iimmed 0,2,fr8 ; multiply by 0 185 set_fr_iimmed 2,0,fr10 186 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 187 set_fr_iimmed 2,0x3fff,fr11 188 cmqmachu fr8,fr10,acc0,cc1,0 189 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 190 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 191 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 192 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 193 test_accg_immed 0,accg0 194 test_acc_immed 6,acc0 195 test_accg_immed 0,accg1 196 test_acc_immed 6,acc1 197 test_accg_immed 0,accg2 198 test_acc_limmed 0x0000,0x8000,acc2 199 test_accg_immed 0,accg3 200 test_acc_limmed 0x0000,0x8000,acc3 201 202 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 203 set_fr_iimmed 2,0x4000,fr10 204 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 205 set_fr_iimmed 2,0x8000,fr11 206 cmqmachu fr8,fr10,acc0,cc1,0 207 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 208 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 209 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 210 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 211 test_accg_immed 0,accg0 212 test_acc_limmed 0x0000,0x8006,acc0 213 test_accg_immed 0,accg1 214 test_acc_limmed 0x0000,0x8006,acc1 215 test_accg_immed 0,accg2 216 test_acc_immed 0x00018000,acc2 217 test_accg_immed 0,accg3 218 test_acc_immed 0x00018000,acc3 219 220 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 221 set_fr_iimmed 0x7fff,0x7fff,fr10 222 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 223 set_fr_iimmed 0x8000,0x8000,fr11 224 cmqmachu fr8,fr10,acc0,cc5,0 225 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 226 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 227 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 228 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 229 test_accg_immed 0,accg0 230 test_acc_immed 0x3fff8007,acc0 231 test_accg_immed 0,accg1 232 test_acc_immed 0x3fff8007,acc1 233 test_accg_immed 0,accg2 234 test_acc_limmed 0x4001,0x8000,acc2 235 test_accg_immed 0,accg3 236 test_acc_limmed 0x4001,0x8000,acc3 237 238 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 239 set_fr_iimmed 0xffff,0xffff,fr10 240 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 241 set_fr_iimmed 0xffff,0xffff,fr11 242 cmqmachu fr8,fr10,acc0,cc5,0 243 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 244 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 245 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 246 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 247 test_accg_immed 1,accg0 248 test_acc_limmed 0x3ffd,0x8008,acc0 249 test_accg_immed 1,accg1 250 test_acc_limmed 0x3ffd,0x8008,acc1 251 test_accg_immed 1,accg2 252 test_acc_limmed 0x3fff,0x8001,acc2 253 test_accg_immed 1,accg3 254 test_acc_limmed 0x3fff,0x8001,acc3 255 256 set_accg_immed 0xff,accg0 ; saturation 257 set_acc_immed 0xffffffff,acc0 258 set_accg_immed 0xff,accg1 259 set_acc_immed 0xffffffff,acc1 260 set_accg_immed 0xff,accg2 ; saturation 261 set_acc_immed 0xffffffff,acc2 262 set_accg_immed 0xff,accg3 263 set_acc_immed 0xffffffff,acc3 264 set_fr_iimmed 1,1,fr8 265 set_fr_iimmed 1,1,fr10 266 set_fr_iimmed 1,1,fr9 267 set_fr_iimmed 1,1,fr11 268 cmqmachu fr8,fr10,acc0,cc5,0 269 test_spr_bits 0x3c,2,0xf,msr0 ; msr0.sie is set 270 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 271 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 272 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 273 test_accg_immed 0xff,accg0 274 test_acc_limmed 0xffff,0xffff,acc0 275 test_accg_immed 0xff,accg1 276 test_acc_limmed 0xffff,0xffff,acc1 277 test_accg_immed 0xff,accg2 278 test_acc_limmed 0xffff,0xffff,acc2 279 test_accg_immed 0xff,accg3 280 test_acc_limmed 0xffff,0xffff,acc3 281 282 set_fr_iimmed 0xffff,0x0000,fr8 283 set_fr_iimmed 0xffff,0xffff,fr10 284 set_fr_iimmed 0x0000,0xffff,fr9 285 set_fr_iimmed 0xffff,0xffff,fr11 286 cmqmachu fr8,fr10,acc0,cc5,0 287 test_spr_bits 0x3c,2,0x9,msr0 ; msr0.sie is set 288 test_spr_bits 2,1,1,msr0 ; msr0.ovf is set 289 test_spr_bits 1,0,1,msr0 ; msr0.aovf is set 290 test_spr_bits 0x7000,12,1,msr0 ; msr0.mtt is set 291 test_accg_immed 0xff,accg0 292 test_acc_limmed 0xffff,0xffff,acc0 293 test_accg_immed 0xff,accg1 294 test_acc_limmed 0xffff,0xffff,acc1 295 test_accg_immed 0xff,accg2 296 test_acc_limmed 0xffff,0xffff,acc2 297 test_accg_immed 0xff,accg3 298 test_acc_limmed 0xffff,0xffff,acc3 299 300 set_spr_immed 0,msr0 301 set_spr_immed 0,msr1 302 set_accg_immed 0x00000011,accg0 303 set_acc_immed 0x11111111,acc0 304 set_accg_immed 0x00000022,accg1 305 set_acc_immed 0x22222222,acc1 306 set_accg_immed 0x00000033,accg2 307 set_acc_immed 0x33333333,acc2 308 set_accg_immed 0x00000044,accg3 309 set_acc_immed 0x44444444,acc3 310 set_fr_iimmed 3,2,fr8 ; multiply small numbers 311 set_fr_iimmed 2,3,fr10 312 set_fr_iimmed 1,2,fr9 ; multiply by 1 313 set_fr_iimmed 2,1,fr11 314 cmqmachu fr8,fr10,acc0,cc0,0 315 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 316 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 317 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 318 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 319 test_accg_immed 0x00000011,accg0 320 test_acc_immed 0x11111111,acc0 321 test_accg_immed 0x00000022,accg1 322 test_acc_immed 0x22222222,acc1 323 test_accg_immed 0x00000033,accg2 324 test_acc_immed 0x33333333,acc2 325 test_accg_immed 0x00000044,accg3 326 test_acc_immed 0x44444444,acc3 327 328 set_fr_iimmed 0,2,fr8 ; multiply by 0 329 set_fr_iimmed 2,0,fr10 330 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 331 set_fr_iimmed 2,0x3fff,fr11 332 cmqmachu fr8,fr10,acc0,cc0,0 333 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 334 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 335 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 336 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 337 test_accg_immed 0x00000011,accg0 338 test_acc_immed 0x11111111,acc0 339 test_accg_immed 0x00000022,accg1 340 test_acc_immed 0x22222222,acc1 341 test_accg_immed 0x00000033,accg2 342 test_acc_immed 0x33333333,acc2 343 test_accg_immed 0x00000044,accg3 344 test_acc_immed 0x44444444,acc3 345 346 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 347 set_fr_iimmed 2,0x4000,fr10 348 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 349 set_fr_iimmed 2,0x8000,fr11 350 cmqmachu fr8,fr10,acc0,cc0,0 351 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 352 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 353 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 354 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 355 test_accg_immed 0x00000011,accg0 356 test_acc_immed 0x11111111,acc0 357 test_accg_immed 0x00000022,accg1 358 test_acc_immed 0x22222222,acc1 359 test_accg_immed 0x00000033,accg2 360 test_acc_immed 0x33333333,acc2 361 test_accg_immed 0x00000044,accg3 362 test_acc_immed 0x44444444,acc3 363 364 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 365 set_fr_iimmed 0x7fff,0x7fff,fr10 366 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 367 set_fr_iimmed 0x8000,0x8000,fr11 368 cmqmachu fr8,fr10,acc0,cc4,0 369 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 370 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 371 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 372 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 373 test_accg_immed 0x00000011,accg0 374 test_acc_immed 0x11111111,acc0 375 test_accg_immed 0x00000022,accg1 376 test_acc_immed 0x22222222,acc1 377 test_accg_immed 0x00000033,accg2 378 test_acc_immed 0x33333333,acc2 379 test_accg_immed 0x00000044,accg3 380 test_acc_immed 0x44444444,acc3 381 382 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 383 set_fr_iimmed 0xffff,0xffff,fr10 384 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 385 set_fr_iimmed 0xffff,0xffff,fr11 386 cmqmachu fr8,fr10,acc0,cc4,0 387 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 388 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 389 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 390 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 391 test_accg_immed 0x00000011,accg0 392 test_acc_immed 0x11111111,acc0 393 test_accg_immed 0x00000022,accg1 394 test_acc_immed 0x22222222,acc1 395 test_accg_immed 0x00000033,accg2 396 test_acc_immed 0x33333333,acc2 397 test_accg_immed 0x00000044,accg3 398 test_acc_immed 0x44444444,acc3 399 400 set_accg_immed 0xff,accg0 ; saturation 401 set_acc_immed 0xffffffff,acc0 402 set_accg_immed 0xff,accg1 403 set_acc_immed 0xffffffff,acc1 404 set_accg_immed 0xff,accg2 ; saturation 405 set_acc_immed 0xffffffff,acc2 406 set_accg_immed 0xff,accg3 407 set_acc_immed 0xffffffff,acc3 408 set_fr_iimmed 1,1,fr8 409 set_fr_iimmed 1,1,fr10 410 set_fr_iimmed 1,1,fr9 411 set_fr_iimmed 1,1,fr11 412 cmqmachu fr8,fr10,acc0,cc4,0 413 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 414 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 415 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 416 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 417 test_accg_immed 0xff,accg0 ; saturation 418 test_acc_immed 0xffffffff,acc0 419 test_accg_immed 0xff,accg1 420 test_acc_immed 0xffffffff,acc1 421 test_accg_immed 0xff,accg2 ; saturation 422 test_acc_immed 0xffffffff,acc2 423 test_accg_immed 0xff,accg3 424 test_acc_immed 0xffffffff,acc3 425 426 set_fr_iimmed 0xffff,0x0000,fr8 427 set_fr_iimmed 0xffff,0xffff,fr10 428 set_fr_iimmed 0x0000,0xffff,fr9 429 set_fr_iimmed 0xffff,0xffff,fr11 430 cmqmachu fr8,fr10,acc0,cc4,0 431 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 432 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 433 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 434 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 435 test_accg_immed 0xff,accg0 ; saturation 436 test_acc_immed 0xffffffff,acc0 437 test_accg_immed 0xff,accg1 438 test_acc_immed 0xffffffff,acc1 439 test_accg_immed 0xff,accg2 ; saturation 440 test_acc_immed 0xffffffff,acc2 441 test_accg_immed 0xff,accg3 442 test_acc_immed 0xffffffff,acc3 443 444 set_spr_immed 0,msr0 445 set_spr_immed 0,msr1 446 set_accg_immed 0x00000011,accg0 447 set_acc_immed 0x11111111,acc0 448 set_accg_immed 0x00000022,accg1 449 set_acc_immed 0x22222222,acc1 450 set_accg_immed 0x00000033,accg2 451 set_acc_immed 0x33333333,acc2 452 set_accg_immed 0x00000044,accg3 453 set_acc_immed 0x44444444,acc3 454 set_fr_iimmed 3,2,fr8 ; multiply small numbers 455 set_fr_iimmed 2,3,fr10 456 set_fr_iimmed 1,2,fr9 ; multiply by 1 457 set_fr_iimmed 2,1,fr11 458 cmqmachu fr8,fr10,acc0,cc1,1 459 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 460 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 461 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 462 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 463 test_accg_immed 0x00000011,accg0 464 test_acc_immed 0x11111111,acc0 465 test_accg_immed 0x00000022,accg1 466 test_acc_immed 0x22222222,acc1 467 test_accg_immed 0x00000033,accg2 468 test_acc_immed 0x33333333,acc2 469 test_accg_immed 0x00000044,accg3 470 test_acc_immed 0x44444444,acc3 471 472 set_fr_iimmed 0,2,fr8 ; multiply by 0 473 set_fr_iimmed 2,0,fr10 474 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 475 set_fr_iimmed 2,0x3fff,fr11 476 cmqmachu fr8,fr10,acc0,cc1,1 477 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 478 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 479 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 480 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 481 test_accg_immed 0x00000011,accg0 482 test_acc_immed 0x11111111,acc0 483 test_accg_immed 0x00000022,accg1 484 test_acc_immed 0x22222222,acc1 485 test_accg_immed 0x00000033,accg2 486 test_acc_immed 0x33333333,acc2 487 test_accg_immed 0x00000044,accg3 488 test_acc_immed 0x44444444,acc3 489 490 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 491 set_fr_iimmed 2,0x4000,fr10 492 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 493 set_fr_iimmed 2,0x8000,fr11 494 cmqmachu fr8,fr10,acc0,cc1,1 495 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 496 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 497 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 498 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 499 test_accg_immed 0x00000011,accg0 500 test_acc_immed 0x11111111,acc0 501 test_accg_immed 0x00000022,accg1 502 test_acc_immed 0x22222222,acc1 503 test_accg_immed 0x00000033,accg2 504 test_acc_immed 0x33333333,acc2 505 test_accg_immed 0x00000044,accg3 506 test_acc_immed 0x44444444,acc3 507 508 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 509 set_fr_iimmed 0x7fff,0x7fff,fr10 510 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 511 set_fr_iimmed 0x8000,0x8000,fr11 512 cmqmachu fr8,fr10,acc0,cc5,1 513 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 514 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 515 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 516 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 517 test_accg_immed 0x00000011,accg0 518 test_acc_immed 0x11111111,acc0 519 test_accg_immed 0x00000022,accg1 520 test_acc_immed 0x22222222,acc1 521 test_accg_immed 0x00000033,accg2 522 test_acc_immed 0x33333333,acc2 523 test_accg_immed 0x00000044,accg3 524 test_acc_immed 0x44444444,acc3 525 526 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 527 set_fr_iimmed 0xffff,0xffff,fr10 528 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 529 set_fr_iimmed 0xffff,0xffff,fr11 530 cmqmachu fr8,fr10,acc0,cc5,1 531 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 532 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 533 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 534 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 535 test_accg_immed 0x00000011,accg0 536 test_acc_immed 0x11111111,acc0 537 test_accg_immed 0x00000022,accg1 538 test_acc_immed 0x22222222,acc1 539 test_accg_immed 0x00000033,accg2 540 test_acc_immed 0x33333333,acc2 541 test_accg_immed 0x00000044,accg3 542 test_acc_immed 0x44444444,acc3 543 544 set_accg_immed 0xff,accg0 ; saturation 545 set_acc_immed 0xffffffff,acc0 546 set_accg_immed 0xff,accg1 547 set_acc_immed 0xffffffff,acc1 548 set_accg_immed 0xff,accg2 ; saturation 549 set_acc_immed 0xffffffff,acc2 550 set_accg_immed 0xff,accg3 551 set_acc_immed 0xffffffff,acc3 552 set_fr_iimmed 1,1,fr8 553 set_fr_iimmed 1,1,fr10 554 set_fr_iimmed 1,1,fr9 555 set_fr_iimmed 1,1,fr11 556 cmqmachu fr8,fr10,acc0,cc5,1 557 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 558 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 559 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 560 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 561 test_accg_immed 0xff,accg0 ; saturation 562 test_acc_immed 0xffffffff,acc0 563 test_accg_immed 0xff,accg1 564 test_acc_immed 0xffffffff,acc1 565 test_accg_immed 0xff,accg2 ; saturation 566 test_acc_immed 0xffffffff,acc2 567 test_accg_immed 0xff,accg3 568 test_acc_immed 0xffffffff,acc3 569 570 set_fr_iimmed 0xffff,0x0000,fr8 571 set_fr_iimmed 0xffff,0xffff,fr10 572 set_fr_iimmed 0x0000,0xffff,fr9 573 set_fr_iimmed 0xffff,0xffff,fr11 574 cmqmachu fr8,fr10,acc0,cc5,1 575 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 576 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 577 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 578 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 579 test_accg_immed 0xff,accg0 ; saturation 580 test_acc_immed 0xffffffff,acc0 581 test_accg_immed 0xff,accg1 582 test_acc_immed 0xffffffff,acc1 583 test_accg_immed 0xff,accg2 ; saturation 584 test_acc_immed 0xffffffff,acc2 585 test_accg_immed 0xff,accg3 586 test_acc_immed 0xffffffff,acc3 587 588 set_spr_immed 0,msr0 589 set_spr_immed 0,msr1 590 set_accg_immed 0x00000011,accg0 591 set_acc_immed 0x11111111,acc0 592 set_accg_immed 0x00000022,accg1 593 set_acc_immed 0x22222222,acc1 594 set_accg_immed 0x00000033,accg2 595 set_acc_immed 0x33333333,acc2 596 set_accg_immed 0x00000044,accg3 597 set_acc_immed 0x44444444,acc3 598 set_fr_iimmed 3,2,fr8 ; multiply small numbers 599 set_fr_iimmed 2,3,fr10 600 set_fr_iimmed 1,2,fr9 ; multiply by 1 601 set_fr_iimmed 2,1,fr11 602 cmqmachu fr8,fr10,acc0,cc2,1 603 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 604 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 605 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 606 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 607 test_accg_immed 0x00000011,accg0 608 test_acc_immed 0x11111111,acc0 609 test_accg_immed 0x00000022,accg1 610 test_acc_immed 0x22222222,acc1 611 test_accg_immed 0x00000033,accg2 612 test_acc_immed 0x33333333,acc2 613 test_accg_immed 0x00000044,accg3 614 test_acc_immed 0x44444444,acc3 615 616 set_fr_iimmed 0,2,fr8 ; multiply by 0 617 set_fr_iimmed 2,0,fr10 618 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 619 set_fr_iimmed 2,0x3fff,fr11 620 cmqmachu fr8,fr10,acc0,cc2,0 621 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 622 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 623 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 624 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 625 test_accg_immed 0x00000011,accg0 626 test_acc_immed 0x11111111,acc0 627 test_accg_immed 0x00000022,accg1 628 test_acc_immed 0x22222222,acc1 629 test_accg_immed 0x00000033,accg2 630 test_acc_immed 0x33333333,acc2 631 test_accg_immed 0x00000044,accg3 632 test_acc_immed 0x44444444,acc3 633 634 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 635 set_fr_iimmed 2,0x4000,fr10 636 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 637 set_fr_iimmed 2,0x8000,fr11 638 cmqmachu fr8,fr10,acc0,cc2,1 639 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 640 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 641 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 642 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 643 test_accg_immed 0x00000011,accg0 644 test_acc_immed 0x11111111,acc0 645 test_accg_immed 0x00000022,accg1 646 test_acc_immed 0x22222222,acc1 647 test_accg_immed 0x00000033,accg2 648 test_acc_immed 0x33333333,acc2 649 test_accg_immed 0x00000044,accg3 650 test_acc_immed 0x44444444,acc3 651 652 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 653 set_fr_iimmed 0x7fff,0x7fff,fr10 654 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 655 set_fr_iimmed 0x8000,0x8000,fr11 656 cmqmachu fr8,fr10,acc0,cc6,0 657 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 658 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 659 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 660 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 661 test_accg_immed 0x00000011,accg0 662 test_acc_immed 0x11111111,acc0 663 test_accg_immed 0x00000022,accg1 664 test_acc_immed 0x22222222,acc1 665 test_accg_immed 0x00000033,accg2 666 test_acc_immed 0x33333333,acc2 667 test_accg_immed 0x00000044,accg3 668 test_acc_immed 0x44444444,acc3 669 670 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 671 set_fr_iimmed 0xffff,0xffff,fr10 672 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 673 set_fr_iimmed 0xffff,0xffff,fr11 674 cmqmachu fr8,fr10,acc0,cc6,1 675 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 676 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 677 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 678 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 679 test_accg_immed 0x00000011,accg0 680 test_acc_immed 0x11111111,acc0 681 test_accg_immed 0x00000022,accg1 682 test_acc_immed 0x22222222,acc1 683 test_accg_immed 0x00000033,accg2 684 test_acc_immed 0x33333333,acc2 685 test_accg_immed 0x00000044,accg3 686 test_acc_immed 0x44444444,acc3 687 688 set_accg_immed 0xff,accg0 ; saturation 689 set_acc_immed 0xffffffff,acc0 690 set_accg_immed 0xff,accg1 691 set_acc_immed 0xffffffff,acc1 692 set_accg_immed 0xff,accg2 ; saturation 693 set_acc_immed 0xffffffff,acc2 694 set_accg_immed 0xff,accg3 695 set_acc_immed 0xffffffff,acc3 696 set_fr_iimmed 1,1,fr8 697 set_fr_iimmed 1,1,fr10 698 set_fr_iimmed 1,1,fr9 699 set_fr_iimmed 1,1,fr11 700 cmqmachu fr8,fr10,acc0,cc6,0 701 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 702 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 703 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 704 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 705 test_accg_immed 0xff,accg0 ; saturation 706 test_acc_immed 0xffffffff,acc0 707 test_accg_immed 0xff,accg1 708 test_acc_immed 0xffffffff,acc1 709 test_accg_immed 0xff,accg2 ; saturation 710 test_acc_immed 0xffffffff,acc2 711 test_accg_immed 0xff,accg3 712 test_acc_immed 0xffffffff,acc3 713 714 set_fr_iimmed 0xffff,0x0000,fr8 715 set_fr_iimmed 0xffff,0xffff,fr10 716 set_fr_iimmed 0x0000,0xffff,fr9 717 set_fr_iimmed 0xffff,0xffff,fr11 718 cmqmachu fr8,fr10,acc0,cc6,1 719 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 720 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 721 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 722 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 723 test_accg_immed 0xff,accg0 ; saturation 724 test_acc_immed 0xffffffff,acc0 725 test_accg_immed 0xff,accg1 726 test_acc_immed 0xffffffff,acc1 727 test_accg_immed 0xff,accg2 ; saturation 728 test_acc_immed 0xffffffff,acc2 729 test_accg_immed 0xff,accg3 730 test_acc_immed 0xffffffff,acc3 731; 732 set_spr_immed 0,msr0 733 set_spr_immed 0,msr1 734 set_accg_immed 0x00000011,accg0 735 set_acc_immed 0x11111111,acc0 736 set_accg_immed 0x00000022,accg1 737 set_acc_immed 0x22222222,acc1 738 set_accg_immed 0x00000033,accg2 739 set_acc_immed 0x33333333,acc2 740 set_accg_immed 0x00000044,accg3 741 set_acc_immed 0x44444444,acc3 742 set_fr_iimmed 3,2,fr8 ; multiply small numbers 743 set_fr_iimmed 2,3,fr10 744 set_fr_iimmed 1,2,fr9 ; multiply by 1 745 set_fr_iimmed 2,1,fr11 746 cmqmachu fr8,fr10,acc0,cc3,1 747 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 748 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 749 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 750 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 751 test_accg_immed 0x00000011,accg0 752 test_acc_immed 0x11111111,acc0 753 test_accg_immed 0x00000022,accg1 754 test_acc_immed 0x22222222,acc1 755 test_accg_immed 0x00000033,accg2 756 test_acc_immed 0x33333333,acc2 757 test_accg_immed 0x00000044,accg3 758 test_acc_immed 0x44444444,acc3 759 760 set_fr_iimmed 0,2,fr8 ; multiply by 0 761 set_fr_iimmed 2,0,fr10 762 set_fr_iimmed 0x3fff,2,fr9 ; 15 bit result 763 set_fr_iimmed 2,0x3fff,fr11 764 cmqmachu fr8,fr10,acc0,cc3,0 765 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 766 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 767 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 768 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 769 test_accg_immed 0x00000011,accg0 770 test_acc_immed 0x11111111,acc0 771 test_accg_immed 0x00000022,accg1 772 test_acc_immed 0x22222222,acc1 773 test_accg_immed 0x00000033,accg2 774 test_acc_immed 0x33333333,acc2 775 test_accg_immed 0x00000044,accg3 776 test_acc_immed 0x44444444,acc3 777 778 set_fr_iimmed 0x4000,2,fr8 ; 16 bit result 779 set_fr_iimmed 2,0x4000,fr10 780 set_fr_iimmed 0x8000,2,fr9 ; 17 bit result 781 set_fr_iimmed 2,0x8000,fr11 782 cmqmachu fr8,fr10,acc0,cc3,1 783 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 784 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 785 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 786 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 787 test_accg_immed 0x00000011,accg0 788 test_acc_immed 0x11111111,acc0 789 test_accg_immed 0x00000022,accg1 790 test_acc_immed 0x22222222,acc1 791 test_accg_immed 0x00000033,accg2 792 test_acc_immed 0x33333333,acc2 793 test_accg_immed 0x00000044,accg3 794 test_acc_immed 0x44444444,acc3 795 796 set_fr_iimmed 0x7fff,0x7fff,fr8 ; max positive result 797 set_fr_iimmed 0x7fff,0x7fff,fr10 798 set_fr_iimmed 0x8000,0x8000,fr9 ; max positive result 799 set_fr_iimmed 0x8000,0x8000,fr11 800 cmqmachu fr8,fr10,acc0,cc7,0 801 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 802 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 803 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 804 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 805 test_accg_immed 0x00000011,accg0 806 test_acc_immed 0x11111111,acc0 807 test_accg_immed 0x00000022,accg1 808 test_acc_immed 0x22222222,acc1 809 test_accg_immed 0x00000033,accg2 810 test_acc_immed 0x33333333,acc2 811 test_accg_immed 0x00000044,accg3 812 test_acc_immed 0x44444444,acc3 813 814 set_fr_iimmed 0xffff,0xffff,fr8 ; max positive result 815 set_fr_iimmed 0xffff,0xffff,fr10 816 set_fr_iimmed 0xffff,0xffff,fr9 ; max positive result 817 set_fr_iimmed 0xffff,0xffff,fr11 818 cmqmachu fr8,fr10,acc0,cc7,1 819 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 820 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 821 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 822 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 823 test_accg_immed 0x00000011,accg0 824 test_acc_immed 0x11111111,acc0 825 test_accg_immed 0x00000022,accg1 826 test_acc_immed 0x22222222,acc1 827 test_accg_immed 0x00000033,accg2 828 test_acc_immed 0x33333333,acc2 829 test_accg_immed 0x00000044,accg3 830 test_acc_immed 0x44444444,acc3 831 832 set_accg_immed 0xff,accg0 ; saturation 833 set_acc_immed 0xffffffff,acc0 834 set_accg_immed 0xff,accg1 835 set_acc_immed 0xffffffff,acc1 836 set_accg_immed 0xff,accg2 ; saturation 837 set_acc_immed 0xffffffff,acc2 838 set_accg_immed 0xff,accg3 839 set_acc_immed 0xffffffff,acc3 840 set_fr_iimmed 1,1,fr8 841 set_fr_iimmed 1,1,fr10 842 set_fr_iimmed 1,1,fr9 843 set_fr_iimmed 1,1,fr11 844 cmqmachu fr8,fr10,acc0,cc7,0 845 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 846 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 847 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 848 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 849 test_accg_immed 0xff,accg0 ; saturation 850 test_acc_immed 0xffffffff,acc0 851 test_accg_immed 0xff,accg1 852 test_acc_immed 0xffffffff,acc1 853 test_accg_immed 0xff,accg2 ; saturation 854 test_acc_immed 0xffffffff,acc2 855 test_accg_immed 0xff,accg3 856 test_acc_immed 0xffffffff,acc3 857 858 set_fr_iimmed 0xffff,0x0000,fr8 859 set_fr_iimmed 0xffff,0xffff,fr10 860 set_fr_iimmed 0x0000,0xffff,fr9 861 set_fr_iimmed 0xffff,0xffff,fr11 862 cmqmachu fr8,fr10,acc0,cc7,1 863 test_spr_bits 0x3c,2,0,msr0 ; msr0.sie is clear 864 test_spr_bits 2,1,0,msr0 ; msr0.ovf not set 865 test_spr_bits 1,0,0,msr0 ; msr0.aovf not set 866 test_spr_bits 0x7000,12,0,msr0 ; msr0.mtt not set 867 test_accg_immed 0xff,accg0 ; saturation 868 test_acc_immed 0xffffffff,acc0 869 test_accg_immed 0xff,accg1 870 test_acc_immed 0xffffffff,acc1 871 test_accg_immed 0xff,accg2 ; saturation 872 test_acc_immed 0xffffffff,acc2 873 test_accg_immed 0xff,accg3 874 test_acc_immed 0xffffffff,acc3 875 876 pass 877