1# frv testcase for csll $GRi,$GRj,$GRk,$CCi,$cond 2# mach: all 3 4 .include "testutils.inc" 5 6 start 7 8 .global csll 9csll: 10 set_spr_immed 0x1b1b,cccr 11 12 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 13 set_gr_immed 2,gr8 14 set_icc 0x0d,0 ; Set mask opposite of expected 15 csll gr8,gr7,gr8,cc0,1 16 test_icc 1 1 0 1 icc0 17 test_gr_immed 2,gr8 18 19 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 20 set_gr_immed 2,gr8 21 set_icc 0x0f,0 ; Set mask opposite of expected 22 csll gr8,gr7,gr8,cc0,1 23 test_icc 1 1 1 1 icc0 24 test_gr_immed 4,gr8 25 26 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 27 set_gr_immed 1,gr8 28 set_icc 0x07,0 ; Set mask opposite of expected 29 csll gr8,gr7,gr8,cc4,1 30 test_icc 0 1 1 1 icc0 31 test_gr_limmed 0x8000,0x0000,gr8 32 33 set_gr_limmed 0xdead,0xbeff,gr7 ; clear register 34 set_gr_immed 2,gr8 35 set_icc 0x0a,0 ; Set mask opposite of expected 36 csll gr8,gr7,gr8,cc4,1 37 test_icc 1 0 1 0 icc0 38 test_gr_immed 0x00000000,gr8 39 40 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 41 set_gr_immed 2,gr8 42 set_icc 0x0d,0 ; Set mask opposite of expected 43 csll gr8,gr7,gr8,cc0,0 44 test_icc 1 1 0 1 icc0 45 test_gr_immed 2,gr8 46 47 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 48 set_gr_immed 2,gr8 49 set_icc 0x0f,0 ; Set mask opposite of expected 50 csll gr8,gr7,gr8,cc0,0 51 test_icc 1 1 1 1 icc0 52 test_gr_immed 2,gr8 53 54 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 55 set_gr_immed 1,gr8 56 set_icc 0x07,0 ; Set mask opposite of expected 57 csll gr8,gr7,gr8,cc4,0 58 test_icc 0 1 1 1 icc0 59 test_gr_immed 1,gr8 60 61 set_gr_limmed 0xdead,0xbeff,gr7 ; clear register 62 set_gr_immed 2,gr8 63 set_icc 0x0a,0 ; Set mask opposite of expected 64 csll gr8,gr7,gr8,cc4,0 65 test_icc 1 0 1 0 icc0 66 test_gr_immed 2,gr8 67 68 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 69 set_gr_immed 2,gr8 70 set_icc 0x0d,1 ; Set mask opposite of expected 71 csll gr8,gr7,gr8,cc1,0 72 test_icc 1 1 0 1 icc1 73 test_gr_immed 2,gr8 74 75 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 76 set_gr_immed 2,gr8 77 set_icc 0x0f,1 ; Set mask opposite of expected 78 csll gr8,gr7,gr8,cc1,0 79 test_icc 1 1 1 1 icc1 80 test_gr_immed 4,gr8 81 82 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 83 set_gr_immed 1,gr8 84 set_icc 0x07,1 ; Set mask opposite of expected 85 csll gr8,gr7,gr8,cc5,0 86 test_icc 0 1 1 1 icc1 87 test_gr_limmed 0x8000,0x0000,gr8 88 89 set_gr_limmed 0xdead,0xbeff,gr7 ; clear register 90 set_gr_immed 2,gr8 91 set_icc 0x0a,1 ; Set mask opposite of expected 92 csll gr8,gr7,gr8,cc5,0 93 test_icc 1 0 1 0 icc1 94 test_gr_immed 0x00000000,gr8 95 96 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 97 set_gr_immed 2,gr8 98 set_icc 0x0d,1 ; Set mask opposite of expected 99 csll gr8,gr7,gr8,cc1,1 100 test_icc 1 1 0 1 icc1 101 test_gr_immed 2,gr8 102 103 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 104 set_gr_immed 2,gr8 105 set_icc 0x0f,1 ; Set mask opposite of expected 106 csll gr8,gr7,gr8,cc1,1 107 test_icc 1 1 1 1 icc1 108 test_gr_immed 2,gr8 109 110 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 111 set_gr_immed 1,gr8 112 set_icc 0x07,1 ; Set mask opposite of expected 113 csll gr8,gr7,gr8,cc5,1 114 test_icc 0 1 1 1 icc1 115 test_gr_immed 1,gr8 116 117 set_gr_limmed 0xdead,0xbeff,gr7 ; clear register 118 set_gr_immed 2,gr8 119 set_icc 0x0a,1 ; Set mask opposite of expected 120 csll gr8,gr7,gr8,cc5,1 121 test_icc 1 0 1 0 icc1 122 test_gr_immed 2,gr8 123 124 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 125 set_gr_immed 2,gr8 126 set_icc 0x0d,2 ; Set mask opposite of expected 127 csll gr8,gr7,gr8,cc2,0 128 test_icc 1 1 0 1 icc2 129 test_gr_immed 2,gr8 130 131 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 132 set_gr_immed 2,gr8 133 set_icc 0x0f,2 ; Set mask opposite of expected 134 csll gr8,gr7,gr8,cc2,0 135 test_icc 1 1 1 1 icc2 136 test_gr_immed 2,gr8 137 138 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 139 set_gr_immed 1,gr8 140 set_icc 0x07,2 ; Set mask opposite of expected 141 csll gr8,gr7,gr8,cc6,1 142 test_icc 0 1 1 1 icc2 143 test_gr_immed 1,gr8 144 145 set_gr_limmed 0xdead,0xbeff,gr7 ; clear register 146 set_gr_immed 2,gr8 147 set_icc 0x0a,2 ; Set mask opposite of expected 148 csll gr8,gr7,gr8,cc6,1 149 test_icc 1 0 1 0 icc2 150 test_gr_immed 2,gr8 151 152 set_gr_limmed 0xdead,0xbee0,gr7 ; Shift by 0 153 set_gr_immed 2,gr8 154 set_icc 0x0d,3 ; Set mask opposite of expected 155 csll gr8,gr7,gr8,cc3,0 156 test_icc 1 1 0 1 icc3 157 test_gr_immed 2,gr8 158 159 set_gr_limmed 0xdead,0xbee1,gr7 ; Shift by 1 160 set_gr_immed 2,gr8 161 set_icc 0x0f,3 ; Set mask opposite of expected 162 csll gr8,gr7,gr8,cc3,0 163 test_icc 1 1 1 1 icc3 164 test_gr_immed 2,gr8 165 166 set_gr_limmed 0xdead,0xbeff,gr7 ; Shift by 31 167 set_gr_immed 1,gr8 168 set_icc 0x07,3 ; Set mask opposite of expected 169 csll gr8,gr7,gr8,cc7,1 170 test_icc 0 1 1 1 icc3 171 test_gr_immed 1,gr8 172 173 set_gr_limmed 0xdead,0xbeff,gr7 ; clear register 174 set_gr_immed 2,gr8 175 set_icc 0x0a,3 ; Set mask opposite of expected 176 csll gr8,gr7,gr8,cc7,1 177 test_icc 1 0 1 0 icc3 178 test_gr_immed 2,gr8 179 180 pass 181