1# frv testcase for fcbgelr $FCCi,$ccond,$hint 2# mach: all 3 4 .include "testutils.inc" 5 6 start 7 8 .global fcbgelr 9fcbgelr: 10 ; ccond is true 11 set_spr_immed 128,lcr 12 set_spr_addr bad,lr 13 set_fcc 0x0 0 14 fcbgelr fcc0,0,0 15 16 set_spr_addr bad,lr 17 set_fcc 0x1 1 18 fcbgelr fcc1,0,1 19 20 set_spr_addr ok3,lr 21 set_fcc 0x2 2 22 fcbgelr fcc2,0,2 23 fail 24ok3: 25 set_spr_addr ok4,lr 26 set_fcc 0x3 3 27 fcbgelr fcc3,0,3 28 fail 29ok4: 30 set_spr_addr bad,lr 31 set_fcc 0x4 0 32 fcbgelr fcc0,0,0 33 34 set_spr_addr bad,lr 35 set_fcc 0x5 1 36 fcbgelr fcc1,0,1 37 38 set_spr_addr ok7,lr 39 set_fcc 0x6 2 40 fcbgelr fcc2,0,2 41 fail 42ok7: 43 set_spr_addr ok8,lr 44 set_fcc 0x7 3 45 fcbgelr fcc3,0,3 46 fail 47ok8: 48 set_spr_addr ok9,lr 49 set_fcc 0x8 0 50 fcbgelr fcc0,0,0 51 fail 52ok9: 53 set_spr_addr oka,lr 54 set_fcc 0x9 1 55 fcbgelr fcc1,0,1 56 fail 57oka: 58 set_spr_addr okb,lr 59 set_fcc 0xa 2 60 fcbgelr fcc2,0,2 61 fail 62okb: 63 set_spr_addr okc,lr 64 set_fcc 0xb 3 65 fcbgelr fcc3,0,3 66 fail 67okc: 68 set_spr_addr okd,lr 69 set_fcc 0xc 0 70 fcbgelr fcc0,0,0 71 fail 72okd: 73 set_spr_addr oke,lr 74 set_fcc 0xd 1 75 fcbgelr fcc1,0,1 76 fail 77oke: 78 set_spr_addr okf,lr 79 set_fcc 0xe 2 80 fcbgelr fcc2,0,2 81 fail 82okf: 83 set_spr_addr okg,lr 84 set_fcc 0xf 3 85 fcbgelr fcc3,0,3 86 fail 87okg: 88 89 ; ccond is true 90 set_spr_immed 1,lcr 91 set_spr_addr bad,lr 92 set_fcc 0x0 0 93 fcbgelr fcc0,1,0 94 95 set_spr_immed 1,lcr 96 set_spr_addr bad,lr 97 set_fcc 0x1 1 98 fcbgelr fcc1,1,1 99 100 set_spr_immed 1,lcr 101 set_spr_addr okj,lr 102 set_fcc 0x2 2 103 fcbgelr fcc2,1,2 104 fail 105okj: 106 set_spr_immed 1,lcr 107 set_spr_addr okk,lr 108 set_fcc 0x3 3 109 fcbgelr fcc3,1,3 110 fail 111okk: 112 set_spr_immed 1,lcr 113 set_spr_addr bad,lr 114 set_fcc 0x4 0 115 fcbgelr fcc0,1,0 116 117 set_spr_immed 1,lcr 118 set_spr_addr bad,lr 119 set_fcc 0x5 1 120 fcbgelr fcc1,1,1 121 122 set_spr_immed 1,lcr 123 set_spr_addr okn,lr 124 set_fcc 0x6 2 125 fcbgelr fcc2,1,2 126 fail 127okn: 128 set_spr_immed 1,lcr 129 set_spr_addr oko,lr 130 set_fcc 0x7 3 131 fcbgelr fcc3,1,3 132 fail 133oko: 134 set_spr_immed 1,lcr 135 set_spr_addr okp,lr 136 set_fcc 0x8 0 137 fcbgelr fcc0,1,0 138 fail 139okp: 140 set_spr_immed 1,lcr 141 set_spr_addr okq,lr 142 set_fcc 0x9 1 143 fcbgelr fcc1,1,1 144 fail 145okq: 146 set_spr_immed 1,lcr 147 set_spr_addr okr,lr 148 set_fcc 0xa 2 149 fcbgelr fcc2,1,2 150 fail 151okr: 152 set_spr_immed 1,lcr 153 set_spr_addr oks,lr 154 set_fcc 0xb 3 155 fcbgelr fcc3,1,3 156 fail 157oks: 158 set_spr_immed 1,lcr 159 set_spr_addr okt,lr 160 set_fcc 0xc 0 161 fcbgelr fcc0,1,0 162 fail 163okt: 164 set_spr_immed 1,lcr 165 set_spr_addr oku,lr 166 set_fcc 0xd 1 167 fcbgelr fcc1,1,1 168 fail 169oku: 170 set_spr_immed 1,lcr 171 set_spr_addr okv,lr 172 set_fcc 0xe 2 173 fcbgelr fcc2,1,2 174 fail 175okv: 176 set_spr_immed 1,lcr 177 set_spr_addr okw,lr 178 set_fcc 0xf 3 179 fcbgelr fcc3,1,3 180 fail 181okw: 182 ; ccond is false 183 set_spr_immed 128,lcr 184 185 set_fcc 0x0 0 186 fcbgelr fcc0,1,0 187 set_fcc 0x1 1 188 fcbgelr fcc1,1,1 189 set_fcc 0x2 2 190 fcbgelr fcc2,1,2 191 set_fcc 0x3 3 192 fcbgelr fcc3,1,3 193 set_fcc 0x4 0 194 fcbgelr fcc0,1,0 195 set_fcc 0x5 1 196 fcbgelr fcc1,1,1 197 set_fcc 0x6 2 198 fcbgelr fcc2,1,2 199 set_fcc 0x7 3 200 fcbgelr fcc3,1,3 201 set_fcc 0x8 0 202 fcbgelr fcc0,1,0 203 set_fcc 0x9 1 204 fcbgelr fcc1,1,1 205 set_fcc 0xa 2 206 fcbgelr fcc2,1,2 207 set_fcc 0xb 3 208 fcbgelr fcc3,1,3 209 set_fcc 0xc 0 210 fcbgelr fcc0,1,0 211 set_fcc 0xd 1 212 fcbgelr fcc1,1,1 213 set_fcc 0xe 2 214 fcbgelr fcc2,1,2 215 set_fcc 0xf 3 216 fcbgelr fcc3,1,3 217 218 ; ccond is false 219 set_spr_immed 1,lcr 220 set_fcc 0x0 0 221 fcbgelr fcc0,0,0 222 set_spr_immed 1,lcr 223 set_fcc 0x1 1 224 fcbgelr fcc1,0,1 225 set_spr_immed 1,lcr 226 set_fcc 0x2 2 227 fcbgelr fcc2,0,2 228 set_spr_immed 1,lcr 229 set_fcc 0x3 3 230 fcbgelr fcc3,0,3 231 set_spr_immed 1,lcr 232 set_fcc 0x4 0 233 fcbgelr fcc0,0,0 234 set_spr_immed 1,lcr 235 set_fcc 0x5 1 236 fcbgelr fcc1,0,1 237 set_spr_immed 1,lcr 238 set_fcc 0x6 2 239 fcbgelr fcc2,0,2 240 set_spr_immed 1,lcr 241 set_fcc 0x7 3 242 fcbgelr fcc3,0,3 243 set_spr_immed 1,lcr 244 set_fcc 0x8 0 245 fcbgelr fcc0,0,0 246 set_spr_immed 1,lcr 247 set_fcc 0x9 1 248 fcbgelr fcc1,0,1 249 set_spr_immed 1,lcr 250 set_fcc 0xa 2 251 fcbgelr fcc2,0,2 252 set_spr_immed 1,lcr 253 set_fcc 0xb 3 254 fcbgelr fcc3,0,3 255 set_spr_immed 1,lcr 256 set_fcc 0xc 0 257 fcbgelr fcc0,0,0 258 set_spr_immed 1,lcr 259 set_fcc 0xd 1 260 fcbgelr fcc1,0,1 261 set_spr_immed 1,lcr 262 set_fcc 0xe 2 263 fcbgelr fcc2,0,2 264 set_spr_immed 1,lcr 265 set_fcc 0xf 3 266 fcbgelr fcc3,0,3 267 268 pass 269bad: 270 fail 271