1# frv testcase for ftgt $FCCi_2,$GRi,$GRj
2# mach: all
3
4	.include "testutils.inc"
5
6	start
7
8	.global ftgt
9ftgt:
10	and_spr_immed	-4081,tbr		; clear tbr.tt
11	set_gr_spr	tbr,gr7
12	inc_gr_immed	2112,gr7		; address of exception handler
13	set_bctrlr_0_0	gr7	; bctrlr 0,0
14
15	set_spr_immed	128,lcr
16	set_gr_immed	0,gr7
17	set_gr_immed	4,gr8
18
19	set_spr_addr	bad,lr
20	set_fcc		0x0 0
21	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
22
23	set_spr_addr	bad,lr
24	set_fcc		0x1 0
25	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
26
27	set_psr_et	1
28	set_spr_addr	ok2,lr
29	set_fcc		0x2 0
30	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
31	fail
32ok2:
33	set_psr_et	1
34	set_spr_addr	ok3,lr
35	set_fcc		0x3 0
36	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
37	fail
38ok3:
39	set_spr_addr	bad,lr
40	set_fcc		0x4 0
41	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
42
43	set_spr_addr	bad,lr
44	set_fcc		0x5 0
45	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
46
47	set_psr_et	1
48	set_spr_addr	ok6,lr
49	set_fcc		0x6 0
50	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
51	fail
52ok6:
53	set_psr_et	1
54	set_spr_addr	ok7,lr
55	set_fcc		0x7 0
56	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
57	fail
58ok7:
59	set_spr_addr	bad,lr
60	set_fcc		0x8 0
61	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
62
63	set_spr_addr	bad,lr
64	set_fcc		0x9 0
65	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
66
67	set_psr_et	1
68	set_spr_addr	oka,lr
69	set_fcc		0xa 0
70	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
71	fail
72oka:
73	set_psr_et	1
74	set_spr_addr	okb,lr
75	set_fcc		0xb 0
76	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
77	fail
78okb:
79	set_spr_addr	bad,lr
80	set_fcc		0xc 0
81	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
82
83	set_spr_addr	bad,lr
84	set_fcc		0xd 0
85	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
86
87	set_psr_et	1
88	set_spr_addr	oke,lr
89	set_fcc		0xe 0
90	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
91	fail
92oke:
93	set_psr_et	1
94	set_spr_addr	okf,lr
95	set_fcc		0xf 0
96	ftgt 		fcc0,gr7,gr8	; should branch to tbr + (128 + 4)*16
97	fail
98okf:
99	pass
100bad:
101	fail
102