1# frv testcase for ftile $FCCi_2,$GRi,$s12 2# mach: all 3 4 .include "testutils.inc" 5 6 start 7 8 .global ftile 9ftile: 10 and_spr_immed -4081,tbr ; clear tbr.tt 11 set_gr_spr tbr,gr7 12 inc_gr_immed 2112,gr7 ; address of exception handler 13 set_bctrlr_0_0 gr7 ; bctrlr 0,0 14 15 set_spr_immed 128,lcr 16 set_gr_immed 0,gr7 17 18 set_spr_addr bad,lr 19 set_fcc 0x0 0 20 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 21 22 set_spr_addr bad,lr 23 set_fcc 0x1 0 24 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 25 26 set_spr_addr bad,lr 27 set_fcc 0x2 0 28 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 29 30 set_spr_addr bad,lr 31 set_fcc 0x3 0 32 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 33 34 set_psr_et 1 35 set_spr_addr ok4,lr 36 set_fcc 0x4 0 37 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 38 fail 39ok4: 40 set_psr_et 1 41 set_spr_addr ok5,lr 42 set_fcc 0x5 0 43 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 44 fail 45ok5: 46 set_psr_et 1 47 set_spr_addr ok6,lr 48 set_fcc 0x6 0 49 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 50 fail 51ok6: 52 set_psr_et 1 53 set_spr_addr ok7,lr 54 set_fcc 0x7 0 55 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 56 fail 57ok7: 58 set_psr_et 1 59 set_spr_addr ok8,lr 60 set_fcc 0x8 0 61 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 62 fail 63ok8: 64 set_psr_et 1 65 set_spr_addr ok9,lr 66 set_fcc 0x9 0 67 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 68 fail 69ok9: 70 set_psr_et 1 71 set_spr_addr oka,lr 72 set_fcc 0xa 0 73 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 74 fail 75oka: 76 set_psr_et 1 77 set_spr_addr okb,lr 78 set_fcc 0xb 0 79 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 80 fail 81okb: 82 set_psr_et 1 83 set_spr_addr okc,lr 84 set_fcc 0xc 0 85 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 86 fail 87okc: 88 set_psr_et 1 89 set_spr_addr okd,lr 90 set_fcc 0xd 0 91 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 92 fail 93okd: 94 set_psr_et 1 95 set_spr_addr oke,lr 96 set_fcc 0xe 0 97 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 98 fail 99oke: 100 set_psr_et 1 101 set_spr_addr okf,lr 102 set_fcc 0xf 0 103 ftile fcc0,gr7,4 ; should branch to tbr + (128 + 4)*16 104 fail 105okf: 106 pass 107bad: 108 fail 109