1# frv testcase for ftra $GRi,$GRj
2# mach: all
3
4	.include "testutils.inc"
5
6	start
7
8	.global ftra
9ftra:
10	and_spr_immed	-4081,tbr		; clear tbr.tt
11	set_gr_spr	tbr,gr7
12	inc_gr_immed	2112,gr7		; address of exception handler
13	set_bctrlr_0_0	gr7	; bctrlr 0,0
14
15	set_spr_immed	128,lcr
16	set_gr_immed	0,gr7
17	set_gr_immed	4,gr8
18
19	set_psr_et	1
20	set_spr_addr	ok0,lr
21	set_fcc		0x0 0
22	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
23	fail
24ok0:
25	set_psr_et	1
26	set_spr_addr	ok1,lr
27	set_fcc		0x1 0
28	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
29	fail
30ok1:
31	set_psr_et	1
32	set_spr_addr	ok2,lr
33	set_fcc		0x2 0
34	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
35	fail
36ok2:
37	set_psr_et	1
38	set_spr_addr	ok3,lr
39	set_fcc		0x3 0
40	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
41	fail
42ok3:
43	set_psr_et	1
44	set_spr_addr	ok4,lr
45	set_fcc		0x4 0
46	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
47	fail
48ok4:
49	set_psr_et	1
50	set_spr_addr	ok5,lr
51	set_fcc		0x5 0
52	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
53	fail
54ok5:
55	set_psr_et	1
56	set_spr_addr	ok6,lr
57	set_fcc		0x6 0
58	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
59	fail
60ok6:
61	set_psr_et	1
62	set_spr_addr	ok7,lr
63	set_fcc		0x7 0
64	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
65	fail
66ok7:
67	set_psr_et	1
68	set_spr_addr	ok8,lr
69	set_fcc		0x8 0
70	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
71	fail
72ok8:
73	set_psr_et	1
74	set_spr_addr	ok9,lr
75	set_fcc		0x9 0
76	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
77	fail
78ok9:
79	set_psr_et	1
80	set_spr_addr	oka,lr
81	set_fcc		0xa 0
82	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
83	fail
84oka:
85	set_psr_et	1
86	set_spr_addr	okb,lr
87	set_fcc		0xb 0
88	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
89	fail
90okb:
91	set_psr_et	1
92	set_spr_addr	okc,lr
93	set_fcc		0xc 0
94	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
95	fail
96okc:
97	set_psr_et	1
98	set_spr_addr	okd,lr
99	set_fcc		0xd 0
100	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
101	fail
102okd:
103	set_psr_et	1
104	set_spr_addr	oke,lr
105	set_fcc		0xe 0
106	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
107	fail
108oke:
109	set_psr_et	1
110	set_spr_addr	okf,lr
111	set_fcc		0xf 0
112	ftra 		gr7,gr8	; should branch to tbr + (128 + 4)*16
113	fail
114okf:
115	pass
116