1# frv testcase for mmachu $GRi,$GRj,$GRk
2# mach: frv fr500 fr400
3
4	.include "testutils.inc"
5
6	start
7
8	.global mmachu
9mmachu:
10	set_fr_iimmed  	3,2,fr7		; multiply small numbers
11	set_fr_iimmed  	2,3,fr8
12	mmachu      	fr7,fr8,acc0
13	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
14	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
15	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
16	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
17	test_accg_immed 	0,accg0
18	test_acc_immed 	6,acc0
19	test_accg_immed 	0,accg1
20	test_acc_immed 	6,acc1
21
22	set_fr_iimmed  	1,2,fr7		; multiply by 1
23	set_fr_iimmed  	2,1,fr8
24	mmachu      	fr7,fr8,acc0
25	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
26	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
27	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
28	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
29	test_accg_immed 	0,accg0
30	test_acc_immed 	8,acc0
31	test_accg_immed 	0,accg1
32	test_acc_immed 	8,acc1
33
34	set_fr_iimmed  	0,2,fr7		; multiply by 0
35	set_fr_iimmed  	2,0,fr8
36	mmachu      	fr7,fr8,acc0
37	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
38	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
39	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
40	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
41	test_accg_immed 	0,accg0
42	test_acc_immed 	8,acc0
43	test_accg_immed 	0,accg1
44	test_acc_immed 	8,acc1
45
46	set_fr_iimmed 	0x3fff,2,fr7	; 15 bit result
47	set_fr_iimmed  	2,0x3fff,fr8
48	mmachu      	fr7,fr8,acc0
49	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
50	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
51	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
52	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
53	test_accg_immed 	0,accg0
54	test_acc_limmed	0x0000,0x8006,acc0
55	test_accg_immed 	0,accg1
56	test_acc_limmed	0x0000,0x8006,acc1
57
58	set_fr_iimmed  	0x4000,2,fr7	; 16 bit result
59	set_fr_iimmed  	2,0x4000,fr8
60	mmachu      	fr7,fr8,acc0
61	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
62	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
63	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
64	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
65	test_accg_immed 	0,accg0
66	test_acc_limmed	0x0001,0x0006,acc0
67	test_accg_immed 	0,accg1
68	test_acc_limmed	0x0001,0x0006,acc1
69
70	set_fr_iimmed  	0x8000,2,fr7	; 17 bit result
71	set_fr_iimmed  	2,0x8000,fr8
72	mmachu      	fr7,fr8,acc0
73	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
74	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
75	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
76	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
77	test_accg_immed 	0,accg0
78	test_acc_immed 	0x00020006,acc0
79	test_accg_immed 	0,accg1
80	test_acc_immed 	0x00020006,acc1
81
82	set_fr_iimmed  	0x7fff,0x7fff,fr7	; max positive result
83	set_fr_iimmed  	0x7fff,0x7fff,fr8
84	mmachu      	fr7,fr8,acc0
85	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
86	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
87	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
88	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
89	test_accg_immed 	0,accg0
90	test_acc_immed 	0x40010007,acc0
91	test_accg_immed 	0,accg1
92	test_acc_immed 	0x40010007,acc1
93
94	set_fr_iimmed  	0x8000,0x8000,fr7	; max positive result
95	set_fr_iimmed  	0x8000,0x8000,fr8
96	mmachu      	fr7,fr8,acc0
97	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
98	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
99	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
100	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
101	test_accg_immed 	0,accg0
102	test_acc_limmed	0x8001,0x0007,acc0
103	test_accg_immed 	0,accg1
104	test_acc_limmed	0x8001,0x0007,acc1
105
106	set_fr_iimmed  	0xffff,0xffff,fr7	; max positive result
107	set_fr_iimmed  	0xffff,0xffff,fr8
108	mmachu      	fr7,fr8,acc0
109	test_spr_bits	0x3c,2,0,msr0		; msr0.sie is clear
110	test_spr_bits	2,1,0,msr0		; msr0.ovf not set
111	test_spr_bits	1,0,0,msr0		; msr0.aovf not set
112	test_spr_bits	0x7000,12,0,msr0	; msr0.mtt not set
113	test_accg_immed 	1,accg0
114	test_acc_limmed	0x7fff,0x0008,acc0
115	test_accg_immed 	1,accg1
116	test_acc_limmed	0x7fff,0x0008,acc1
117
118	set_accg_immed 	0xff,accg0		; saturation
119	set_acc_immed	0xffffffff,acc0
120	set_accg_immed 	0xff,accg1
121	set_acc_immed	0xffffffff,acc1
122	set_fr_iimmed  	1,1,fr7
123	set_fr_iimmed  	1,1,fr8
124	mmachu      	fr7,fr8,acc0
125	test_spr_bits	0x3c,2,0xc,msr0		; msr0.sie is set
126	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
127	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
128	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
129	test_accg_immed 	0xff,accg0
130	test_acc_limmed	0xffff,0xffff,acc0
131	test_accg_immed 	0xff,accg1
132	test_acc_limmed	0xffff,0xffff,acc1
133
134	set_fr_iimmed  	0xffff,0x0000,fr7
135	set_fr_iimmed  	0xffff,0xffff,fr8
136	mmachu      	fr7,fr8,acc0
137	test_spr_bits	0x3c,2,0x8,msr0		; msr0.sie is set
138	test_spr_bits	2,1,1,msr0		; msr0.ovf is set
139	test_spr_bits	1,0,1,msr0		; msr0.aovf is set
140	test_spr_bits	0x7000,12,1,msr0	; msr0.mtt is set
141	test_accg_immed 	0xff,accg0
142	test_acc_limmed	0xffff,0xffff,acc0
143	test_accg_immed 	0xff,accg1
144	test_acc_limmed	0xffff,0xffff,acc1
145
146	pass
147