1unit mk20d7; 2interface 3{$PACKRECORDS 2} 4{$GOTO ON} 5{$MODESWITCH ADVANCEDRECORDS} 6// ** ################################################################### 7// ** Processors: MK20DX64VLH7 8// ** MK20DX128VLH7 9// ** MK20DX256VLH7 10// ** MK20DX64VLK7 11// ** MK20DX128VLK7 12// ** MK20DX256VLK7 13// ** MK20DX128VLL7 14// ** MK20DX256VLL7 15// ** MK20DX64VMB7 16// ** MK20DX128VMB7 17// ** MK20DX256VMB7 18// ** MK20DX128VML7 19// ** MK20DX256VML7 20// ** 21// ** Compilers: ARM Compiler 22// ** Freescale C/C++ for Embedded ARM 23// ** GNU C Compiler 24// ** IAR ANSI C/C++ Compiler for ARM 25// ** 26// ** Reference manual: Kxx (P1 silicon) Sub-Family Reference Manual Rev. 0, draft A Oct 2011 27// ** Version: rev. 1.0, 2012-01-15 28// ** 29// ** Abstract: 30// ** CMSIS Peripheral Access Layer for MK20D7 31// ** 32// ** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved. 33// ** 34// ** http: www.freescale.com 35// ** mail: support@freescale.com 36// ** 37// ** Revisions: 38// ** - rev. 1.0 (2012-01-15) 39// ** Initial public version. 40// ** 41// ** ################################################################### 42// * 43// * @file MK20D7.h 44// * @version 1.0 45// * @date 2012-01-15 46// CMSIS Peripheral Access Layer for MK20D7 47// * 48// * CMSIS Peripheral Access Layer for MK20D7 49// * Memory map major version (memory maps with equal major version number are 50// * compatible) 51// * Memory map minor version 52// Macro to access a single bit of a peripheral register (bit band region 53// * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. 54// * @param Reg Register to access. 55// * @param Bit Bit number to access. 56// * @return Value of the targeted bit in the bit band region. 57// ---------------------------------------------------------------------------- 58// -- Interrupt vector numbers 59// ---------------------------------------------------------------------------- 60// * 61// * Interrupt Number Definitions 62 63type 64 TIRQn_Enum = ( 65 NonMaskableInt_IRQn = -14, // *< Non Maskable Interrupt 66 MemoryManagement_IRQn = -12, // *< Cortex-M4 Memory Management Interrupt 67 BusFault_IRQn = -11, // *< Cortex-M4 Bus Fault Interrupt 68 UsageFault_IRQn = -10, // *< Cortex-M4 Usage Fault Interrupt 69 SVCall_IRQn = -5, // *< Cortex-M4 SV Call Interrupt 70 DebugMonitor_IRQn = -4, // *< Cortex-M4 Debug Monitor Interrupt 71 PendSV_IRQn = -2, // *< Cortex-M4 Pend SV Interrupt 72 SysTick_IRQn = -1, // *< Cortex-M4 System Tick Interrupt 73 DMA0_IRQn = 0, // *< DMA Channel 0 Transfer Complete 74 DMA1_IRQn = 1, // *< DMA Channel 1 Transfer Complete 75 DMA2_IRQn = 2, // *< DMA Channel 2 Transfer Complete 76 DMA3_IRQn = 3, // *< DMA Channel 3 Transfer Complete 77 DMA4_IRQn = 4, // *< DMA Channel 4 Transfer Complete 78 DMA5_IRQn = 5, // *< DMA Channel 5 Transfer Complete 79 DMA6_IRQn = 6, // *< DMA Channel 6 Transfer Complete 80 DMA7_IRQn = 7, // *< DMA Channel 7 Transfer Complete 81 DMA8_IRQn = 8, // *< DMA Channel 8 Transfer Complete 82 DMA9_IRQn = 9, // *< DMA Channel 9 Transfer Complete 83 DMA10_IRQn = 10, // *< DMA Channel 10 Transfer Complete 84 DMA11_IRQn = 11, // *< DMA Channel 11 Transfer Complete 85 DMA12_IRQn = 12, // *< DMA Channel 12 Transfer Complete 86 DMA13_IRQn = 13, // *< DMA Channel 13 Transfer Complete 87 DMA14_IRQn = 14, // *< DMA Channel 14 Transfer Complete 88 DMA15_IRQn = 15, // *< DMA Channel 15 Transfer Complete 89 DMA_Error_IRQn = 16, // *< DMA Error Interrupt 90 MCM_IRQn = 17, // *< Normal interrupt 91 FTFL_IRQn = 18, // *< FTFL Interrupt 92 Read_Collision_IRQn = 19, // *< Read Collision Interrupt 93 LVD_LVW_IRQn = 20, // *< Low Voltage Detect, Low Voltage Warning 94 LLW_IRQn = 21, // *< Low Leakage Wakeup 95 Watchdog_IRQn = 22, // *< WDOG Interrupt 96 RESERVED39_IRQn = 23, // *< Reserved Interrupt 39 97 I2C0_IRQn = 24, // *< I2C0 interrupt 98 I2C1_IRQn = 25, // *< I2C1 interrupt 99 SPI0_IRQn = 26, // *< SPI0 Interrupt 100 SPI1_IRQn = 27, // *< SPI1 Interrupt 101 RESERVED44_IRQn = 28, // *< Reserved interrupt 44 102 CAN0_ORed_Message_buffer_IRQn = 29, // *< CAN0 OR'd Message Buffers Interrupt 103 CAN0_Bus_Off_IRQn = 30, // *< CAN0 Bus Off Interrupt 104 CAN0_Error_IRQn = 31, // *< CAN0 Error Interrupt 105 CAN0_Tx_Warning_IRQn = 32, // *< CAN0 Tx Warning Interrupt 106 CAN0_Rx_Warning_IRQn = 33, // *< CAN0 Rx Warning Interrupt 107 CAN0_Wake_Up_IRQn = 34, // *< CAN0 Wake Up Interrupt 108 I2S0_Tx_IRQn = 35, // *< I2S0 transmit interrupt 109 I2S0_Rx_IRQn = 36, // *< I2S0 receive interrupt 110 RESERVED53_IRQn = 37, // *< Reserved interrupt 53 111 RESERVED54_IRQn = 38, // *< Reserved interrupt 54 112 RESERVED55_IRQn = 39, // *< Reserved interrupt 55 113 RESERVED56_IRQn = 40, // *< Reserved interrupt 56 114 RESERVED57_IRQn = 41, // *< Reserved interrupt 57 115 RESERVED58_IRQn = 42, // *< Reserved interrupt 58 116 RESERVED59_IRQn = 43, // *< Reserved interrupt 59 117 UART0_LON_IRQn = 44, // *< UART0 LON interrupt 118 UART0_RX_TX_IRQn = 45, // *< UART0 Receive/Transmit interrupt 119 UART0_ERR_IRQn = 46, // *< UART0 Error interrupt 120 UART1_RX_TX_IRQn = 47, // *< UART1 Receive/Transmit interrupt 121 UART1_ERR_IRQn = 48, // *< UART1 Error interrupt 122 UART2_RX_TX_IRQn = 49, // *< UART2 Receive/Transmit interrupt 123 UART2_ERR_IRQn = 50, // *< UART2 Error interrupt 124 UART3_RX_TX_IRQn = 51, // *< UART3 Receive/Transmit interrupt 125 UART3_ERR_IRQn = 52, // *< UART3 Error interrupt 126 UART4_RX_TX_IRQn = 53, // *< UART4 Receive/Transmit interrupt 127 UART4_ERR_IRQn = 54, // *< UART4 Error interrupt 128 RESERVED71_IRQn = 55, // *< Reserved interrupt 71 129 RESERVED72_IRQn = 56, // *< Reserved interrupt 72 130 ADC0_IRQn = 57, // *< ADC0 interrupt 131 ADC1_IRQn = 58, // *< ADC1 interrupt 132 CMP0_IRQn = 59, // *< CMP0 interrupt 133 CMP1_IRQn = 60, // *< CMP1 interrupt 134 CMP2_IRQn = 61, // *< CMP2 interrupt 135 FTM0_IRQn = 62, // *< FTM0 fault, overflow and channels interrupt 136 FTM1_IRQn = 63, // *< FTM1 fault, overflow and channels interrupt 137 FTM2_IRQn = 64, // *< FTM2 fault, overflow and channels interrupt 138 CMT_IRQn = 65, // *< CMT interrupt 139 RTC_IRQn = 66, // *< RTC interrupt 140 RTC_Seconds_IRQn = 67, // *< RTC seconds interrupt 141 PIT0_IRQn = 68, // *< PIT timer channel 0 interrupt 142 PIT1_IRQn = 69, // *< PIT timer channel 1 interrupt 143 PIT2_IRQn = 70, // *< PIT timer channel 2 interrupt 144 PIT3_IRQn = 71, // *< PIT timer channel 3 interrupt 145 PDB0_IRQn = 72, // *< PDB0 Interrupt 146 USB0_IRQn = 73, // *< USB0 interrupt 147 USBDCD_IRQn = 74, // *< USBDCD Interrupt 148 RESERVED91_IRQn = 75, // *< Reserved interrupt 91 149 RESERVED92_IRQn = 76, // *< Reserved interrupt 92 150 RESERVED93_IRQn = 77, // *< Reserved interrupt 93 151 RESERVED94_IRQn = 78, // *< Reserved interrupt 94 152 RESERVED95_IRQn = 79, // *< Reserved interrupt 95 153 RESERVED96_IRQn = 80, // *< Reserved interrupt 96 154 DAC0_IRQn = 81, // *< DAC0 interrupt 155 RESERVED98_IRQn = 82, // *< Reserved interrupt 98 156 TSI0_IRQn = 83, // *< TSI0 Interrupt 157 MCG_IRQn = 84, // *< MCG Interrupt 158 LPTimer_IRQn = 85, // *< LPTimer interrupt 159 RESERVED102_IRQn = 86, // *< Reserved interrupt 102 160 PORTA_IRQn = 87, // *< Port A interrupt 161 PORTB_IRQn = 88, // *< Port B interrupt 162 PORTC_IRQn = 89, // *< Port C interrupt 163 PORTD_IRQn = 90, // *< Port D interrupt 164 PORTE_IRQn = 91, // *< Port E interrupt 165 RESERVED108_IRQn = 92, // *< Reserved interrupt 108 166 RESERVED109_IRQn = 93, // *< Reserved interrupt 109 167 SWI_IRQn = 94 // *< Software interrupt 168 ); 169 170 TADC_Registers = record 171 SC1 : array[0..1] of longword; // *< ADC status and control registers 1, array offset: 0x0, array step: 0x4 172 CFG1 : longword; // *< ADC configuration register 1, offset: 0x8 173 CFG2 : longword; // *< Configuration register 2, offset: 0xC 174 R : array[0..1] of longword; // *< ADC data result register, array offset: 0x10, array step: 0x4 175 CV1 : longword; // *< Compare value registers, offset: 0x18 176 CV2 : longword; // *< Compare value registers, offset: 0x1C 177 SC2 : longword; // *< Status and control register 2, offset: 0x20 178 SC3 : longword; // *< Status and control register 3, offset: 0x24 179 OFS : longword; // *< ADC offset correction register, offset: 0x28 180 PG : longword; // *< ADC plus-side gain register, offset: 0x2C 181 MG : longword; // *< ADC minus-side gain register, offset: 0x30 182 CLPD : longword; // *< ADC plus-side general calibration value register, offset: 0x34 183 CLPS : longword; // *< ADC plus-side general calibration value register, offset: 0x38 184 CLP4 : longword; // *< ADC plus-side general calibration value register, offset: 0x3C 185 CLP3 : longword; // *< ADC plus-side general calibration value register, offset: 0x40 186 CLP2 : longword; // *< ADC plus-side general calibration value register, offset: 0x44 187 CLP1 : longword; // *< ADC plus-side general calibration value register, offset: 0x48 188 CLP0 : longword; // *< ADC plus-side general calibration value register, offset: 0x4C 189 PGA : longword; // *< ADC PGA register, offset: 0x50 190 CLMD : longword; // *< ADC minus-side general calibration value register, offset: 0x54 191 CLMS : longword; // *< ADC minus-side general calibration value register, offset: 0x58 192 CLM4 : longword; // *< ADC minus-side general calibration value register, offset: 0x5C 193 CLM3 : longword; // *< ADC minus-side general calibration value register, offset: 0x60 194 CLM2 : longword; // *< ADC minus-side general calibration value register, offset: 0x64 195 CLM1 : longword; // *< ADC minus-side general calibration value register, offset: 0x68 196 CLM0 : longword; // *< ADC minus-side general calibration value register, offset: 0x6C 197 end; 198 199const 200 ADC0_BASE = $4003B000; 201 202var 203 ADC0 : TADC_Registers absolute ADC0_BASE; 204 205const 206 ADC1_BASE = $400BB000; 207 208var 209 ADC1 : TADC_Registers absolute ADC1_BASE; 210 211type 212 TAIPS_Registers = record 213 MPRA : longword; // *< Master Privilege Register A, offset: 0x0 214 RESERVED_0 : array[0..27] of byte; 215 PACRA : longword; // *< Peripheral Access Control Register, offset: 0x20 216 PACRB : longword; // *< Peripheral Access Control Register, offset: 0x24 217 PACRC : longword; // *< Peripheral Access Control Register, offset: 0x28 218 PACRD : longword; // *< Peripheral Access Control Register, offset: 0x2C 219 RESERVED_1 : array[0..15] of byte; 220 PACRE : longword; // *< Peripheral Access Control Register, offset: 0x40 221 PACRF : longword; // *< Peripheral Access Control Register, offset: 0x44 222 PACRG : longword; // *< Peripheral Access Control Register, offset: 0x48 223 PACRH : longword; // *< Peripheral Access Control Register, offset: 0x4C 224 PACRI : longword; // *< Peripheral Access Control Register, offset: 0x50 225 PACRJ : longword; // *< Peripheral Access Control Register, offset: 0x54 226 PACRK : longword; // *< Peripheral Access Control Register, offset: 0x58 227 PACRL : longword; // *< Peripheral Access Control Register, offset: 0x5C 228 PACRM : longword; // *< Peripheral Access Control Register, offset: 0x60 229 PACRN : longword; // *< Peripheral Access Control Register, offset: 0x64 230 PACRO : longword; // *< Peripheral Access Control Register, offset: 0x68 231 PACRP : longword; // *< Peripheral Access Control Register, offset: 0x6C 232 end; 233 234const 235 AIPS0_BASE = $40000000; 236 237var 238 AIPS0 : TAIPS_Registers absolute AIPS0_BASE; 239 240const 241 AIPS1_BASE = $40080000; 242 243var 244 AIPS1 : TAIPS_Registers absolute AIPS1_BASE; 245 246type 247 TAXBS_SLAVE = record 248 PRS : longword; // *< Priority Registers Slave, array offset: 0x0, array step: 0x100 249 RESERVED_0 : array[0..11] of byte; 250 CRS : longword; // *< Control Register, array offset: 0x10, array step: 0x100 251 RESERVED_1 : array[0..235] of byte; 252 end; 253 254 TAXBS_Registers = record 255 SLAVE : array[0..3] of TAXBS_SLAVE; 256 RESERVED_0 : array[0..1023] of byte; 257 MGPCR0 : longword; // *< Master General Purpose Control Register, offset: 0x800 258 RESERVED_1 : array[0..251] of byte; 259 MGPCR1 : longword; // *< Master General Purpose Control Register, offset: 0x900 260 RESERVED_2 : array[0..251] of byte; 261 MGPCR2 : longword; // *< Master General Purpose Control Register, offset: 0xA00 262 RESERVED_3 : array[0..251] of byte; 263 MGPCR3 : longword; // *< Master General Purpose Control Register, offset: 0xB00 264 end; 265 266const 267 AXBS_BASE = $40004000; 268 269var 270 AXBS : TAXBS_Registers absolute AXBS_BASE; 271 272type 273 TCAN_MB = record 274 CS : longword; // *< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 275 ID : longword; // *< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 276 WORD0 : longword; // *< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 277 WORD1 : longword; // *< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 278 end; 279 280 TCAN_Registers = record 281 MCR : longword; // *< Module Configuration Register, offset: 0x0 282 CTRL1 : longword; // *< Control 1 Register, offset: 0x4 283 TIMER : longword; // *< Free Running Timer, offset: 0x8 284 RESERVED_0 : array[0..3] of byte; 285 RXMGMASK : longword; // *< Rx Mailboxes Global Mask Register, offset: 0x10 286 RX14MASK : longword; // *< Rx 14 Mask Register, offset: 0x14 287 RX15MASK : longword; // *< Rx 15 Mask Register, offset: 0x18 288 ECR : longword; // *< Error Counter, offset: 0x1C 289 ESR1 : longword; // *< Error and Status 1 Register, offset: 0x20 290 IMASK2 : longword; // *< Interrupt Masks 2 Register, offset: 0x24 291 IMASK1 : longword; // *< Interrupt Masks 1 Register, offset: 0x28 292 IFLAG2 : longword; // *< Interrupt Flags 2 Register, offset: 0x2C 293 IFLAG1 : longword; // *< Interrupt Flags 1 Register, offset: 0x30 294 CTRL2 : longword; // *< Control 2 Register, offset: 0x34 295 ESR2 : longword; // *< Error and Status 2 Register, offset: 0x38 296 RESERVED_1 : array[0..7] of byte; 297 CRCR : longword; // *< CRC Register, offset: 0x44 298 RXFGMASK : longword; // *< Rx FIFO Global Mask Register, offset: 0x48 299 RXFIR : longword; // *< Rx FIFO Information Register, offset: 0x4C 300 RESERVED_2 : array[0..47] of byte; 301 MB : array[0..15] of TCAN_MB; 302 RESERVED_3 : array[0..1791] of byte; 303 RXIMR : array[0..15] of longword; // *< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 304 end; 305 306const 307 CAN0_BASE = $40024000; 308 309var 310 CAN0 : TCAN_Registers absolute CAN0_BASE; 311 312type 313 TCMP_Registers = record 314 CR0 : byte; // *< CMP Control Register 0, offset: 0x0 315 CR1 : byte; // *< CMP Control Register 1, offset: 0x1 316 FPR : byte; // *< CMP Filter Period Register, offset: 0x2 317 SCR : byte; // *< CMP Status and Control Register, offset: 0x3 318 DACCR : byte; // *< DAC Control Register, offset: 0x4 319 MUXCR : byte; // *< MUX Control Register, offset: 0x5 320 end; 321 322const 323 CMP0_BASE = $40073000; 324 325var 326 CMP0 : TCMP_Registers absolute CMP0_BASE; 327 328const 329 CMP1_BASE = $40073008; 330 331var 332 CMP1 : TCMP_Registers absolute CMP1_BASE; 333 334const 335 CMP2_BASE = $40073010; 336 337var 338 CMP2 : TCMP_Registers absolute CMP2_BASE; 339 340type 341 TCMT_Registers = record 342 CGH1 : byte; // *< CMT Carrier Generator High Data Register 1, offset: 0x0 343 CGL1 : byte; // *< CMT Carrier Generator Low Data Register 1, offset: 0x1 344 CGH2 : byte; // *< CMT Carrier Generator High Data Register 2, offset: 0x2 345 CGL2 : byte; // *< CMT Carrier Generator Low Data Register 2, offset: 0x3 346 OC : byte; // *< CMT Output Control Register, offset: 0x4 347 MSC : byte; // *< CMT Modulator Status and Control Register, offset: 0x5 348 CMD1 : byte; // *< CMT Modulator Data Register Mark High, offset: 0x6 349 CMD2 : byte; // *< CMT Modulator Data Register Mark Low, offset: 0x7 350 CMD3 : byte; // *< CMT Modulator Data Register Space High, offset: 0x8 351 CMD4 : byte; // *< CMT Modulator Data Register Space Low, offset: 0x9 352 PPS : byte; // *< CMT Primary Prescaler Register, offset: 0xA 353 DMA : byte; // *< CMT Direct Memory Access, offset: 0xB 354 end; 355 356const 357 CMT_BASE = $40062000; 358 359var 360 CMT : TCMT_Registers absolute CMT_BASE; 361 362type 363 TCRC_Registers = record 364 CRC : longword; // *< CRC Data Register, offset: 0x0 365 GPOLY : longword; // *< CRC Polynomial Register, offset: 0x4 366 CTRL : longword; // *< CRC Control Register, offset: 0x8 367 end; 368 369const 370 CRC_BASE = $40032000; 371 372var 373 CRC0 : TCRC_Registers absolute CRC_BASE; 374 375type 376 TDAC_DAT = record 377 DATL : byte; // *< DAC Data Low Register, array offset: 0x0, array step: 0x2 378 DATH : byte; // *< DAC Data High Register, array offset: 0x1, array step: 0x2 379 end; 380 381 TDAC_Registers = record 382 DAT : array[0..15] of TDAC_DAT; 383 SR : byte; // *< DAC Status Register, offset: 0x20 384 C0 : byte; // *< DAC Control Register, offset: 0x21 385 C1 : byte; // *< DAC Control Register 1, offset: 0x22 386 C2 : byte; // *< DAC Control Register 2, offset: 0x23 387 end; 388 389const 390 DAC0_BASE = $400CC000; 391 392type 393 TDMA_TCD = record 394 SADDR : longword; // *< TCD Source Address, array offset: 0x1000, array step: 0x20 395 SOFF : word; // *< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 396 ATTR : word; // *< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 397 NBYTES_MLNO: longword; // *< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 398 SLAST : longword; // *< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 399 DADDR : longword; // *< TCD Destination Address, array offset: 0x1010, array step: 0x20 400 DOFF : word; // *< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 401 CITER_ELINKNO : word; // *< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 402 DLAST_SGA : longword; // *< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 403 CSR : word; // *< TCD Control and Status, array offset: 0x101C, array step: 0x20 404 BITER_ELINKNO : word; // *< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 405 end; 406 407 TDMA_Registers = record 408 CR : longword; // *< Control Register, offset: 0x0 409 ES : longword; // *< Error Status Register, offset: 0x4 410 RESERVED_0 : array[0..3] of byte; 411 ERQ : longword; // *< Enable Request Register, offset: 0xC 412 RESERVED_1 : array[0..3] of byte; 413 EEI : longword; // *< Enable Error Interrupt Register, offset: 0x14 414 CEEI : byte; // *< Clear Enable Error Interrupt Register, offset: 0x18 415 SEEI : byte; // *< Set Enable Error Interrupt Register, offset: 0x19 416 CERQ : byte; // *< Clear Enable Request Register, offset: 0x1A 417 SERQ : byte; // *< Set Enable Request Register, offset: 0x1B 418 CDNE : byte; // *< Clear DONE Status Bit Register, offset: 0x1C 419 SSRT : byte; // *< Set START Bit Register, offset: 0x1D 420 CERR : byte; // *< Clear Error Register, offset: 0x1E 421 CINT : byte; // *< Clear Interrupt Request Register, offset: 0x1F 422 RESERVED_2 : array[0..3] of byte; 423 INT : longword; // *< Interrupt Request Register, offset: 0x24 424 RESERVED_3 : array[0..3] of byte; 425 ERR : longword; // *< Error Register, offset: 0x2C 426 RESERVED_4 : array[0..3] of byte; 427 HRS : longword; // *< Hardware Request Status Register, offset: 0x34 428 RESERVED_5 : array[0..199] of byte; 429 DCHPRI3 : byte; // *< Channel n Priority Register, offset: 0x100 430 DCHPRI2 : byte; // *< Channel n Priority Register, offset: 0x101 431 DCHPRI1 : byte; // *< Channel n Priority Register, offset: 0x102 432 DCHPRI0 : byte; // *< Channel n Priority Register, offset: 0x103 433 DCHPRI7 : byte; // *< Channel n Priority Register, offset: 0x104 434 DCHPRI6 : byte; // *< Channel n Priority Register, offset: 0x105 435 DCHPRI5 : byte; // *< Channel n Priority Register, offset: 0x106 436 DCHPRI4 : byte; // *< Channel n Priority Register, offset: 0x107 437 DCHPRI11 : byte; // *< Channel n Priority Register, offset: 0x108 438 DCHPRI10 : byte; // *< Channel n Priority Register, offset: 0x109 439 DCHPRI9 : byte; // *< Channel n Priority Register, offset: 0x10A 440 DCHPRI8 : byte; // *< Channel n Priority Register, offset: 0x10B 441 DCHPRI15 : byte; // *< Channel n Priority Register, offset: 0x10C 442 DCHPRI14 : byte; // *< Channel n Priority Register, offset: 0x10D 443 DCHPRI13 : byte; // *< Channel n Priority Register, offset: 0x10E 444 DCHPRI12 : byte; // *< Channel n Priority Register, offset: 0x10F 445 RESERVED_6 : array[0..3823] of byte; 446 TCD : array[0..15] of TDMA_TCD; 447 end; 448 449const 450 DMA_BASE = $40008000; 451 452var 453 DMA0 : TDMA_Registers absolute DMA_BASE; 454 455type 456 TDMAMUX_Registers = record 457 CHCFG : array[0..15] of byte; // *< Channel Configuration Register, array offset: 0x0, array step: 0x1 458 end; 459 460const 461 DMAMUX_BASE = $40021000; 462 463var 464 DMAMUX : TDMAMUX_Registers absolute DMAMUX_BASE; 465 466type 467 TEWM_Registers = record 468 CTRL : byte; // *< Control Register, offset: 0x0 469 SERV : byte; // *< Service Register, offset: 0x1 470 CMPL : byte; // *< Compare Low Register, offset: 0x2 471 CMPH : byte; // *< Compare High Register, offset: 0x3 472 end; 473 474const 475 EWM_BASE = $40061000; 476 477var 478 EWM : TEWM_Registers absolute EWM_BASE; 479 480type 481 TFB_CS = record 482 CSAR : longword; // *< Chip select address register, array offset: 0x0, array step: 0xC 483 CSMR : longword; // *< Chip select mask register, array offset: 0x4, array step: 0xC 484 CSCR : longword; // *< Chip select control register, array offset: 0x8, array step: 0xC 485 end; 486 487 TFB_Registers = record 488 CS : array[0..5] of TFB_CS; 489 RESERVED_0 : array[0..23] of byte; 490 CSPMCR : longword; // *< Chip select port multiplexing control register, offset: 0x60 491 end; 492 493const 494 FB_BASE = $4000C000; 495 496var 497 FB : TFB_Registers absolute FB_BASE; 498 499type 500 TFMC_SET = record 501 DATA_U : longword; // *< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 502 DATA_L : longword; // *< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 503 end; 504 505 TFMC_Registers = record 506 PFAPR : longword; // *< Flash Access Protection Register, offset: 0x0 507 PFB0CR : longword; // *< Flash Bank 0 Control Register, offset: 0x4 508 PFB1CR : longword; // *< Flash Bank 1 Control Register, offset: 0x8 509 RESERVED_0 : array[0..243] of byte; 510 TAGVD : array[0..3] of longword; // *< Cache Tag Storage, array offset: 0x100, array step: index*0x20, index2*0x4 511 RESERVED_1 : array[0..127] of byte; 512 &SET : array[0..3] of TFMC_SET; 513 end; 514 515const 516 FMC_BASE = $4001F000; 517 518var 519 FMC : TFMC_Registers absolute FMC_BASE; 520 521type 522 TFTFL_Registers = record 523 FSTAT : byte; // *< Flash Status Register, offset: 0x0 524 FCNFG : byte; // *< Flash Configuration Register, offset: 0x1 525 FSEC : byte; // *< Flash Security Register, offset: 0x2 526 FOPT : byte; // *< Flash Option Register, offset: 0x3 527 FCCOB3 : byte; // *< Flash Common Command Object Registers, offset: 0x4 528 FCCOB2 : byte; // *< Flash Common Command Object Registers, offset: 0x5 529 FCCOB1 : byte; // *< Flash Common Command Object Registers, offset: 0x6 530 FCCOB0 : byte; // *< Flash Common Command Object Registers, offset: 0x7 531 FCCOB7 : byte; // *< Flash Common Command Object Registers, offset: 0x8 532 FCCOB6 : byte; // *< Flash Common Command Object Registers, offset: 0x9 533 FCCOB5 : byte; // *< Flash Common Command Object Registers, offset: 0xA 534 FCCOB4 : byte; // *< Flash Common Command Object Registers, offset: 0xB 535 FCCOBB : byte; // *< Flash Common Command Object Registers, offset: 0xC 536 FCCOBA : byte; // *< Flash Common Command Object Registers, offset: 0xD 537 FCCOB9 : byte; // *< Flash Common Command Object Registers, offset: 0xE 538 FCCOB8 : byte; // *< Flash Common Command Object Registers, offset: 0xF 539 FPROT3 : byte; // *< Program Flash Protection Registers, offset: 0x10 540 FPROT2 : byte; // *< Program Flash Protection Registers, offset: 0x11 541 FPROT1 : byte; // *< Program Flash Protection Registers, offset: 0x12 542 FPROT0 : byte; // *< Program Flash Protection Registers, offset: 0x13 543 RESERVED_0 : array[0..1] of byte; 544 FEPROT : byte; // *< EEPROM Protection Register, offset: 0x16 545 FDPROT : byte; // *< Data Flash Protection Register, offset: 0x17 546 end; 547 548const 549 FTFL_BASE = $40020000; 550 551var 552 FTFL : TFTFL_Registers absolute FTFL_BASE; 553 554type 555 TFTM_CONTROLS= record 556 CnSC : longword; // *< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 557 CnV : longword; // *< Channel (n) Value, array offset: 0x10, array step: 0x8 558 end; 559 560 TFTM_Registers = record 561 SC : longword; // *< Status and Control, offset: 0x0 562 CNT : longword; // *< Counter, offset: 0x4 563 &MOD : longword; // *< Modulo, offset: 0x8 564 CONTROLS : array[0..7] of TFTM_CONTROLS; 565 CNTIN : longword; // *< Counter Initial Value, offset: 0x4C 566 STATUS : longword; // *< Capture and Compare Status, offset: 0x50 567 MODE : longword; // *< Features Mode Selection, offset: 0x54 568 SYNC : longword; // *< Synchronization, offset: 0x58 569 OUTINIT : longword; // *< Initial State for Channels Output, offset: 0x5C 570 OUTMASK : longword; // *< Output Mask, offset: 0x60 571 COMBINE : longword; // *< Function for Linked Channels, offset: 0x64 572 DEADTIME : longword; // *< Deadtime Insertion Control, offset: 0x68 573 EXTTRIG : longword; // *< FTM External Trigger, offset: 0x6C 574 POL : longword; // *< Channels Polarity, offset: 0x70 575 FMS : longword; // *< Fault Mode Status, offset: 0x74 576 FILTER : longword; // *< Input Capture Filter Control, offset: 0x78 577 FLTCTRL : longword; // *< Fault Control, offset: 0x7C 578 QDCTRL : longword; // *< Quadrature Decoder Control and Status, offset: 0x80 579 CONF : longword; // *< Configuration, offset: 0x84 580 FLTPOL : longword; // *< FTM Fault Input Polarity, offset: 0x88 581 SYNCONF : longword; // *< Synchronization Configuration, offset: 0x8C 582 INVCTRL : longword; // *< FTM Inverting Control, offset: 0x90 583 SWOCTRL : longword; // *< FTM Software Output Control, offset: 0x94 584 PWMLOAD : longword; // *< FTM PWM Load, offset: 0x98 585 end; 586 587const 588 FTM0_BASE = $40038000; 589 590var 591 FTM0 : TFTM_Registers absolute FTM0_BASE; 592 593const 594 FTM1_BASE = $40039000; 595 596var 597 FTM1 : TFTM_Registers absolute FTM1_BASE; 598 599const 600 FTM2_BASE = $400B8000; 601 602var 603 FTM2 : TFTM_Registers absolute FTM2_BASE; 604 605type 606 TGPIO_Registers = record 607 PDOR : longword; // *< Port Data Output Register, offset: 0x0 608 PSOR : longword; // *< Port Set Output Register, offset: 0x4 609 PCOR : longword; // *< Port Clear Output Register, offset: 0x8 610 PTOR : longword; // *< Port Toggle Output Register, offset: 0xC 611 PDIR : longword; // *< Port Data Input Register, offset: 0x10 612 PDDR : longword; // *< Port Data Direction Register, offset: 0x14 613 end; 614 615const 616 PTA_BASE = $400FF000; 617 618var 619 PTA : TGPIO_Registers absolute PTA_BASE; 620 621const 622 PTB_BASE = $400FF040; 623 624var 625 PTB : TGPIO_Registers absolute PTB_BASE; 626 627const 628 PTC_BASE = $400FF080; 629 630var 631 PTC : TGPIO_Registers absolute PTC_BASE; 632 633const 634 PTD_BASE = $400FF0C0; 635 636var 637 PTD : TGPIO_Registers absolute PTD_BASE; 638 639const 640 PTE_BASE = $400FF100; 641 642var 643 PTE : TGPIO_Registers absolute PTE_BASE; 644 645type 646 TI2C_Registers = record 647 A1 : byte; // *< I2C Address Register 1, offset: 0x0 648 F : byte; // *< I2C Frequency Divider register, offset: 0x1 649 C1 : byte; // *< I2C Control Register 1, offset: 0x2 650 S : byte; // *< I2C Status Register, offset: 0x3 651 D : byte; // *< I2C Data I/O register, offset: 0x4 652 C2 : byte; // *< I2C Control Register 2, offset: 0x5 653 FLT : byte; // *< I2C Programmable Input Glitch Filter register, offset: 0x6 654 RA : byte; // *< I2C Range Address register, offset: 0x7 655 SMB : byte; // *< I2C SMBus Control and Status register, offset: 0x8 656 A2 : byte; // *< I2C Address Register 2, offset: 0x9 657 SLTH : byte; // *< I2C SCL Low Timeout Register High, offset: 0xA 658 SLTL : byte; // *< I2C SCL Low Timeout Register Low, offset: 0xB 659 end; 660 661const 662 I2C0_BASE = $40066000; 663 664var 665 I2C0 : TI2C_Registers absolute I2C0_BASE; 666 667const 668 I2C1_BASE = $40067000; 669 670var 671 I2C1 : TI2C_Registers absolute I2C1_BASE; 672 673type 674 TI2S_Registers = record 675 TCSR : longword; // *< SAI Transmit Control Register, offset: 0x0 676 TCR1 : longword; // *< SAI Transmit Configuration 1 Register, offset: 0x4 677 TCR2 : longword; // *< SAI Transmit Configuration 2 Register, offset: 0x8 678 TCR3 : longword; // *< SAI Transmit Configuration 3 Register, offset: 0xC 679 TCR4 : longword; // *< SAI Transmit Configuration 4 Register, offset: 0x10 680 TCR5 : longword; // *< SAI Transmit Configuration 5 Register, offset: 0x14 681 RESERVED_0 : array[0..7] of byte; 682 TDR : array[0..1] of longword; // *< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 683 RESERVED_1 : array[0..23] of byte; 684 TFR : array[0..1] of longword; // *< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 685 RESERVED_2 : array[0..23] of byte; 686 TMR : longword; // *< SAI Transmit Mask Register, offset: 0x60 687 RESERVED_3 : array[0..27] of byte; 688 RCSR : longword; // *< SAI Receive Control Register, offset: 0x80 689 RCR1 : longword; // *< SAI Receive Configuration 1 Register, offset: 0x84 690 RCR2 : longword; // *< SAI Receive Configuration 2 Register, offset: 0x88 691 RCR3 : longword; // *< SAI Receive Configuration 3 Register, offset: 0x8C 692 RCR4 : longword; // *< SAI Receive Configuration 4 Register, offset: 0x90 693 RCR5 : longword; // *< SAI Receive Configuration 5 Register, offset: 0x94 694 RESERVED_4 : array[0..7] of byte; 695 RDR : array[0..1] of longword; // *< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 696 RESERVED_5 : array[0..23] of byte; 697 RFR : array[0..1] of longword; // *< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 698 RESERVED_6 : array[0..23] of byte; 699 RMR : longword; // *< SAI Receive Mask Register, offset: 0xE0 700 RESERVED_7 : array[0..27] of byte; 701 MCR : longword; // *< SAI MCLK Control Register, offset: 0x100 702 MDR : longword; // *< MCLK Divide Register, offset: 0x104 703 end; 704 705const 706 I2S0_BASE = $4002F000; 707 708var 709 I2S0 : TI2S_Registers absolute I2S0_BASE; 710 711type 712 TLLWU_Registers = record 713 PE1 : byte; // *< LLWU Pin Enable 1 Register, offset: 0x0 714 PE2 : byte; // *< LLWU Pin Enable 2 Register, offset: 0x1 715 PE3 : byte; // *< LLWU Pin Enable 3 Register, offset: 0x2 716 PE4 : byte; // *< LLWU Pin Enable 4 Register, offset: 0x3 717 ME : byte; // *< LLWU Module Enable Register, offset: 0x4 718 F1 : byte; // *< LLWU Flag 1 Register, offset: 0x5 719 F2 : byte; // *< LLWU Flag 2 Register, offset: 0x6 720 F3 : byte; // *< LLWU Flag 3 Register, offset: 0x7 721 FILT1 : byte; // *< LLWU Pin Filter 1 Register, offset: 0x8 722 FILT2 : byte; // *< LLWU Pin Filter 2 Register, offset: 0x9 723 RST : byte; // *< LLWU Reset Enable Register, offset: 0xA 724 end; 725 726const 727 LLWU_BASE = $4007C000; 728 729var 730 LLWU : TLLWU_Registers absolute LLWU_BASE; 731 732type 733 TLPTMR_Registers = record 734 CSR : longword; // *< Low Power Timer Control Status Register, offset: 0x0 735 PSR : longword; // *< Low Power Timer Prescale Register, offset: 0x4 736 CMR : longword; // *< Low Power Timer Compare Register, offset: 0x8 737 CNR : longword; // *< Low Power Timer Counter Register, offset: 0xC 738 end; 739 740const 741 LPTMR0_BASE = $40040000; 742 743var 744 LPTMR0 : TLPTMR_Registers absolute LPTMR0_BASE; 745 746type 747 TMCG_Registers = record 748 C1 : byte; // *< MCG Control 1 Register, offset: 0x0 749 C2 : byte; // *< MCG Control 2 Register, offset: 0x1 750 C3 : byte; // *< MCG Control 3 Register, offset: 0x2 751 C4 : byte; // *< MCG Control 4 Register, offset: 0x3 752 C5 : byte; // *< MCG Control 5 Register, offset: 0x4 753 C6 : byte; // *< MCG Control 6 Register, offset: 0x5 754 S : byte; // *< MCG Status Register, offset: 0x6 755 RESERVED_0 : array[0..0] of byte; 756 SC : byte; // *< MCG Status and Control Register, offset: 0x8 757 RESERVED_1 : array[0..0] of byte; 758 ATCVH : byte; // *< MCG Auto Trim Compare Value High Register, offset: 0xA 759 ATCVL : byte; // *< MCG Auto Trim Compare Value Low Register, offset: 0xB 760 C7 : byte; // *< MCG Control 7 Register, offset: 0xC 761 C8 : byte; // *< MCG Control 8 Register, offset: 0xD 762 end; 763 764const 765 MCG_BASE = $40064000; 766 767var 768 MCG : TMCG_Registers absolute MCG_BASE; 769 770type 771 TMCM_Registers = record 772 RESERVED_0 : array[0..7] of byte; 773 PLASC : word; // *< Crossbar switch (AXBS) slave configuration, offset: 0x8 774 PLAMC : word; // *< Crossbar switch (AXBS) master configuration, offset: 0xA 775 CR : longword; // *< Control register, offset: 0xC 776 end; 777 778const 779 MCM_BASE = $E0080000; 780 781var 782 MCM : TMCM_Registers absolute MCM_BASE; 783 784type 785 TNV_Registers = record 786 BACKKEY3 : byte; // *< Backdoor Comparison Key 3., offset: 0x0 787 BACKKEY2 : byte; // *< Backdoor Comparison Key 2., offset: 0x1 788 BACKKEY1 : byte; // *< Backdoor Comparison Key 1., offset: 0x2 789 BACKKEY0 : byte; // *< Backdoor Comparison Key 0., offset: 0x3 790 BACKKEY7 : byte; // *< Backdoor Comparison Key 7., offset: 0x4 791 BACKKEY6 : byte; // *< Backdoor Comparison Key 6., offset: 0x5 792 BACKKEY5 : byte; // *< Backdoor Comparison Key 5., offset: 0x6 793 BACKKEY4 : byte; // *< Backdoor Comparison Key 4., offset: 0x7 794 FPROT3 : byte; // *< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 795 FPROT2 : byte; // *< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 796 FPROT1 : byte; // *< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA 797 FPROT0 : byte; // *< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB 798 FSEC : byte; // *< Non-volatile Flash Security Register, offset: 0xC 799 FOPT : byte; // *< Non-volatile Flash Option Register, offset: 0xD 800 FEPROT : byte; // *< Non-volatile EERAM Protection Register, offset: 0xE 801 FDPROT : byte; // *< Non-volatile D-Flash Protection Register, offset: 0xF 802 end; 803 804const 805 FTFL_FlashConfig_BASE = $400; 806 807var 808 FTFL_FlashConfig : TNV_Registers absolute FTFL_FlashConfig_BASE; 809 810type 811 TOSC_Registers = record 812 CR : byte; // *< OSC Control Register, offset: 0x0 813 end; 814 815const 816 OSC_BASE = $40065000; 817 818var 819 OSC : TOSC_Registers absolute OSC_BASE; 820 821type 822 TPDB_CH = record 823 C1 : longword; // *< Channel n Control Register 1, array offset: 0x10, array step: 0x28 824 S : longword; // *< Channel n Status Register, array offset: 0x14, array step: 0x28 825 DLY : array[0..1] of longword; // *< Channel n Delay 0 Register..Channel n Delay 1 Register, array offset: 0x18, array step: index*0x28, index2*0x4 826 RESERVED_0 : array[0..23] of byte; 827 end; 828 829 TPDB_DAC = record 830 INTC : longword; // *< DAC Interval Trigger n Control Register, array offset: 0x150, array step: 0x8 831 INT : longword; // *< DAC Interval n Register, array offset: 0x154, array step: 0x8 832 end; 833 834 TPDB_Registers = record 835 SC : longword; // *< Status and Control Register, offset: 0x0 836 &MOD : longword; // *< Modulus Register, offset: 0x4 837 CNT : longword; // *< Counter Register, offset: 0x8 838 IDLY : longword; // *< Interrupt Delay Register, offset: 0xC 839 CH : array[0..1] of TPDB_CH; 840 RESERVED_0 : array[0..239] of byte; 841 DAC : array[0..0] of TPDB_DAC; 842 RESERVED_1 : array[0..55] of byte; 843 POEN : longword; // *< Pulse-Out n Enable Register, offset: 0x190 844 PODLY : array[0..2] of longword; // *< Pulse-Out n Delay Register, array offset: 0x194, array step: 0x4 845 end; 846 847const 848 PDB0_BASE = $40036000; 849 850var 851 PDB0 : TPDB_Registers absolute PDB0_BASE; 852 853type 854 TPIT_CHANNEL = record 855 LDVAL : longword; // *< Timer Load Value Register, array offset: 0x100, array step: 0x10 856 CVAL : longword; // *< Current Timer Value Register, array offset: 0x104, array step: 0x10 857 TCTRL : longword; // *< Timer Control Register, array offset: 0x108, array step: 0x10 858 TFLG : longword; // *< Timer Flag Register, array offset: 0x10C, array step: 0x10 859 end; 860 861 TPIT_Registers = record 862 MCR : longword; // *< PIT Module Control Register, offset: 0x0 863 RESERVED_0 : array[0..251] of byte; 864 CHANNEL : array[0..3] of TPIT_CHANNEL; 865 end; 866 867const 868 PIT_BASE = $40037000; 869 870var 871 PIT : TPIT_Registers absolute PIT_BASE; 872 873type 874 TPMC_Registers = record 875 LVDSC1 : byte; // *< Low Voltage Detect Status and Control 1 Register, offset: 0x0 876 LVDSC2 : byte; // *< Low Voltage Detect Status and Control 2 Register, offset: 0x1 877 REGSC : byte; // *< Regulator Status and Control Register, offset: 0x2 878 end; 879 880const 881 PMC_BASE = $4007D000; 882 883var 884 PMC : TPMC_Registers absolute PMC_BASE; 885 886type 887 TPORT_Registers = record 888 PCR : array[0..31] of longword; // *< Pin Control Register n, array offset: 0x0, array step: 0x4 889 GPCLR : longword; // *< Global Pin Control Low Register, offset: 0x80 890 GPCHR : longword; // *< Global Pin Control High Register, offset: 0x84 891 RESERVED_0 : array[0..23] of byte; 892 ISFR : longword; // *< Interrupt Status Flag Register, offset: 0xA0 893 RESERVED_1 : array[0..27] of byte; 894 DFER : longword; // *< Digital Filter Enable Register, offset: 0xC0 895 DFCR : longword; // *< Digital Filter Clock Register, offset: 0xC4 896 DFWR : longword; // *< Digital Filter Width Register, offset: 0xC8 897 end; 898 899const 900 PORTA_BASE = $40049000; 901 902var 903 PORTA : TPORT_Registers absolute PORTA_BASE; 904 905const 906 PORTB_BASE = $4004A000; 907 908var 909 PORTB : TPORT_Registers absolute PORTB_BASE; 910 911const 912 PORTC_BASE = $4004B000; 913 914var 915 PORTC : TPORT_Registers absolute PORTC_BASE; 916 917const 918 PORTD_BASE = $4004C000; 919 920var 921 PORTD : TPORT_Registers absolute PORTD_BASE; 922 923const 924 PORTE_BASE = $4004D000; 925 926var 927 PORTE : TPORT_Registers absolute PORTE_BASE; 928 929type 930 TRCM_Registers = record 931 SRS0 : byte; // *< System Reset Status Register 0, offset: 0x0 932 SRS1 : byte; // *< System Reset Status Register 1, offset: 0x1 933 RESERVED_0 : array[0..1] of byte; 934 RPFC : byte; // *< Reset Pin Filter Control Register, offset: 0x4 935 RPFW : byte; // *< Reset Pin Filter Width Register, offset: 0x5 936 RESERVED_1 : array[0..0] of byte; 937 MR : byte; // *< Mode Register, offset: 0x7 938 end; 939 940const 941 RCM_BASE = $4007F000; 942 943var 944 RCM : TRCM_Registers absolute RCM_BASE; 945 946type 947 TRFSYS_Registers = record 948 REG : array[0..7] of longword; // *< Register file register, array offset: 0x0, array step: 0x4 949 end; 950 951const 952 RFSYS_BASE = $40041000; 953 954var 955 RFSYS : TRFSYS_Registers absolute RFSYS_BASE; 956 957type 958 TRFVBAT_Registers = record 959 REG : array[0..7] of longword; // *< VBAT register file register, array offset: 0x0, array step: 0x4 960 end; 961 962const 963 RFVBAT_BASE = $4003E000; 964 965var 966 RFVBAT : TRFVBAT_Registers absolute RFVBAT_BASE; 967 968type 969 TRTC_Registers = record 970 TSR : longword; // *< RTC Time Seconds Register, offset: 0x0 971 TPR : longword; // *< RTC Time Prescaler Register, offset: 0x4 972 TAR : longword; // *< RTC Time Alarm Register, offset: 0x8 973 TCR : longword; // *< RTC Time Compensation Register, offset: 0xC 974 CR : longword; // *< RTC Control Register, offset: 0x10 975 SR : longword; // *< RTC Status Register, offset: 0x14 976 LR : longword; // *< RTC Lock Register, offset: 0x18 977 IER : longword; // *< RTC Interrupt Enable Register, offset: 0x1C 978 RESERVED_0 : array[0..2015] of byte; 979 WAR : longword; // *< RTC Write Access Register, offset: 0x800 980 RAR : longword; // *< RTC Read Access Register, offset: 0x804 981 end; 982 983const 984 RTC_BASE = $4003D000; 985 986var 987 RTC : TRTC_Registers absolute RTC_BASE; 988 989type 990 TSIM_Registers = record 991 SOPT1 : longword; // *< System Options Register 1, offset: 0x0 992 SOPT1CFG : longword; // *< SOPT1 Configuration Register, offset: 0x4 993 RESERVED_0 : array[0..4091] of byte; 994 SOPT2 : longword; // *< System Options Register 2, offset: 0x1004 995 RESERVED_1 : array[0..3] of byte; 996 SOPT4 : longword; // *< System Options Register 4, offset: 0x100C 997 SOPT5 : longword; // *< System Options Register 5, offset: 0x1010 998 RESERVED_2 : array[0..3] of byte; 999 SOPT7 : longword; // *< System Options Register 7, offset: 0x1018 1000 RESERVED_3 : array[0..7] of byte; 1001 SDID : longword; // *< System Device Identification Register, offset: 0x1024 1002 SCGC1 : longword; // *< System Clock Gating Control Register 1, offset: 0x1028 1003 SCGC2 : longword; // *< System Clock Gating Control Register 2, offset: 0x102C 1004 SCGC3 : longword; // *< System Clock Gating Control Register 3, offset: 0x1030 1005 SCGC4 : longword; // *< System Clock Gating Control Register 4, offset: 0x1034 1006 SCGC5 : longword; // *< System Clock Gating Control Register 5, offset: 0x1038 1007 SCGC6 : longword; // *< System Clock Gating Control Register 6, offset: 0x103C 1008 SCGC7 : longword; // *< System Clock Gating Control Register 7, offset: 0x1040 1009 CLKDIV1 : longword; // *< System Clock Divider Register 1, offset: 0x1044 1010 CLKDIV2 : longword; // *< System Clock Divider Register 2, offset: 0x1048 1011 FCFG1 : longword; // *< Flash Configuration Register 1, offset: 0x104C 1012 FCFG2 : longword; // *< Flash Configuration Register 2, offset: 0x1050 1013 UIDH : longword; // *< Unique Identification Register High, offset: 0x1054 1014 UIDMH : longword; // *< Unique Identification Register Mid-High, offset: 0x1058 1015 UIDML : longword; // *< Unique Identification Register Mid Low, offset: 0x105C 1016 UIDL : longword; // *< Unique Identification Register Low, offset: 0x1060 1017 end; 1018 1019const 1020 SIM_BASE = $40047000; 1021 1022var 1023 SIM : TSIM_Registers absolute SIM_BASE; 1024 1025type 1026 TSMC_Registers = record 1027 PMPROT : byte; // *< Power Mode Protection Register, offset: 0x0 1028 PMCTRL : byte; // *< Power Mode Control Register, offset: 0x1 1029 VLLSCTRL : byte; // *< VLLS Control Register, offset: 0x2 1030 PMSTAT : byte; // *< Power Mode Status Register, offset: 0x3 1031 end; 1032 1033const 1034 SMC_BASE = $4007E000; 1035 1036var 1037 SMC : TSMC_Registers absolute SMC_BASE; 1038 1039type 1040 TSPI_Registers = record 1041 MCR : longword; // *< DSPI Module Configuration Register, offset: 0x0 1042 RESERVED_0 : array[0..3] of byte; 1043 TCR : longword; // *< DSPI Transfer Count Register, offset: 0x8 1044 CTAR : array[0..1] of longword; // *< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 1045 RESERVED_1 : array[0..23] of byte; 1046 SR : longword; // *< DSPI Status Register, offset: 0x2C 1047 RSER : longword; // *< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 1048 PUSHR : longword; // *< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 1049 POPR : longword; // *< DSPI POP RX FIFO Register, offset: 0x38 1050 TXFR0 : longword; // *< DSPI Transmit FIFO Registers, offset: 0x3C 1051 TXFR1 : longword; // *< DSPI Transmit FIFO Registers, offset: 0x40 1052 TXFR2 : longword; // *< DSPI Transmit FIFO Registers, offset: 0x44 1053 TXFR3 : longword; // *< DSPI Transmit FIFO Registers, offset: 0x48 1054 RESERVED_2 : array[0..47] of byte; 1055 RXFR0 : longword; // *< DSPI Receive FIFO Registers, offset: 0x7C 1056 RXFR1 : longword; // *< DSPI Receive FIFO Registers, offset: 0x80 1057 RXFR2 : longword; // *< DSPI Receive FIFO Registers, offset: 0x84 1058 RXFR3 : longword; // *< DSPI Receive FIFO Registers, offset: 0x88 1059 end; 1060 1061const 1062 SPI0_BASE = $4002C000; 1063 1064var 1065 SPI0 : TSPI_Registers absolute SPI0_BASE; 1066 1067const 1068 SPI1_BASE = $4002D000; 1069 1070var 1071 SPI1 : TSPI_Registers absolute SPI1_BASE; 1072 1073type 1074 TTSI_Registers = record 1075 GENCS : longword; // *< General Control and Status Register, offset: 0x0 1076 SCANC : longword; // *< SCAN Control Register, offset: 0x4 1077 PEN : longword; // *< Pin Enable Register, offset: 0x8 1078 WUCNTR : longword; // *< Wake-Up Channel Counter Register, offset: 0xC 1079 RESERVED_0 : array[0..239] of byte; 1080 CNTR1 : longword; // *< Counter Register, offset: 0x100 1081 CNTR3 : longword; // *< Counter Register, offset: 0x104 1082 CNTR5 : longword; // *< Counter Register, offset: 0x108 1083 CNTR7 : longword; // *< Counter Register, offset: 0x10C 1084 CNTR9 : longword; // *< Counter Register, offset: 0x110 1085 CNTR11 : longword; // *< Counter Register, offset: 0x114 1086 CNTR13 : longword; // *< Counter Register, offset: 0x118 1087 CNTR15 : longword; // *< Counter Register, offset: 0x11C 1088 THRESHOLD : longword; // *< Low Power Channel Threshold Register, offset: 0x120 1089 end; 1090 1091const 1092 TSI0_BASE = $40045000; 1093 1094var 1095 TSI0 : TTSI_Registers absolute TSI0_BASE; 1096 1097type 1098 TUART_Registers = record 1099 BDH : byte; // *< UART Baud Rate Registers:High, offset: 0x0 1100 BDL : byte; // *< UART Baud Rate Registers: Low, offset: 0x1 1101 C1 : byte; // *< UART Control Register 1, offset: 0x2 1102 C2 : byte; // *< UART Control Register 2, offset: 0x3 1103 S1 : byte; // *< UART Status Register 1, offset: 0x4 1104 S2 : byte; // *< UART Status Register 2, offset: 0x5 1105 C3 : byte; // *< UART Control Register 3, offset: 0x6 1106 D : byte; // *< UART Data Register, offset: 0x7 1107 MA1 : byte; // *< UART Match Address Registers 1, offset: 0x8 1108 MA2 : byte; // *< UART Match Address Registers 2, offset: 0x9 1109 C4 : byte; // *< UART Control Register 4, offset: 0xA 1110 C5 : byte; // *< UART Control Register 5, offset: 0xB 1111 ED : byte; // *< UART Extended Data Register, offset: 0xC 1112 MODEM : byte; // *< UART Modem Register, offset: 0xD 1113 IR : byte; // *< UART Infrared Register, offset: 0xE 1114 RESERVED_0 : array[0..0] of byte; 1115 PFIFO : byte; // *< UART FIFO Parameters, offset: 0x10 1116 CFIFO : byte; // *< UART FIFO Control Register, offset: 0x11 1117 SFIFO : byte; // *< UART FIFO Status Register, offset: 0x12 1118 TWFIFO : byte; // *< UART FIFO Transmit Watermark, offset: 0x13 1119 TCFIFO : byte; // *< UART FIFO Transmit Count, offset: 0x14 1120 RWFIFO : byte; // *< UART FIFO Receive Watermark, offset: 0x15 1121 RCFIFO : byte; // *< UART FIFO Receive Count, offset: 0x16 1122 RESERVED_1 : array[0..0] of byte; 1123 C7816 : byte; // *< UART 7816 Control Register, offset: 0x18 1124 IE7816 : byte; // *< UART 7816 Interrupt Enable Register, offset: 0x19 1125 IS7816 : byte; // *< UART 7816 Interrupt Status Register, offset: 0x1A 1126 WP7816_T_TYPE0 : byte; // *< UART 7816 Wait Parameter Register, offset: 0x1B 1127 WN7816 : byte; // *< UART 7816 Wait N Register, offset: 0x1C 1128 WF7816 : byte; // *< UART 7816 Wait FD Register, offset: 0x1D 1129 ET7816 : byte; // *< UART 7816 Error Threshold Register, offset: 0x1E 1130 TL7816 : byte; // *< UART 7816 Transmit Length Register, offset: 0x1F 1131 end; 1132 1133const 1134 UART0_BASE = $4006A000; 1135 1136var 1137 UART0 : TUART_Registers absolute UART0_BASE; 1138 1139const 1140 UART1_BASE = $4006B000; 1141 1142var 1143 UART1 : TUART_Registers absolute UART1_BASE; 1144 1145const 1146 UART2_BASE = $4006C000; 1147 1148var 1149 UART2 : TUART_Registers absolute UART2_BASE; 1150 1151const 1152 UART3_BASE = $4006D000; 1153 1154var 1155 UART3 : TUART_Registers absolute UART3_BASE; 1156 1157const 1158 UART4_BASE = $400EA000; 1159 1160var 1161 UART4 : TUART_Registers absolute UART4_BASE; 1162 1163type 1164 TUSB_ENDPOINT= record 1165 ENDPT : byte; // *< Endpoint Control Register, array offset: 0xC0, array step: 0x4 1166 RESERVED_0 : array[0..2] of byte; 1167 end; 1168 1169 TUSB_Registers = record 1170 PERID : byte; // *< Peripheral ID Register, offset: 0x0 1171 RESERVED_0 : array[0..2] of byte; 1172 IDCOMP : byte; // *< Peripheral ID Complement Register, offset: 0x4 1173 RESERVED_1 : array[0..2] of byte; 1174 REV : byte; // *< Peripheral Revision Register, offset: 0x8 1175 RESERVED_2 : array[0..2] of byte; 1176 ADDINFO : byte; // *< Peripheral Additional Info Register, offset: 0xC 1177 RESERVED_3 : array[0..2] of byte; 1178 OTGISTAT : byte; // *< OTG Interrupt Status Register, offset: 0x10 1179 RESERVED_4 : array[0..2] of byte; 1180 OTGICR : byte; // *< OTG Interrupt Control Register, offset: 0x14 1181 RESERVED_5 : array[0..2] of byte; 1182 OTGSTAT : byte; // *< OTG Status Register, offset: 0x18 1183 RESERVED_6 : array[0..2] of byte; 1184 OTGCTL : byte; // *< OTG Control Register, offset: 0x1C 1185 RESERVED_7 : array[0..98] of byte; 1186 ISTAT : byte; // *< Interrupt Status Register, offset: 0x80 1187 RESERVED_8 : array[0..2] of byte; 1188 INTEN : byte; // *< Interrupt Enable Register, offset: 0x84 1189 RESERVED_9 : array[0..2] of byte; 1190 ERRSTAT : byte; // *< Error Interrupt Status Register, offset: 0x88 1191 RESERVED_10 : array[0..2] of byte; 1192 ERREN : byte; // *< Error Interrupt Enable Register, offset: 0x8C 1193 RESERVED_11 : array[0..2] of byte; 1194 STAT : byte; // *< Status Register, offset: 0x90 1195 RESERVED_12 : array[0..2] of byte; 1196 CTL : byte; // *< Control Register, offset: 0x94 1197 RESERVED_13 : array[0..2] of byte; 1198 ADDR : byte; // *< Address Register, offset: 0x98 1199 RESERVED_14 : array[0..2] of byte; 1200 BDTPAGE1 : byte; // *< BDT Page Register 1, offset: 0x9C 1201 RESERVED_15 : array[0..2] of byte; 1202 FRMNUML : byte; // *< Frame Number Register Low, offset: 0xA0 1203 RESERVED_16 : array[0..2] of byte; 1204 FRMNUMH : byte; // *< Frame Number Register High, offset: 0xA4 1205 RESERVED_17 : array[0..2] of byte; 1206 TOKEN : byte; // *< Token Register, offset: 0xA8 1207 RESERVED_18 : array[0..2] of byte; 1208 SOFTHLD : byte; // *< SOF Threshold Register, offset: 0xAC 1209 RESERVED_19 : array[0..2] of byte; 1210 BDTPAGE2 : byte; // *< BDT Page Register 2, offset: 0xB0 1211 RESERVED_20 : array[0..2] of byte; 1212 BDTPAGE3 : byte; // *< BDT Page Register 3, offset: 0xB4 1213 RESERVED_21 : array[0..10] of byte; 1214 ENDPOINT : array[0..15] of TUSB_ENDPOINT; 1215 USBCTRL : byte; // *< USB Control Register, offset: 0x100 1216 RESERVED_22 : array[0..2] of byte; 1217 OBSERVE : byte; // *< USB OTG Observe Register, offset: 0x104 1218 RESERVED_23 : array[0..2] of byte; 1219 CONTROL : byte; // *< USB OTG Control Register, offset: 0x108 1220 RESERVED_24 : array[0..2] of byte; 1221 USBTRC0 : byte; // *< USB Transceiver Control Register 0, offset: 0x10C 1222 RESERVED_25 : array[0..6] of byte; 1223 USBFRMADJUST : byte; // *< Frame Adjust Register, offset: 0x114 1224 end; 1225 1226const 1227 USB0_BASE = $40072000; 1228 1229var 1230 USB0 : TUSB_Registers absolute USB0_BASE; 1231 1232type 1233 TUSBDCD_Registers = record 1234 CONTROL : longword; // *< Control Register, offset: 0x0 1235 CLOCK : longword; // *< Clock Register, offset: 0x4 1236 STATUS : longword; // *< Status Register, offset: 0x8 1237 RESERVED_0 : array[0..3] of byte; 1238 TIMER0 : longword; // *< TIMER0 Register, offset: 0x10 1239 TIMER1 : longword; // *< , offset: 0x14 1240 TIMER2 : longword; // *< , offset: 0x18 1241 end; 1242 1243const 1244 USBDCD_BASE = $40035000; 1245 1246var 1247 USBDCD : TUSBDCD_Registers absolute USBDCD_BASE; 1248 1249type 1250 TVREF_Registers = record 1251 TRM : byte; // *< VREF Trim Register, offset: 0x0 1252 SC : byte; // *< VREF Status and Control Register, offset: 0x1 1253 end; 1254 1255const 1256 VREF_BASE = $40074000; 1257 1258var 1259 VREF : TVREF_Registers absolute VREF_BASE; 1260 1261type 1262 TWDOG_Registers = record 1263 STCTRLH : word; // *< Watchdog Status and Control Register High, offset: 0x0 1264 STCTRLL : word; // *< Watchdog Status and Control Register Low, offset: 0x2 1265 TOVALH : word; // *< Watchdog Time-out Value Register High, offset: 0x4 1266 TOVALL : word; // *< Watchdog Time-out Value Register Low, offset: 0x6 1267 WINH : word; // *< Watchdog Window Register High, offset: 0x8 1268 WINL : word; // *< Watchdog Window Register Low, offset: 0xA 1269 REFRESH : word; // *< Watchdog Refresh Register, offset: 0xC 1270 UNLOCK : word; // *< Watchdog Unlock Register, offset: 0xE 1271 TMROUTH : word; // *< Watchdog Timer Output Register High, offset: 0x10 1272 TMROUTL : word; // *< Watchdog Timer Output Register Low, offset: 0x12 1273 RSTCNT : word; // *< Watchdog Reset Count Register, offset: 0x14 1274 PRESC : word; // *< Watchdog Prescaler Register, offset: 0x16 1275 end; 1276 1277const 1278 WDOG_BASE = $40052000; 1279 1280var 1281 WDOG : TWDOG_Registers absolute WDOG_BASE; 1282 1283implementation 1284 1285procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt'; 1286procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt'; 1287procedure BusFault_interrupt; external name 'BusFault_interrupt'; 1288procedure UsageFault_interrupt; external name 'UsageFault_interrupt'; 1289procedure SVCall_interrupt; external name 'SVCall_interrupt'; 1290procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt'; 1291procedure PendSV_interrupt; external name 'PendSV_interrupt'; 1292procedure SysTick_interrupt; external name 'SysTick_interrupt'; 1293procedure DMA0_interrupt; external name 'DMA0_interrupt'; 1294procedure DMA1_interrupt; external name 'DMA1_interrupt'; 1295procedure DMA2_interrupt; external name 'DMA2_interrupt'; 1296procedure DMA3_interrupt; external name 'DMA3_interrupt'; 1297procedure DMA4_interrupt; external name 'DMA4_interrupt'; 1298procedure DMA5_interrupt; external name 'DMA5_interrupt'; 1299procedure DMA6_interrupt; external name 'DMA6_interrupt'; 1300procedure DMA7_interrupt; external name 'DMA7_interrupt'; 1301procedure DMA8_interrupt; external name 'DMA8_interrupt'; 1302procedure DMA9_interrupt; external name 'DMA9_interrupt'; 1303procedure DMA10_interrupt; external name 'DMA10_interrupt'; 1304procedure DMA11_interrupt; external name 'DMA11_interrupt'; 1305procedure DMA12_interrupt; external name 'DMA12_interrupt'; 1306procedure DMA13_interrupt; external name 'DMA13_interrupt'; 1307procedure DMA14_interrupt; external name 'DMA14_interrupt'; 1308procedure DMA15_interrupt; external name 'DMA15_interrupt'; 1309procedure DMA_Error_interrupt; external name 'DMA_Error_interrupt'; 1310procedure MCM_interrupt; external name 'MCM_interrupt'; 1311procedure FTFL_interrupt; external name 'FTFL_interrupt'; 1312procedure Read_Collision_interrupt; external name 'Read_Collision_interrupt'; 1313procedure LVD_LVW_interrupt; external name 'LVD_LVW_interrupt'; 1314procedure LLW_interrupt; external name 'LLW_interrupt'; 1315procedure Watchdog_interrupt; external name 'Watchdog_interrupt'; 1316procedure RESERVED39_interrupt; external name 'RESERVED39_interrupt'; 1317procedure I2C0_interrupt; external name 'I2C0_interrupt'; 1318procedure I2C1_interrupt; external name 'I2C1_interrupt'; 1319procedure SPI0_interrupt; external name 'SPI0_interrupt'; 1320procedure SPI1_interrupt; external name 'SPI1_interrupt'; 1321procedure RESERVED44_interrupt; external name 'RESERVED44_interrupt'; 1322procedure CAN0_ORed_Message_buffer_interrupt; external name 'CAN0_ORed_Message_buffer_interrupt'; 1323procedure CAN0_Bus_Off_interrupt; external name 'CAN0_Bus_Off_interrupt'; 1324procedure CAN0_Error_interrupt; external name 'CAN0_Error_interrupt'; 1325procedure CAN0_Tx_Warning_interrupt; external name 'CAN0_Tx_Warning_interrupt'; 1326procedure CAN0_Rx_Warning_interrupt; external name 'CAN0_Rx_Warning_interrupt'; 1327procedure CAN0_Wake_Up_interrupt; external name 'CAN0_Wake_Up_interrupt'; 1328procedure I2S0_Tx_interrupt; external name 'I2S0_Tx_interrupt'; 1329procedure I2S0_Rx_interrupt; external name 'I2S0_Rx_interrupt'; 1330procedure RESERVED53_interrupt; external name 'RESERVED53_interrupt'; 1331procedure RESERVED54_interrupt; external name 'RESERVED54_interrupt'; 1332procedure RESERVED55_interrupt; external name 'RESERVED55_interrupt'; 1333procedure RESERVED56_interrupt; external name 'RESERVED56_interrupt'; 1334procedure RESERVED57_interrupt; external name 'RESERVED57_interrupt'; 1335procedure RESERVED58_interrupt; external name 'RESERVED58_interrupt'; 1336procedure RESERVED59_interrupt; external name 'RESERVED59_interrupt'; 1337procedure UART0_LON_interrupt; external name 'UART0_LON_interrupt'; 1338procedure UART0_RX_TX_interrupt; external name 'UART0_RX_TX_interrupt'; 1339procedure UART0_ERR_interrupt; external name 'UART0_ERR_interrupt'; 1340procedure UART1_RX_TX_interrupt; external name 'UART1_RX_TX_interrupt'; 1341procedure UART1_ERR_interrupt; external name 'UART1_ERR_interrupt'; 1342procedure UART2_RX_TX_interrupt; external name 'UART2_RX_TX_interrupt'; 1343procedure UART2_ERR_interrupt; external name 'UART2_ERR_interrupt'; 1344procedure UART3_RX_TX_interrupt; external name 'UART3_RX_TX_interrupt'; 1345procedure UART3_ERR_interrupt; external name 'UART3_ERR_interrupt'; 1346procedure UART4_RX_TX_interrupt; external name 'UART4_RX_TX_interrupt'; 1347procedure UART4_ERR_interrupt; external name 'UART4_ERR_interrupt'; 1348procedure RESERVED71_interrupt; external name 'RESERVED71_interrupt'; 1349procedure RESERVED72_interrupt; external name 'RESERVED72_interrupt'; 1350procedure ADC0_interrupt; external name 'ADC0_interrupt'; 1351procedure ADC1_interrupt; external name 'ADC1_interrupt'; 1352procedure CMP0_interrupt; external name 'CMP0_interrupt'; 1353procedure CMP1_interrupt; external name 'CMP1_interrupt'; 1354procedure CMP2_interrupt; external name 'CMP2_interrupt'; 1355procedure FTM0_interrupt; external name 'FTM0_interrupt'; 1356procedure FTM1_interrupt; external name 'FTM1_interrupt'; 1357procedure FTM2_interrupt; external name 'FTM2_interrupt'; 1358procedure CMT_interrupt; external name 'CMT_interrupt'; 1359procedure RTC_interrupt; external name 'RTC_interrupt'; 1360procedure RTC_Seconds_interrupt; external name 'RTC_Seconds_interrupt'; 1361procedure PIT0_interrupt; external name 'PIT0_interrupt'; 1362procedure PIT1_interrupt; external name 'PIT1_interrupt'; 1363procedure PIT2_interrupt; external name 'PIT2_interrupt'; 1364procedure PIT3_interrupt; external name 'PIT3_interrupt'; 1365procedure PDB0_interrupt; external name 'PDB0_interrupt'; 1366procedure USB0_interrupt; external name 'USB0_interrupt'; 1367procedure USBDCD_interrupt; external name 'USBDCD_interrupt'; 1368procedure RESERVED91_interrupt; external name 'RESERVED91_interrupt'; 1369procedure RESERVED92_interrupt; external name 'RESERVED92_interrupt'; 1370procedure RESERVED93_interrupt; external name 'RESERVED93_interrupt'; 1371procedure RESERVED94_interrupt; external name 'RESERVED94_interrupt'; 1372procedure RESERVED95_interrupt; external name 'RESERVED95_interrupt'; 1373procedure RESERVED96_interrupt; external name 'RESERVED96_interrupt'; 1374procedure DAC0_interrupt; external name 'DAC0_interrupt'; 1375procedure RESERVED98_interrupt; external name 'RESERVED98_interrupt'; 1376procedure TSI0_interrupt; external name 'TSI0_interrupt'; 1377procedure MCG_interrupt; external name 'MCG_interrupt'; 1378procedure LPTimer_interrupt; external name 'LPTimer_interrupt'; 1379procedure RESERVED102_interrupt; external name 'RESERVED102_interrupt'; 1380procedure PORTA_interrupt; external name 'PORTA_interrupt'; 1381procedure PORTB_interrupt; external name 'PORTB_interrupt'; 1382procedure PORTC_interrupt; external name 'PORTC_interrupt'; 1383procedure PORTD_interrupt; external name 'PORTD_interrupt'; 1384procedure PORTE_interrupt; external name 'PORTE_interrupt'; 1385procedure RESERVED108_interrupt; external name 'RESERVED108_interrupt'; 1386procedure RESERVED109_interrupt; external name 'RESERVED109_interrupt'; 1387procedure SWI_interrupt; external name 'SWI_interrupt'; 1388 1389{$i cortexm4f_start.inc} 1390 1391procedure FlashConfiguration; assembler; nostackframe; 1392label flash_conf; 1393asm 1394 .section ".flash_config.flash_conf" 1395flash_conf: 1396 .byte 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF 1397 1398 .text 1399end; 1400 1401procedure LowLevelStartup; assembler; nostackframe; [public, alias: '_LOWLEVELSTART']; 1402asm 1403 // Unlock watchdog 1404 ldr r0, .LWDOG_BASE 1405 movw r1, #50464 1406 strh r1, [r0, #0xE] 1407 movw r1, #55592 1408 strh r1, [r0, #0xE] 1409 nop 1410 nop 1411 // Disable watchdog for now 1412 movs r1, #0 1413 strh r1, [r0, #0] 1414 1415 b Startup 1416 1417.LWDOG_BASE: 1418 .long 0x40052000 1419end; 1420 1421procedure Vectors; assembler; nostackframe; 1422label interrupt_vectors; 1423asm 1424 .section ".init.interrupt_vectors" 1425 interrupt_vectors: 1426 .long _stack_top 1427 .long LowLevelStartup 1428 .long NonMaskableInt_interrupt 1429 .long 0 1430 .long MemoryManagement_interrupt 1431 .long BusFault_interrupt 1432 .long UsageFault_interrupt 1433 .long 0 1434 .long 0 1435 .long 0 1436 .long 0 1437 .long SVCall_interrupt 1438 .long DebugMonitor_interrupt 1439 .long 0 1440 .long PendSV_interrupt 1441 .long SysTick_interrupt 1442 .long DMA0_interrupt 1443 .long DMA1_interrupt 1444 .long DMA2_interrupt 1445 .long DMA3_interrupt 1446 .long DMA4_interrupt 1447 .long DMA5_interrupt 1448 .long DMA6_interrupt 1449 .long DMA7_interrupt 1450 .long DMA8_interrupt 1451 .long DMA9_interrupt 1452 .long DMA10_interrupt 1453 .long DMA11_interrupt 1454 .long DMA12_interrupt 1455 .long DMA13_interrupt 1456 .long DMA14_interrupt 1457 .long DMA15_interrupt 1458 .long DMA_Error_interrupt 1459 .long MCM_interrupt 1460 .long FTFL_interrupt 1461 .long Read_Collision_interrupt 1462 .long LVD_LVW_interrupt 1463 .long LLW_interrupt 1464 .long Watchdog_interrupt 1465 .long RESERVED39_interrupt 1466 .long I2C0_interrupt 1467 .long I2C1_interrupt 1468 .long SPI0_interrupt 1469 .long SPI1_interrupt 1470 .long RESERVED44_interrupt 1471 .long CAN0_ORed_Message_buffer_interrupt 1472 .long CAN0_Bus_Off_interrupt 1473 .long CAN0_Error_interrupt 1474 .long CAN0_Tx_Warning_interrupt 1475 .long CAN0_Rx_Warning_interrupt 1476 .long CAN0_Wake_Up_interrupt 1477 .long I2S0_Tx_interrupt 1478 .long I2S0_Rx_interrupt 1479 .long RESERVED53_interrupt 1480 .long RESERVED54_interrupt 1481 .long RESERVED55_interrupt 1482 .long RESERVED56_interrupt 1483 .long RESERVED57_interrupt 1484 .long RESERVED58_interrupt 1485 .long RESERVED59_interrupt 1486 .long UART0_LON_interrupt 1487 .long UART0_RX_TX_interrupt 1488 .long UART0_ERR_interrupt 1489 .long UART1_RX_TX_interrupt 1490 .long UART1_ERR_interrupt 1491 .long UART2_RX_TX_interrupt 1492 .long UART2_ERR_interrupt 1493 .long UART3_RX_TX_interrupt 1494 .long UART3_ERR_interrupt 1495 .long UART4_RX_TX_interrupt 1496 .long UART4_ERR_interrupt 1497 .long RESERVED71_interrupt 1498 .long RESERVED72_interrupt 1499 .long ADC0_interrupt 1500 .long ADC1_interrupt 1501 .long CMP0_interrupt 1502 .long CMP1_interrupt 1503 .long CMP2_interrupt 1504 .long FTM0_interrupt 1505 .long FTM1_interrupt 1506 .long FTM2_interrupt 1507 .long CMT_interrupt 1508 .long RTC_interrupt 1509 .long RTC_Seconds_interrupt 1510 .long PIT0_interrupt 1511 .long PIT1_interrupt 1512 .long PIT2_interrupt 1513 .long PIT3_interrupt 1514 .long PDB0_interrupt 1515 .long USB0_interrupt 1516 .long USBDCD_interrupt 1517 .long RESERVED91_interrupt 1518 .long RESERVED92_interrupt 1519 .long RESERVED93_interrupt 1520 .long RESERVED94_interrupt 1521 .long RESERVED95_interrupt 1522 .long RESERVED96_interrupt 1523 .long DAC0_interrupt 1524 .long RESERVED98_interrupt 1525 .long TSI0_interrupt 1526 .long MCG_interrupt 1527 .long LPTimer_interrupt 1528 .long RESERVED102_interrupt 1529 .long PORTA_interrupt 1530 .long PORTB_interrupt 1531 .long PORTC_interrupt 1532 .long PORTD_interrupt 1533 .long PORTE_interrupt 1534 .long RESERVED108_interrupt 1535 .long RESERVED109_interrupt 1536 .long SWI_interrupt 1537 1538 .weak NonMaskableInt_interrupt 1539 .weak MemoryManagement_interrupt 1540 .weak BusFault_interrupt 1541 .weak UsageFault_interrupt 1542 .weak SVCall_interrupt 1543 .weak DebugMonitor_interrupt 1544 .weak PendSV_interrupt 1545 .weak SysTick_interrupt 1546 .weak DMA0_interrupt 1547 .weak DMA1_interrupt 1548 .weak DMA2_interrupt 1549 .weak DMA3_interrupt 1550 .weak DMA4_interrupt 1551 .weak DMA5_interrupt 1552 .weak DMA6_interrupt 1553 .weak DMA7_interrupt 1554 .weak DMA8_interrupt 1555 .weak DMA9_interrupt 1556 .weak DMA10_interrupt 1557 .weak DMA11_interrupt 1558 .weak DMA12_interrupt 1559 .weak DMA13_interrupt 1560 .weak DMA14_interrupt 1561 .weak DMA15_interrupt 1562 .weak DMA_Error_interrupt 1563 .weak MCM_interrupt 1564 .weak FTFL_interrupt 1565 .weak Read_Collision_interrupt 1566 .weak LVD_LVW_interrupt 1567 .weak LLW_interrupt 1568 .weak Watchdog_interrupt 1569 .weak RESERVED39_interrupt 1570 .weak I2C0_interrupt 1571 .weak I2C1_interrupt 1572 .weak SPI0_interrupt 1573 .weak SPI1_interrupt 1574 .weak RESERVED44_interrupt 1575 .weak CAN0_ORed_Message_buffer_interrupt 1576 .weak CAN0_Bus_Off_interrupt 1577 .weak CAN0_Error_interrupt 1578 .weak CAN0_Tx_Warning_interrupt 1579 .weak CAN0_Rx_Warning_interrupt 1580 .weak CAN0_Wake_Up_interrupt 1581 .weak I2S0_Tx_interrupt 1582 .weak I2S0_Rx_interrupt 1583 .weak RESERVED53_interrupt 1584 .weak RESERVED54_interrupt 1585 .weak RESERVED55_interrupt 1586 .weak RESERVED56_interrupt 1587 .weak RESERVED57_interrupt 1588 .weak RESERVED58_interrupt 1589 .weak RESERVED59_interrupt 1590 .weak UART0_LON_interrupt 1591 .weak UART0_RX_TX_interrupt 1592 .weak UART0_ERR_interrupt 1593 .weak UART1_RX_TX_interrupt 1594 .weak UART1_ERR_interrupt 1595 .weak UART2_RX_TX_interrupt 1596 .weak UART2_ERR_interrupt 1597 .weak UART3_RX_TX_interrupt 1598 .weak UART3_ERR_interrupt 1599 .weak UART4_RX_TX_interrupt 1600 .weak UART4_ERR_interrupt 1601 .weak RESERVED71_interrupt 1602 .weak RESERVED72_interrupt 1603 .weak ADC0_interrupt 1604 .weak ADC1_interrupt 1605 .weak CMP0_interrupt 1606 .weak CMP1_interrupt 1607 .weak CMP2_interrupt 1608 .weak FTM0_interrupt 1609 .weak FTM1_interrupt 1610 .weak FTM2_interrupt 1611 .weak CMT_interrupt 1612 .weak RTC_interrupt 1613 .weak RTC_Seconds_interrupt 1614 .weak PIT0_interrupt 1615 .weak PIT1_interrupt 1616 .weak PIT2_interrupt 1617 .weak PIT3_interrupt 1618 .weak PDB0_interrupt 1619 .weak USB0_interrupt 1620 .weak USBDCD_interrupt 1621 .weak RESERVED91_interrupt 1622 .weak RESERVED92_interrupt 1623 .weak RESERVED93_interrupt 1624 .weak RESERVED94_interrupt 1625 .weak RESERVED95_interrupt 1626 .weak RESERVED96_interrupt 1627 .weak DAC0_interrupt 1628 .weak RESERVED98_interrupt 1629 .weak TSI0_interrupt 1630 .weak MCG_interrupt 1631 .weak LPTimer_interrupt 1632 .weak RESERVED102_interrupt 1633 .weak PORTA_interrupt 1634 .weak PORTB_interrupt 1635 .weak PORTC_interrupt 1636 .weak PORTD_interrupt 1637 .weak PORTE_interrupt 1638 .weak RESERVED108_interrupt 1639 .weak RESERVED109_interrupt 1640 .weak SWI_interrupt 1641 .set NonMaskableInt_interrupt, HaltProc 1642 .set MemoryManagement_interrupt, HaltProc 1643 .set BusFault_interrupt, HaltProc 1644 .set UsageFault_interrupt, HaltProc 1645 .set SVCall_interrupt, HaltProc 1646 .set DebugMonitor_interrupt, HaltProc 1647 .set PendSV_interrupt, HaltProc 1648 .set SysTick_interrupt, HaltProc 1649 .set DMA0_interrupt, HaltProc 1650 .set DMA1_interrupt, HaltProc 1651 .set DMA2_interrupt, HaltProc 1652 .set DMA3_interrupt, HaltProc 1653 .set DMA4_interrupt, HaltProc 1654 .set DMA5_interrupt, HaltProc 1655 .set DMA6_interrupt, HaltProc 1656 .set DMA7_interrupt, HaltProc 1657 .set DMA8_interrupt, HaltProc 1658 .set DMA9_interrupt, HaltProc 1659 .set DMA10_interrupt, HaltProc 1660 .set DMA11_interrupt, HaltProc 1661 .set DMA12_interrupt, HaltProc 1662 .set DMA13_interrupt, HaltProc 1663 .set DMA14_interrupt, HaltProc 1664 .set DMA15_interrupt, HaltProc 1665 .set DMA_Error_interrupt, HaltProc 1666 .set MCM_interrupt, HaltProc 1667 .set FTFL_interrupt, HaltProc 1668 .set Read_Collision_interrupt, HaltProc 1669 .set LVD_LVW_interrupt, HaltProc 1670 .set LLW_interrupt, HaltProc 1671 .set Watchdog_interrupt, HaltProc 1672 .set RESERVED39_interrupt, HaltProc 1673 .set I2C0_interrupt, HaltProc 1674 .set I2C1_interrupt, HaltProc 1675 .set SPI0_interrupt, HaltProc 1676 .set SPI1_interrupt, HaltProc 1677 .set RESERVED44_interrupt, HaltProc 1678 .set CAN0_ORed_Message_buffer_interrupt, HaltProc 1679 .set CAN0_Bus_Off_interrupt, HaltProc 1680 .set CAN0_Error_interrupt, HaltProc 1681 .set CAN0_Tx_Warning_interrupt, HaltProc 1682 .set CAN0_Rx_Warning_interrupt, HaltProc 1683 .set CAN0_Wake_Up_interrupt, HaltProc 1684 .set I2S0_Tx_interrupt, HaltProc 1685 .set I2S0_Rx_interrupt, HaltProc 1686 .set RESERVED53_interrupt, HaltProc 1687 .set RESERVED54_interrupt, HaltProc 1688 .set RESERVED55_interrupt, HaltProc 1689 .set RESERVED56_interrupt, HaltProc 1690 .set RESERVED57_interrupt, HaltProc 1691 .set RESERVED58_interrupt, HaltProc 1692 .set RESERVED59_interrupt, HaltProc 1693 .set UART0_LON_interrupt, HaltProc 1694 .set UART0_RX_TX_interrupt, HaltProc 1695 .set UART0_ERR_interrupt, HaltProc 1696 .set UART1_RX_TX_interrupt, HaltProc 1697 .set UART1_ERR_interrupt, HaltProc 1698 .set UART2_RX_TX_interrupt, HaltProc 1699 .set UART2_ERR_interrupt, HaltProc 1700 .set UART3_RX_TX_interrupt, HaltProc 1701 .set UART3_ERR_interrupt, HaltProc 1702 .set UART4_RX_TX_interrupt, HaltProc 1703 .set UART4_ERR_interrupt, HaltProc 1704 .set RESERVED71_interrupt, HaltProc 1705 .set RESERVED72_interrupt, HaltProc 1706 .set ADC0_interrupt, HaltProc 1707 .set ADC1_interrupt, HaltProc 1708 .set CMP0_interrupt, HaltProc 1709 .set CMP1_interrupt, HaltProc 1710 .set CMP2_interrupt, HaltProc 1711 .set FTM0_interrupt, HaltProc 1712 .set FTM1_interrupt, HaltProc 1713 .set FTM2_interrupt, HaltProc 1714 .set CMT_interrupt, HaltProc 1715 .set RTC_interrupt, HaltProc 1716 .set RTC_Seconds_interrupt, HaltProc 1717 .set PIT0_interrupt, HaltProc 1718 .set PIT1_interrupt, HaltProc 1719 .set PIT2_interrupt, HaltProc 1720 .set PIT3_interrupt, HaltProc 1721 .set PDB0_interrupt, HaltProc 1722 .set USB0_interrupt, HaltProc 1723 .set USBDCD_interrupt, HaltProc 1724 .set RESERVED91_interrupt, HaltProc 1725 .set RESERVED92_interrupt, HaltProc 1726 .set RESERVED93_interrupt, HaltProc 1727 .set RESERVED94_interrupt, HaltProc 1728 .set RESERVED95_interrupt, HaltProc 1729 .set RESERVED96_interrupt, HaltProc 1730 .set DAC0_interrupt, HaltProc 1731 .set RESERVED98_interrupt, HaltProc 1732 .set TSI0_interrupt, HaltProc 1733 .set MCG_interrupt, HaltProc 1734 .set LPTimer_interrupt, HaltProc 1735 .set RESERVED102_interrupt, HaltProc 1736 .set PORTA_interrupt, HaltProc 1737 .set PORTB_interrupt, HaltProc 1738 .set PORTC_interrupt, HaltProc 1739 .set PORTD_interrupt, HaltProc 1740 .set PORTE_interrupt, HaltProc 1741 .set RESERVED108_interrupt, HaltProc 1742 .set RESERVED109_interrupt, HaltProc 1743 .set SWI_interrupt, HaltProc 1744 .text 1745end; 1746end. 1747