1unit ATmega32U4; 2 3{$goto on} 4 5interface 6 7var 8 // WATCHDOG 9 WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register 10 // PORTD 11 PORTD : byte absolute $00+$2B; // Port D Data Register 12 DDRD : byte absolute $00+$2A; // Port D Data Direction Register 13 PIND : byte absolute $00+$29; // Port D Input Pins 14 // SPI 15 SPCR : byte absolute $00+$4C; // SPI Control Register 16 SPSR : byte absolute $00+$4D; // SPI Status Register 17 SPDR : byte absolute $00+$4E; // SPI Data Register 18 // USART1 19 UDR1 : byte absolute $00+$CE; // USART I/O Data Register 20 UCSR1A : byte absolute $00+$C8; // USART Control and Status Register A 21 UCSR1B : byte absolute $00+$C9; // USART Control and Status Register B 22 UCSR1C : byte absolute $00+$CA; // USART Control and Status Register C 23 UBRR1 : word absolute $00+$CC; // USART Baud Rate Register Bytes 24 UBRR1L : byte absolute $00+$CC; // USART Baud Rate Register Bytes 25 UBRR1H : byte absolute $00+$CC+1; // USART Baud Rate Register Bytes 26 // BOOT_LOAD 27 SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register 28 // EEPROM 29 EEAR : word absolute $00+$41; // EEPROM Address Register Low Bytes 30 EEARL : byte absolute $00+$41; // EEPROM Address Register Low Bytes 31 EEARH : byte absolute $00+$41+1; // EEPROM Address Register Low Bytes 32 EEDR : byte absolute $00+$40; // EEPROM Data Register 33 EECR : byte absolute $00+$3F; // EEPROM Control Register 34 // TIMER_COUNTER_0 35 OCR0B : byte absolute $00+$48; // Timer/Counter0 Output Compare Register 36 OCR0A : byte absolute $00+$47; // Timer/Counter0 Output Compare Register 37 TCNT0 : byte absolute $00+$46; // Timer/Counter0 38 TCCR0B : byte absolute $00+$45; // Timer/Counter Control Register B 39 TCCR0A : byte absolute $00+$44; // Timer/Counter Control Register A 40 TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask Register 41 TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag register 42 GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register 43 // TIMER_COUNTER_3 44 TCCR3A : byte absolute $00+$90; // Timer/Counter3 Control Register A 45 TCCR3B : byte absolute $00+$91; // Timer/Counter3 Control Register B 46 TCCR3C : byte absolute $00+$92; // Timer/Counter 3 Control Register C 47 TCNT3 : word absolute $00+$94; // Timer/Counter3 Bytes 48 TCNT3L : byte absolute $00+$94; // Timer/Counter3 Bytes 49 TCNT3H : byte absolute $00+$94+1; // Timer/Counter3 Bytes 50 OCR3A : word absolute $00+$98; // Timer/Counter3 Output Compare Register A Bytes 51 OCR3AL : byte absolute $00+$98; // Timer/Counter3 Output Compare Register A Bytes 52 OCR3AH : byte absolute $00+$98+1; // Timer/Counter3 Output Compare Register A Bytes 53 OCR3B : word absolute $00+$9A; // Timer/Counter3 Output Compare Register B Bytes 54 OCR3BL : byte absolute $00+$9A; // Timer/Counter3 Output Compare Register B Bytes 55 OCR3BH : byte absolute $00+$9A+1; // Timer/Counter3 Output Compare Register B Bytes 56 OCR3C : word absolute $00+$9C; // Timer/Counter3 Output Compare Register B Bytes 57 OCR3CL : byte absolute $00+$9C; // Timer/Counter3 Output Compare Register B Bytes 58 OCR3CH : byte absolute $00+$9C+1; // Timer/Counter3 Output Compare Register B Bytes 59 ICR3 : word absolute $00+$96; // Timer/Counter3 Input Capture Register Bytes 60 ICR3L : byte absolute $00+$96; // Timer/Counter3 Input Capture Register Bytes 61 ICR3H : byte absolute $00+$96+1; // Timer/Counter3 Input Capture Register Bytes 62 TIMSK3 : byte absolute $00+$71; // Timer/Counter3 Interrupt Mask Register 63 TIFR3 : byte absolute $00+$38; // Timer/Counter3 Interrupt Flag register 64 // TIMER_COUNTER_1 65 TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A 66 TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B 67 TCCR1C : byte absolute $00+$82; // Timer/Counter 1 Control Register C 68 TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes 69 TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes 70 TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes 71 OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register A Bytes 72 OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register A Bytes 73 OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register A Bytes 74 OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register B Bytes 75 OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register B Bytes 76 OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register B Bytes 77 OCR1C : word absolute $00+$8C; // Timer/Counter1 Output Compare Register C Bytes 78 OCR1CL : byte absolute $00+$8C; // Timer/Counter1 Output Compare Register C Bytes 79 OCR1CH : byte absolute $00+$8C+1; // Timer/Counter1 Output Compare Register C Bytes 80 ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 81 ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes 82 ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes 83 TIMSK1 : byte absolute $00+$6F; // Timer/Counter1 Interrupt Mask Register 84 TIFR1 : byte absolute $00+$36; // Timer/Counter1 Interrupt Flag register 85 // JTAG 86 OCDR : byte absolute $00+$51; // On-Chip Debug Related Register in I/O Memory 87 MCUCR : byte absolute $00+$55; // MCU Control Register 88 MCUSR : byte absolute $00+$54; // MCU Status Register 89 // EXTERNAL_INTERRUPT 90 EICRA : byte absolute $00+$69; // External Interrupt Control Register A 91 EICRB : byte absolute $00+$6A; // External Interrupt Control Register B 92 EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register 93 EIFR : byte absolute $00+$3C; // External Interrupt Flag Register 94 PCMSK0 : byte absolute $00+$6B; // Pin Change Mask Register 0 95 PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register 96 PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register 97 // TIMER_COUNTER_4 98 TCCR4A : byte absolute $00+$C0; // Timer/Counter4 Control Register A 99 TCCR4B : byte absolute $00+$C1; // Timer/Counter4 Control Register B 100 TCCR4C : byte absolute $00+$C2; // Timer/Counter 4 Control Register C 101 TCCR4D : byte absolute $00+$C3; // Timer/Counter 4 Control Register D 102 TCCR4E : byte absolute $00+$C4; // Timer/Counter 4 Control Register E 103 TCNT4 : byte absolute $00+$BE; // Timer/Counter4 Low Bytes 104 TC4H : byte absolute $00+$BF; // Timer/Counter4 105 OCR4A : byte absolute $00+$CF; // Timer/Counter4 Output Compare Register A 106 OCR4B : byte absolute $00+$D0; // Timer/Counter4 Output Compare Register B 107 OCR4C : byte absolute $00+$D1; // Timer/Counter4 Output Compare Register C 108 OCR4D : byte absolute $00+$D2; // Timer/Counter4 Output Compare Register D 109 TIMSK4 : byte absolute $00+$72; // Timer/Counter4 Interrupt Mask Register 110 TIFR4 : byte absolute $00+$39; // Timer/Counter4 Interrupt Flag register 111 DT4 : byte absolute $00+$D4; // Timer/Counter 4 Dead Time Value 112 // PORTB 113 PORTB : byte absolute $00+$25; // Port B Data Register 114 DDRB : byte absolute $00+$24; // Port B Data Direction Register 115 PINB : byte absolute $00+$23; // Port B Input Pins 116 // PORTC 117 PORTC : byte absolute $00+$28; // Port C Data Register 118 DDRC : byte absolute $00+$27; // Port C Data Direction Register 119 PINC : byte absolute $00+$26; // Port C Input Pins 120 // PORTE 121 PORTE : byte absolute $00+$2E; // Data Register, Port E 122 DDRE : byte absolute $00+$2D; // Data Direction Register, Port E 123 PINE : byte absolute $00+$2C; // Input Pins, Port E 124 // PORTF 125 PORTF : byte absolute $00+$31; // Data Register, Port F 126 DDRF : byte absolute $00+$30; // Data Direction Register, Port F 127 PINF : byte absolute $00+$2F; // Input Pins, Port F 128 // TWI 129 TWAMR : byte absolute $00+$BD; // TWI (Slave) Address Mask Register 130 TWBR : byte absolute $00+$B8; // TWI Bit Rate register 131 TWCR : byte absolute $00+$BC; // TWI Control Register 132 TWSR : byte absolute $00+$B9; // TWI Status Register 133 TWDR : byte absolute $00+$BB; // TWI Data register 134 TWAR : byte absolute $00+$BA; // TWI (Slave) Address register 135 // AD_CONVERTER 136 ADMUX : byte absolute $00+$7C; // The ADC multiplexer Selection Register 137 ADCSRA : byte absolute $00+$7A; // The ADC Control and Status register 138 ADC : word absolute $00+$78; // ADC Data Register Bytes 139 ADCL : byte absolute $00+$78; // ADC Data Register Bytes 140 ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes 141 ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B 142 DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 1 143 DIDR2 : byte absolute $00+$7D; // Digital Input Disable Register 1 144 // ANALOG_COMPARATOR 145 ACSR : byte absolute $00+$50; // Analog Comparator Control And Status Register 146 DIDR1 : byte absolute $00+$7F; // 147 // CPU 148 SREG : byte absolute $00+$5F; // Status Register 149 SP : word absolute $00+$5D; // Stack Pointer 150 SPL : byte absolute $00+$5D; // Stack Pointer 151 SPH : byte absolute $00+$5D+1; // Stack Pointer 152 OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value 153 RCCTRL : byte absolute $00+$67; // Oscillator Control Register 154 CLKPR : byte absolute $00+$61; // 155 SMCR : byte absolute $00+$53; // Sleep Mode Control Register 156 EIND : byte absolute $00+$5C; // Extended Indirect Register 157 GPIOR2 : byte absolute $00+$4B; // General Purpose IO Register 2 158 GPIOR1 : byte absolute $00+$4A; // General Purpose IO Register 1 159 GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0 160 PRR1 : byte absolute $00+$65; // Power Reduction Register1 161 PRR0 : byte absolute $00+$64; // Power Reduction Register0 162 CLKSTA : byte absolute $00+$C7; // 163 CLKSEL1 : byte absolute $00+$C6; // 164 CLKSEL0 : byte absolute $00+$C5; // 165 // PLL 166 PLLCSR : byte absolute $00+$49; // PLL Status and Control register 167 PLLFRQ : byte absolute $00+$52; // PLL Frequency Control Register 168 // USB_DEVICE 169 UEINT : byte absolute $00+$F4; // 170 UEBCHX : byte absolute $00+$F3; // 171 UEBCLX : byte absolute $00+$F2; // 172 UEDATX : byte absolute $00+$F1; // 173 UEIENX : byte absolute $00+$F0; // 174 UESTA1X : byte absolute $00+$EF; // 175 UESTA0X : byte absolute $00+$EE; // 176 UECFG1X : byte absolute $00+$ED; // 177 UECFG0X : byte absolute $00+$EC; // 178 UECONX : byte absolute $00+$EB; // 179 UERST : byte absolute $00+$EA; // 180 UENUM : byte absolute $00+$E9; // 181 UEINTX : byte absolute $00+$E8; // 182 UDMFN : byte absolute $00+$E6; // 183 UDFNUM : word absolute $00+$E4; // 184 UDFNUML : byte absolute $00+$E4; // 185 UDFNUMH : byte absolute $00+$E4+1; // 186 UDADDR : byte absolute $00+$E3; // 187 UDIEN : byte absolute $00+$E2; // 188 UDINT : byte absolute $00+$E1; // 189 UDCON : byte absolute $00+$E0; // 190 USBCON : byte absolute $00+$D8; // USB General Control Register 191 USBINT : byte absolute $00+$DA; // 192 USBSTA : byte absolute $00+$D9; // 193 UHWCON : byte absolute $00+$D7; // 194 195const 196 // WDTCSR 197 WDIF = 7; // Watchdog Timeout Interrupt Flag 198 WDIE = 6; // Watchdog Timeout Interrupt Enable 199 WDP = 0; // Watchdog Timer Prescaler Bits 200 WDCE = 4; // Watchdog Change Enable 201 WDE = 3; // Watch Dog Enable 202 // SPCR 203 SPIE = 7; // SPI Interrupt Enable 204 SPE = 6; // SPI Enable 205 DORD = 5; // Data Order 206 MSTR = 4; // Master/Slave Select 207 CPOL = 3; // Clock polarity 208 CPHA = 2; // Clock Phase 209 SPR = 0; // SPI Clock Rate Selects 210 // SPSR 211 SPIF = 7; // SPI Interrupt Flag 212 WCOL = 6; // Write Collision Flag 213 SPI2X = 0; // Double SPI Speed Bit 214 // UCSR1A 215 RXC1 = 7; // USART Receive Complete 216 TXC1 = 6; // USART Transmitt Complete 217 UDRE1 = 5; // USART Data Register Empty 218 FE1 = 4; // Framing Error 219 DOR1 = 3; // Data overRun 220 UPE1 = 2; // Parity Error 221 U2X1 = 1; // Double the USART transmission speed 222 MPCM1 = 0; // Multi-processor Communication Mode 223 // UCSR1B 224 RXCIE1 = 7; // RX Complete Interrupt Enable 225 TXCIE1 = 6; // TX Complete Interrupt Enable 226 UDRIE1 = 5; // USART Data register Empty Interrupt Enable 227 RXEN1 = 4; // Receiver Enable 228 TXEN1 = 3; // Transmitter Enable 229 UCSZ12 = 2; // Character Size 230 RXB81 = 1; // Receive Data Bit 8 231 TXB81 = 0; // Transmit Data Bit 8 232 // UCSR1C 233 UMSEL1 = 6; // USART Mode Select 234 UPM1 = 4; // Parity Mode Bits 235 USBS1 = 3; // Stop Bit Select 236 UCSZ1 = 1; // Character Size 237 UCPOL1 = 0; // Clock Polarity 238 // SPMCSR 239 SPMIE = 7; // SPM Interrupt Enable 240 RWWSB = 6; // Read While Write Section Busy 241 SIGRD = 5; // Signature Row Read 242 RWWSRE = 4; // Read While Write section read enable 243 BLBSET = 3; // Boot Lock Bit Set 244 PGWRT = 2; // Page Write 245 PGERS = 1; // Page Erase 246 SPMEN = 0; // Store Program Memory Enable 247 // EECR 248 EEPM = 4; // EEPROM Programming Mode Bits 249 EERIE = 3; // EEPROM Ready Interrupt Enable 250 EEMPE = 2; // EEPROM Master Write Enable 251 EEPE = 1; // EEPROM Write Enable 252 EERE = 0; // EEPROM Read Enable 253 // TCCR0B 254 FOC0A = 7; // Force Output Compare A 255 FOC0B = 6; // Force Output Compare B 256 WGM02 = 3; // 257 CS0 = 0; // Clock Select 258 // TCCR0A 259 COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode 260 COM0B = 4; // Compare Output Mode, Fast PWm 261 WGM0 = 0; // Waveform Generation Mode 262 // TIMSK0 263 OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable 264 OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable 265 TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable 266 // TIFR0 267 OCF0B = 2; // Timer/Counter0 Output Compare Flag 0B 268 OCF0A = 1; // Timer/Counter0 Output Compare Flag 0A 269 TOV0 = 0; // Timer/Counter0 Overflow Flag 270 // GTCCR 271 TSM = 7; // Timer/Counter Synchronization Mode 272 PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0 273 // TCCR3A 274 COM3A = 6; // Compare Output Mode 1A, bits 275 COM3B = 4; // Compare Output Mode 3B, bits 276 COM3C = 2; // Compare Output Mode 3C, bits 277 WGM3 = 0; // Waveform Generation Mode 278 // TCCR3B 279 ICNC3 = 7; // Input Capture 3 Noise Canceler 280 ICES3 = 6; // Input Capture 3 Edge Select 281 CS3 = 0; // Prescaler source of Timer/Counter 3 282 // TCCR3C 283 FOC3A = 7; // Force Output Compare 3A 284 FOC3B = 6; // Force Output Compare 3B 285 FOC3C = 5; // Force Output Compare 3C 286 // TIMSK3 287 ICIE3 = 5; // Timer/Counter3 Input Capture Interrupt Enable 288 OCIE3C = 3; // Timer/Counter3 Output Compare C Match Interrupt Enable 289 OCIE3B = 2; // Timer/Counter3 Output Compare B Match Interrupt Enable 290 OCIE3A = 1; // Timer/Counter3 Output Compare A Match Interrupt Enable 291 TOIE3 = 0; // Timer/Counter3 Overflow Interrupt Enable 292 // TIFR3 293 ICF3 = 5; // Input Capture Flag 3 294 OCF3C = 3; // Output Compare Flag 3C 295 OCF3B = 2; // Output Compare Flag 3B 296 OCF3A = 1; // Output Compare Flag 3A 297 TOV3 = 0; // Timer/Counter3 Overflow Flag 298 // TCCR1A 299 COM1A = 6; // Compare Output Mode 1A, bits 300 COM1B = 4; // Compare Output Mode 1B, bits 301 COM1C = 2; // Compare Output Mode 1C, bits 302 WGM1 = 0; // Waveform Generation Mode 303 // TCCR1B 304 ICNC1 = 7; // Input Capture 1 Noise Canceler 305 ICES1 = 6; // Input Capture 1 Edge Select 306 CS1 = 0; // Prescaler source of Timer/Counter 1 307 // TCCR1C 308 FOC1A = 7; // Force Output Compare 1A 309 FOC1B = 6; // Force Output Compare 1B 310 FOC1C = 5; // Force Output Compare 1C 311 // TIMSK1 312 ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable 313 OCIE1C = 3; // Timer/Counter1 Output Compare C Match Interrupt Enable 314 OCIE1B = 2; // Timer/Counter1 Output Compare B Match Interrupt Enable 315 OCIE1A = 1; // Timer/Counter1 Output Compare A Match Interrupt Enable 316 TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable 317 // TIFR1 318 ICF1 = 5; // Input Capture Flag 1 319 OCF1C = 3; // Output Compare Flag 1C 320 OCF1B = 2; // Output Compare Flag 1B 321 OCF1A = 1; // Output Compare Flag 1A 322 TOV1 = 0; // Timer/Counter1 Overflow Flag 323 // MCUCR 324 JTD = 7; // JTAG Interface Disable 325 // MCUSR 326 JTRF = 4; // JTAG Reset Flag 327 // EICRA 328 ISC3 = 6; // External Interrupt Sense Control Bit 329 ISC2 = 4; // External Interrupt Sense Control Bit 330 ISC1 = 2; // External Interrupt Sense Control Bit 331 ISC0 = 0; // External Interrupt Sense Control Bit 332 // EICRB 333 ISC7 = 6; // External Interrupt 7-4 Sense Control Bit 334 ISC6 = 4; // External Interrupt 7-4 Sense Control Bit 335 ISC5 = 2; // External Interrupt 7-4 Sense Control Bit 336 ISC4 = 0; // External Interrupt 7-4 Sense Control Bit 337 // EIMSK 338 INT = 0; // External Interrupt Request 7 Enable 339 // EIFR 340 INTF = 0; // External Interrupt Flags 341 // PCIFR 342 PCIF0 = 0; // Pin Change Interrupt Flag 0 343 // PCICR 344 PCIE0 = 0; // Pin Change Interrupt Enable 0 345 // TCCR4A 346 COM4A = 6; // Compare Output Mode 1A, bits 347 COM4B = 4; // Compare Output Mode 4B, bits 348 FOC4A = 3; // Force Output Compare Match 4A 349 FOC4B = 2; // Force Output Compare Match 4B 350 PWM4A = 1; // 351 PWM4B = 0; // 352 // TCCR4B 353 PWM4X = 7; // PWM Inversion Mode 354 PSR4 = 6; // Prescaler Reset Timer/Counter 4 355 DTPS4 = 4; // Dead Time Prescaler Bits 356 CS4 = 0; // Clock Select Bits 357 // TCCR4C 358 COM4A1S = 7; // Comparator A Output Mode 359 COM4A0S = 6; // Comparator A Output Mode 360 COM4B1S = 5; // Comparator B Output Mode 361 COM4B0S = 4; // Comparator B Output Mode 362 COM4D = 2; // Comparator D Output Mode 363 FOC4D = 1; // Force Output Compare Match 4D 364 PWM4D = 0; // Pulse Width Modulator D Enable 365 // TCCR4D 366 FPIE4 = 7; // Fault Protection Interrupt Enable 367 FPEN4 = 6; // Fault Protection Mode Enable 368 FPNC4 = 5; // Fault Protection Noise Canceler 369 FPES4 = 4; // Fault Protection Edge Select 370 FPAC4 = 3; // Fault Protection Analog Comparator Enable 371 FPF4 = 2; // Fault Protection Interrupt Flag 372 WGM4 = 0; // Waveform Generation Mode bits 373 // TCCR4E 374 TLOCK4 = 7; // Register Update Lock 375 ENHC4 = 6; // Enhanced Compare/PWM Mode 376 OC4OE = 0; // Output Compare Override Enable bit 377 // TIMSK4 378 OCIE4D = 7; // Timer/Counter4 Output Compare D Match Interrupt Enable 379 OCIE4A = 6; // Timer/Counter4 Output Compare A Match Interrupt Enable 380 OCIE4B = 5; // Timer/Counter4 Output Compare B Match Interrupt Enable 381 TOIE4 = 2; // Timer/Counter4 Overflow Interrupt Enable 382 // TIFR4 383 OCF4D = 7; // Output Compare Flag 4D 384 OCF4A = 6; // Output Compare Flag 4A 385 OCF4B = 5; // Output Compare Flag 4B 386 TOV4 = 2; // Timer/Counter4 Overflow Flag 387 // DT4 388 DT4L = 0; // Timer/Counter 4 Dead Time Value Bits 389 // TWAMR 390 TWAM = 1; // 391 // TWCR 392 TWINT = 7; // TWI Interrupt Flag 393 TWEA = 6; // TWI Enable Acknowledge Bit 394 TWSTA = 5; // TWI Start Condition Bit 395 TWSTO = 4; // TWI Stop Condition Bit 396 TWWC = 3; // TWI Write Collition Flag 397 TWEN = 2; // TWI Enable Bit 398 TWIE = 0; // TWI Interrupt Enable 399 // TWSR 400 TWS = 3; // TWI Status 401 TWPS = 0; // TWI Prescaler 402 // TWAR 403 TWA = 1; // TWI (Slave) Address register Bits 404 TWGCE = 0; // TWI General Call Recognition Enable Bit 405 // ADMUX 406 REFS = 6; // Reference Selection Bits 407 ADLAR = 5; // Left Adjust Result 408 MUX = 0; // Analog Channel and Gain Selection Bits 409 // ADCSRA 410 ADEN = 7; // ADC Enable 411 ADSC = 6; // ADC Start Conversion 412 ADATE = 5; // ADC Auto Trigger Enable 413 ADIF = 4; // ADC Interrupt Flag 414 ADIE = 3; // ADC Interrupt Enable 415 ADPS = 0; // ADC Prescaler Select Bits 416 // ADCSRB 417 ADHSM = 7; // ADC High Speed Mode 418 MUX5 = 5; // Analog Channel and Gain Selection Bits 419 ADTS = 0; // ADC Auto Trigger Sources 420 // DIDR0 421 ADC7D = 7; // ADC7 Digital input Disable 422 ADC6D = 6; // ADC6 Digital input Disable 423 ADC5D = 5; // ADC5 Digital input Disable 424 ADC4D = 4; // ADC4 Digital input Disable 425 ADC3D = 3; // ADC3 Digital input Disable 426 ADC2D = 2; // ADC2 Digital input Disable 427 ADC1D = 1; // ADC1 Digital input Disable 428 ADC0D = 0; // ADC0 Digital input Disable 429 // DIDR2 430 ADC13D = 5; // ADC13 Digital input Disable 431 ADC12D = 4; // ADC12 Digital input Disable 432 ADC11D = 3; // ADC11 Digital input Disable 433 ADC10D = 2; // ADC10 Digital input Disable 434 ADC9D = 1; // ADC9 Digital input Disable 435 ADC8D = 0; // ADC8 Digital input Disable 436 // ADCSRB 437 ACME = 6; // Analog Comparator Multiplexer Enable 438 // ACSR 439 ACD = 7; // Analog Comparator Disable 440 ACBG = 6; // Analog Comparator Bandgap Select 441 ACO = 5; // Analog Compare Output 442 ACI = 4; // Analog Comparator Interrupt Flag 443 ACIE = 3; // Analog Comparator Interrupt Enable 444 ACIC = 2; // Analog Comparator Input Capture Enable 445 ACIS = 0; // Analog Comparator Interrupt Mode Select bits 446 // DIDR1 447 AIN1D = 1; // AIN1 Digital Input Disable 448 AIN0D = 0; // AIN0 Digital Input Disable 449 // SREG 450 I = 7; // Global Interrupt Enable 451 T = 6; // Bit Copy Storage 452 H = 5; // Half Carry Flag 453 S = 4; // Sign Bit 454 V = 3; // Two's Complement Overflow Flag 455 N = 2; // Negative Flag 456 Z = 1; // Zero Flag 457 C = 0; // Carry Flag 458 // MCUCR 459 PUD = 4; // Pull-up disable 460 IVSEL = 1; // Interrupt Vector Select 461 IVCE = 0; // Interrupt Vector Change Enable 462 // MCUSR 463 WDRF = 3; // Watchdog Reset Flag 464 BORF = 2; // Brown-out Reset Flag 465 EXTRF = 1; // External Reset Flag 466 PORF = 0; // Power-on reset flag 467 // RCCTRL 468 RCFREQ = 0; // 469 // CLKPR 470 CLKPCE = 7; // 471 CLKPS = 0; // 472 // SMCR 473 SM = 1; // Sleep Mode Select bits 474 SE = 0; // Sleep Enable 475 // GPIOR2 476 GPIOR = 0; // General Purpose IO Register 2 bis 477 // GPIOR1 478 // GPIOR0 479 GPIOR07 = 7; // General Purpose IO Register 0 bit 7 480 GPIOR06 = 6; // General Purpose IO Register 0 bit 6 481 GPIOR05 = 5; // General Purpose IO Register 0 bit 5 482 GPIOR04 = 4; // General Purpose IO Register 0 bit 4 483 GPIOR03 = 3; // General Purpose IO Register 0 bit 3 484 GPIOR02 = 2; // General Purpose IO Register 0 bit 2 485 GPIOR01 = 1; // General Purpose IO Register 0 bit 1 486 GPIOR00 = 0; // General Purpose IO Register 0 bit 0 487 // PRR1 488 PRUSB = 7; // Power Reduction USB 489 PRTIM3 = 3; // Power Reduction Timer/Counter3 490 PRUSART1 = 0; // Power Reduction USART1 491 // PRR0 492 PRTWI = 7; // Power Reduction TWI 493 PRTIM2 = 6; // Power Reduction Timer/Counter2 494 PRTIM0 = 5; // Power Reduction Timer/Counter0 495 PRTIM1 = 3; // Power Reduction Timer/Counter1 496 PRSPI = 2; // Power Reduction Serial Peripheral Interface 497 PRUSART0 = 1; // Power Reduction USART 498 PRADC = 0; // Power Reduction ADC 499 // CLKSTA 500 RCON = 1; // 501 EXTON = 0; // 502 // CLKSEL1 503 RCCKSEL = 4; // 504 EXCKSEL = 0; // 505 // CLKSEL0 506 RCSUT = 6; // 507 EXSUT = 4; // 508 RCE = 3; // 509 EXTE = 2; // 510 CLKS = 0; // 511 // PLLCSR 512 PINDIV = 4; // PLL prescaler Bit 2 513 PLLE = 1; // PLL Enable Bit 514 PLOCK = 0; // PLL Lock Status Bit 515 // PLLFRQ 516 PINMUX = 7; // 517 PLLUSB = 6; // 518 PLLTM = 4; // 519 PDIV = 0; // 520 // UEDATX 521 DAT = 0; // 522 // UEIENX 523 FLERRE = 7; // 524 NAKINE = 6; // 525 NAKOUTE = 4; // 526 RXSTPE = 3; // 527 RXOUTE = 2; // 528 STALLEDE = 1; // 529 TXINE = 0; // 530 // UESTA1X 531 CTRLDIR = 2; // 532 CURRBK = 0; // 533 // UESTA0X 534 CFGOK = 7; // 535 OVERFI = 6; // 536 UNDERFI = 5; // 537 DTSEQ = 2; // 538 NBUSYBK = 0; // 539 // UECFG1X 540 EPSIZE = 4; // 541 EPBK = 2; // 542 ALLOC = 1; // 543 // UECFG0X 544 EPTYPE = 6; // 545 EPDIR = 0; // 546 // UECONX 547 STALLRQ = 5; // 548 STALLRQC = 4; // 549 RSTDT = 3; // 550 EPEN = 0; // 551 // UERST 552 EPRST = 0; // 553 // UEINTX 554 FIFOCON = 7; // 555 NAKINI = 6; // 556 RWAL = 5; // 557 NAKOUTI = 4; // 558 RXSTPI = 3; // 559 RXOUTI = 2; // 560 STALLEDI = 1; // 561 TXINI = 0; // 562 // UDMFN 563 FNCERR = 4; // 564 // UDADDR 565 ADDEN = 7; // 566 UADD = 0; // 567 // UDIEN 568 UPRSME = 6; // 569 EORSME = 5; // 570 WAKEUPE = 4; // 571 EORSTE = 3; // 572 SOFE = 2; // 573 SUSPE = 0; // 574 // UDINT 575 UPRSMI = 6; // 576 EORSMI = 5; // 577 WAKEUPI = 4; // 578 EORSTI = 3; // 579 SOFI = 2; // 580 SUSPI = 0; // 581 // UDCON 582 LSM = 2; // USB low speed mode 583 RSTCPU = 3; // 584 RMWKUP = 1; // 585 DETACH = 0; // 586 // USBCON 587 USBE = 7; // 588 FRZCLK = 5; // 589 OTGPADE = 4; // 590 VBUSTE = 0; // 591 // USBINT 592 VBUSTI = 0; // 593 // USBSTA 594 SPEED = 3; // 595 VBUS = 0; // 596 // UHWCON 597 UVREGE = 0; // 598 599implementation 600 601{$i avrcommon.inc} 602 603procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0 604procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1 605procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 3 External Interrupt Request 2 606procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 4 External Interrupt Request 3 607procedure Reserved1_ISR; external name 'Reserved1_ISR'; // Interrupt 5 Reserved1 608procedure Reserved2_ISR; external name 'Reserved2_ISR'; // Interrupt 6 Reserved2 609procedure INT6_ISR; external name 'INT6_ISR'; // Interrupt 7 External Interrupt Request 6 610procedure Reserved3_ISR; external name 'Reserved3_ISR'; // Interrupt 8 Reserved3 611procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 9 Pin Change Interrupt Request 0 612procedure USB_GEN_ISR; external name 'USB_GEN_ISR'; // Interrupt 10 USB General Interrupt Request 613procedure USB_COM_ISR; external name 'USB_COM_ISR'; // Interrupt 11 USB Endpoint/Pipe Interrupt Communication Request 614procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-out Interrupt 615procedure Reserved4_ISR; external name 'Reserved4_ISR'; // Interrupt 13 Reserved4 616procedure Reserved5_ISR; external name 'Reserved5_ISR'; // Interrupt 14 Reserved5 617procedure Reserved6_ISR; external name 'Reserved6_ISR'; // Interrupt 15 Reserved6 618procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 16 Timer/Counter1 Capture Event 619procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 17 Timer/Counter1 Compare Match A 620procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 18 Timer/Counter1 Compare Match B 621procedure TIMER1_COMPC_ISR; external name 'TIMER1_COMPC_ISR'; // Interrupt 19 Timer/Counter1 Compare Match C 622procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 20 Timer/Counter1 Overflow 623procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 21 Timer/Counter0 Compare Match A 624procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 22 Timer/Counter0 Compare Match B 625procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 23 Timer/Counter0 Overflow 626procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 24 SPI Serial Transfer Complete 627procedure USART1__RX_ISR; external name 'USART1__RX_ISR'; // Interrupt 25 USART1, Rx Complete 628procedure USART1__UDRE_ISR; external name 'USART1__UDRE_ISR'; // Interrupt 26 USART1 Data register Empty 629procedure USART1__TX_ISR; external name 'USART1__TX_ISR'; // Interrupt 27 USART1, Tx Complete 630procedure ANALOG_COMP_ISR; external name 'ANALOG_COMP_ISR'; // Interrupt 28 Analog Comparator 631procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 29 ADC Conversion Complete 632procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 30 EEPROM Ready 633procedure TIMER3_CAPT_ISR; external name 'TIMER3_CAPT_ISR'; // Interrupt 31 Timer/Counter3 Capture Event 634procedure TIMER3_COMPA_ISR; external name 'TIMER3_COMPA_ISR'; // Interrupt 32 Timer/Counter3 Compare Match A 635procedure TIMER3_COMPB_ISR; external name 'TIMER3_COMPB_ISR'; // Interrupt 33 Timer/Counter3 Compare Match B 636procedure TIMER3_COMPC_ISR; external name 'TIMER3_COMPC_ISR'; // Interrupt 34 Timer/Counter3 Compare Match C 637procedure TIMER3_OVF_ISR; external name 'TIMER3_OVF_ISR'; // Interrupt 35 Timer/Counter3 Overflow 638procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 36 2-wire Serial Interface 639procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 37 Store Program Memory Read 640procedure TIMER4_COMPA_ISR; external name 'TIMER4_COMPA_ISR'; // Interrupt 38 Timer/Counter4 Compare Match A 641procedure TIMER4_COMPB_ISR; external name 'TIMER4_COMPB_ISR'; // Interrupt 39 Timer/Counter4 Compare Match B 642procedure TIMER4_COMPD_ISR; external name 'TIMER4_COMPD_ISR'; // Interrupt 40 Timer/Counter4 Compare Match D 643procedure TIMER4_OVF_ISR; external name 'TIMER4_OVF_ISR'; // Interrupt 41 Timer/Counter4 Overflow 644procedure TIMER4_FPF_ISR; external name 'TIMER4_FPF_ISR'; // Interrupt 42 Timer/Counter4 Fault Protection Interrupt 645 646procedure _FPC_start; assembler; nostackframe; 647label 648 _start; 649 asm 650 .init 651 .globl _start 652 653 jmp _start 654 jmp INT0_ISR 655 jmp INT1_ISR 656 jmp INT2_ISR 657 jmp INT3_ISR 658 jmp Reserved1_ISR 659 jmp Reserved2_ISR 660 jmp INT6_ISR 661 jmp Reserved3_ISR 662 jmp PCINT0_ISR 663 jmp USB_GEN_ISR 664 jmp USB_COM_ISR 665 jmp WDT_ISR 666 jmp Reserved4_ISR 667 jmp Reserved5_ISR 668 jmp Reserved6_ISR 669 jmp TIMER1_CAPT_ISR 670 jmp TIMER1_COMPA_ISR 671 jmp TIMER1_COMPB_ISR 672 jmp TIMER1_COMPC_ISR 673 jmp TIMER1_OVF_ISR 674 jmp TIMER0_COMPA_ISR 675 jmp TIMER0_COMPB_ISR 676 jmp TIMER0_OVF_ISR 677 jmp SPI__STC_ISR 678 jmp USART1__RX_ISR 679 jmp USART1__UDRE_ISR 680 jmp USART1__TX_ISR 681 jmp ANALOG_COMP_ISR 682 jmp ADC_ISR 683 jmp EE_READY_ISR 684 jmp TIMER3_CAPT_ISR 685 jmp TIMER3_COMPA_ISR 686 jmp TIMER3_COMPB_ISR 687 jmp TIMER3_COMPC_ISR 688 jmp TIMER3_OVF_ISR 689 jmp TWI_ISR 690 jmp SPM_READY_ISR 691 jmp TIMER4_COMPA_ISR 692 jmp TIMER4_COMPB_ISR 693 jmp TIMER4_COMPD_ISR 694 jmp TIMER4_OVF_ISR 695 jmp TIMER4_FPF_ISR 696 697 {$i start.inc} 698 699 .weak INT0_ISR 700 .weak INT1_ISR 701 .weak INT2_ISR 702 .weak INT3_ISR 703 .weak Reserved1_ISR 704 .weak Reserved2_ISR 705 .weak INT6_ISR 706 .weak Reserved3_ISR 707 .weak PCINT0_ISR 708 .weak USB_GEN_ISR 709 .weak USB_COM_ISR 710 .weak WDT_ISR 711 .weak Reserved4_ISR 712 .weak Reserved5_ISR 713 .weak Reserved6_ISR 714 .weak TIMER1_CAPT_ISR 715 .weak TIMER1_COMPA_ISR 716 .weak TIMER1_COMPB_ISR 717 .weak TIMER1_COMPC_ISR 718 .weak TIMER1_OVF_ISR 719 .weak TIMER0_COMPA_ISR 720 .weak TIMER0_COMPB_ISR 721 .weak TIMER0_OVF_ISR 722 .weak SPI__STC_ISR 723 .weak USART1__RX_ISR 724 .weak USART1__UDRE_ISR 725 .weak USART1__TX_ISR 726 .weak ANALOG_COMP_ISR 727 .weak ADC_ISR 728 .weak EE_READY_ISR 729 .weak TIMER3_CAPT_ISR 730 .weak TIMER3_COMPA_ISR 731 .weak TIMER3_COMPB_ISR 732 .weak TIMER3_COMPC_ISR 733 .weak TIMER3_OVF_ISR 734 .weak TWI_ISR 735 .weak SPM_READY_ISR 736 .weak TIMER4_COMPA_ISR 737 .weak TIMER4_COMPB_ISR 738 .weak TIMER4_COMPD_ISR 739 .weak TIMER4_OVF_ISR 740 .weak TIMER4_FPF_ISR 741 742 .set INT0_ISR, Default_IRQ_handler 743 .set INT1_ISR, Default_IRQ_handler 744 .set INT2_ISR, Default_IRQ_handler 745 .set INT3_ISR, Default_IRQ_handler 746 .set Reserved1_ISR, Default_IRQ_handler 747 .set Reserved2_ISR, Default_IRQ_handler 748 .set INT6_ISR, Default_IRQ_handler 749 .set Reserved3_ISR, Default_IRQ_handler 750 .set PCINT0_ISR, Default_IRQ_handler 751 .set USB_GEN_ISR, Default_IRQ_handler 752 .set USB_COM_ISR, Default_IRQ_handler 753 .set WDT_ISR, Default_IRQ_handler 754 .set Reserved4_ISR, Default_IRQ_handler 755 .set Reserved5_ISR, Default_IRQ_handler 756 .set Reserved6_ISR, Default_IRQ_handler 757 .set TIMER1_CAPT_ISR, Default_IRQ_handler 758 .set TIMER1_COMPA_ISR, Default_IRQ_handler 759 .set TIMER1_COMPB_ISR, Default_IRQ_handler 760 .set TIMER1_COMPC_ISR, Default_IRQ_handler 761 .set TIMER1_OVF_ISR, Default_IRQ_handler 762 .set TIMER0_COMPA_ISR, Default_IRQ_handler 763 .set TIMER0_COMPB_ISR, Default_IRQ_handler 764 .set TIMER0_OVF_ISR, Default_IRQ_handler 765 .set SPI__STC_ISR, Default_IRQ_handler 766 .set USART1__RX_ISR, Default_IRQ_handler 767 .set USART1__UDRE_ISR, Default_IRQ_handler 768 .set USART1__TX_ISR, Default_IRQ_handler 769 .set ANALOG_COMP_ISR, Default_IRQ_handler 770 .set ADC_ISR, Default_IRQ_handler 771 .set EE_READY_ISR, Default_IRQ_handler 772 .set TIMER3_CAPT_ISR, Default_IRQ_handler 773 .set TIMER3_COMPA_ISR, Default_IRQ_handler 774 .set TIMER3_COMPB_ISR, Default_IRQ_handler 775 .set TIMER3_COMPC_ISR, Default_IRQ_handler 776 .set TIMER3_OVF_ISR, Default_IRQ_handler 777 .set TWI_ISR, Default_IRQ_handler 778 .set SPM_READY_ISR, Default_IRQ_handler 779 .set TIMER4_COMPA_ISR, Default_IRQ_handler 780 .set TIMER4_COMPB_ISR, Default_IRQ_handler 781 .set TIMER4_COMPD_ISR, Default_IRQ_handler 782 .set TIMER4_OVF_ISR, Default_IRQ_handler 783 .set TIMER4_FPF_ISR, Default_IRQ_handler 784 end; 785 786end. 787