1 /////////////////////////////////////////////////////////////////////////
2 // $Id: instrument.cc 14110 2021-01-31 05:41:43Z sshwarts $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // Copyright (c) 2006-2015 Stanislav Shwartsman
6 // Written by Stanislav Shwartsman [sshwarts at sourceforge net]
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
21
22
23 #include <assert.h>
24
25 #include "bochs.h"
26 #include "cpu/cpu.h"
27 #include "disasm/disasm.h"
28
29 // maximum size of an instruction
30 #define MAX_OPCODE_LENGTH 16
31
32 // maximum physical addresses an instruction can generate
33 #define MAX_DATA_ACCESSES 1024
34
35 // Use this variable to turn on/off collection of instrumentation data
36 // If you are not using the debugger to turn this on/off, then possibly
37 // start this at 1 instead of 0.
38 static bool active = 1;
39
40 static disassembler bx_disassembler;
41
42 static struct instruction_t {
43 bool ready; // is current instruction ready to be printed
44 unsigned opcode_length;
45 Bit8u opcode[MAX_OPCODE_LENGTH];
46 bool is32, is64;
47 unsigned num_data_accesses;
48 struct {
49 bx_address laddr; // linear address
50 bx_phy_address paddr; // physical address
51 unsigned rw; // BX_READ, BX_WRITE or BX_RW
52 unsigned size; // 1 .. 64
53 unsigned memtype;
54 } data_access[MAX_DATA_ACCESSES];
55 bool is_branch;
56 bool is_taken;
57 bx_address target_linear;
58 } *instruction;
59
60 static logfunctions *instrument_log = new logfunctions ();
61 #define LOG_THIS instrument_log->
62
bx_instr_init_env(void)63 void bx_instr_init_env(void) {}
bx_instr_exit_env(void)64 void bx_instr_exit_env(void) {}
65
bx_instr_initialize(unsigned cpu)66 void bx_instr_initialize(unsigned cpu)
67 {
68 assert(cpu < BX_SMP_PROCESSORS);
69
70 if (instruction == NULL)
71 instruction = new struct instruction_t[BX_SMP_PROCESSORS];
72
73 fprintf(stderr, "Initialize cpu %u\n", cpu);
74 }
75
bx_instr_reset(unsigned cpu,unsigned type)76 void bx_instr_reset(unsigned cpu, unsigned type)
77 {
78 instruction[cpu].ready = 0;
79 instruction[cpu].num_data_accesses = 0;
80 instruction[cpu].is_branch = 0;
81 }
82
bx_print_instruction(unsigned cpu,const instruction_t * i)83 void bx_print_instruction(unsigned cpu, const instruction_t *i)
84 {
85 char disasm_tbuf[512]; // buffer for instruction disassembly
86 unsigned length = i->opcode_length, n;
87 bx_disassembler.disasm(i->is32, i->is64, 0, 0, i->opcode, disasm_tbuf);
88
89 if(length != 0)
90 {
91 fprintf(stderr, "----------------------------------------------------------\n");
92 fprintf(stderr, "CPU %u: %s\n", cpu, disasm_tbuf);
93 fprintf(stderr, "LEN %u\tBYTES: ", length);
94 for(n=0;n < length;n++) fprintf(stderr, "%02x", i->opcode[n]);
95 if(i->is_branch)
96 {
97 fprintf(stderr, "\tBRANCH ");
98
99 if(i->is_taken)
100 fprintf(stderr, "TARGET " FMT_ADDRX " (TAKEN)", i->target_linear);
101 else
102 fprintf(stderr, "(NOT TAKEN)");
103 }
104 fprintf(stderr, "\n");
105 for(n=0;n < i->num_data_accesses;n++)
106 {
107 fprintf(stderr, "MEM ACCESS[%u]: 0x" FMT_ADDRX " (linear) 0x" FMT_PHY_ADDRX " (physical) %s SIZE: %d\n", n,
108 i->data_access[n].laddr,
109 i->data_access[n].paddr,
110 i->data_access[n].rw == BX_READ ? "RD":"WR",
111 i->data_access[n].size);
112 }
113 fprintf(stderr, "\n");
114 }
115 }
116
bx_instr_before_execution(unsigned cpu,bxInstruction_c * bx_instr)117 void bx_instr_before_execution(unsigned cpu, bxInstruction_c *bx_instr)
118 {
119 if (!active) return;
120
121 instruction_t *i = &instruction[cpu];
122
123 if (i->ready) bx_print_instruction(cpu, i);
124
125 // prepare instruction_t structure for new instruction
126 i->ready = 1;
127 i->num_data_accesses = 0;
128 i->is_branch = 0;
129
130 i->is32 = BX_CPU(cpu)->sregs[BX_SEG_REG_CS].cache.u.segment.d_b;
131 i->is64 = BX_CPU(cpu)->long64_mode();
132 i->opcode_length = bx_instr->ilen();
133 memcpy(i->opcode, bx_instr->get_opcode_bytes(), i->opcode_length);
134 }
135
bx_instr_after_execution(unsigned cpu,bxInstruction_c * bx_instr)136 void bx_instr_after_execution(unsigned cpu, bxInstruction_c *bx_instr)
137 {
138 if (!active) return;
139
140 instruction_t *i = &instruction[cpu];
141 if (i->ready) {
142 bx_print_instruction(cpu, i);
143 i->ready = 0;
144 }
145 }
146
branch_taken(unsigned cpu,bx_address new_eip)147 static void branch_taken(unsigned cpu, bx_address new_eip)
148 {
149 if (!active || !instruction[cpu].ready) return;
150
151 instruction[cpu].is_branch = 1;
152 instruction[cpu].is_taken = 1;
153
154 // find linear address
155 instruction[cpu].target_linear = BX_CPU(cpu)->get_laddr(BX_SEG_REG_CS, new_eip);
156 }
157
bx_instr_cnear_branch_taken(unsigned cpu,bx_address branch_eip,bx_address new_eip)158 void bx_instr_cnear_branch_taken(unsigned cpu, bx_address branch_eip, bx_address new_eip)
159 {
160 branch_taken(cpu, new_eip);
161 }
162
bx_instr_cnear_branch_not_taken(unsigned cpu,bx_address branch_eip)163 void bx_instr_cnear_branch_not_taken(unsigned cpu, bx_address branch_eip)
164 {
165 if (!active || !instruction[cpu].ready) return;
166
167 instruction[cpu].is_branch = 1;
168 instruction[cpu].is_taken = 0;
169 }
170
bx_instr_ucnear_branch(unsigned cpu,unsigned what,bx_address branch_eip,bx_address new_eip)171 void bx_instr_ucnear_branch(unsigned cpu, unsigned what, bx_address branch_eip, bx_address new_eip)
172 {
173 branch_taken(cpu, new_eip);
174 }
175
bx_instr_far_branch(unsigned cpu,unsigned what,Bit16u prev_cs,bx_address prev_eip,Bit16u new_cs,bx_address new_eip)176 void bx_instr_far_branch(unsigned cpu, unsigned what, Bit16u prev_cs, bx_address prev_eip, Bit16u new_cs, bx_address new_eip)
177 {
178 branch_taken(cpu, new_eip);
179 }
180
bx_instr_interrupt(unsigned cpu,unsigned vector)181 void bx_instr_interrupt(unsigned cpu, unsigned vector)
182 {
183 if(active)
184 {
185 fprintf(stderr, "CPU %u: interrupt %02xh\n", cpu, vector);
186 }
187 }
188
bx_instr_exception(unsigned cpu,unsigned vector,unsigned error_code)189 void bx_instr_exception(unsigned cpu, unsigned vector, unsigned error_code)
190 {
191 if(active)
192 {
193 fprintf(stderr, "CPU %u: exception %02xh, error_code = %x\n", cpu, vector, error_code);
194 }
195 }
196
bx_instr_hwinterrupt(unsigned cpu,unsigned vector,Bit16u cs,bx_address eip)197 void bx_instr_hwinterrupt(unsigned cpu, unsigned vector, Bit16u cs, bx_address eip)
198 {
199 if(active)
200 {
201 fprintf(stderr, "CPU %u: hardware interrupt %02xh\n", cpu, vector);
202 }
203 }
204
bx_instr_lin_access(unsigned cpu,bx_address lin,bx_phy_address phy,unsigned len,unsigned memtype,unsigned rw)205 void bx_instr_lin_access(unsigned cpu, bx_address lin, bx_phy_address phy, unsigned len, unsigned memtype, unsigned rw)
206 {
207 if(!active || !instruction[cpu].ready) return;
208
209 unsigned index = instruction[cpu].num_data_accesses;
210
211 if (index < MAX_DATA_ACCESSES) {
212 instruction[cpu].data_access[index].laddr = lin;
213 instruction[cpu].data_access[index].paddr = phy;
214 instruction[cpu].data_access[index].rw = rw;
215 instruction[cpu].data_access[index].size = len;
216 instruction[cpu].data_access[index].memtype = memtype;
217 instruction[cpu].num_data_accesses++;
218 index++;
219 }
220 }
221