1 /* This file is part of the dynarmic project.
2 * Copyright (c) 2019 MerryMage
3 * SPDX-License-Identifier: 0BSD
4 */
5
6 #include "frontend/A32/translate/impl/translate_arm.h"
7
8 namespace Dynarmic::A32 {
9 namespace {
10 using DivideFunction = IR::U32U64 (IREmitter::*)(const IR::U32U64&, const IR::U32U64&);
11
DivideOperation(ArmTranslatorVisitor & v,Cond cond,Reg d,Reg m,Reg n,DivideFunction fn)12 bool DivideOperation(ArmTranslatorVisitor& v, Cond cond, Reg d, Reg m, Reg n,
13 DivideFunction fn) {
14 if (d == Reg::PC || m == Reg::PC || n == Reg::PC) {
15 return v.UnpredictableInstruction();
16 }
17
18 if (!v.ConditionPassed(cond)) {
19 return true;
20 }
21
22 const IR::U32 operand1 = v.ir.GetRegister(n);
23 const IR::U32 operand2 = v.ir.GetRegister(m);
24 const IR::U32 result = (v.ir.*fn)(operand1, operand2);
25
26 v.ir.SetRegister(d, result);
27 return true;
28 }
29 } // Anonymous namespace
30
31 // SDIV<c> <Rd>, <Rn>, <Rm>
arm_SDIV(Cond cond,Reg d,Reg m,Reg n)32 bool ArmTranslatorVisitor::arm_SDIV(Cond cond, Reg d, Reg m, Reg n) {
33 return DivideOperation(*this, cond, d, m, n, &IREmitter::SignedDiv);
34 }
35
36 // UDIV<c> <Rd>, <Rn>, <Rm>
arm_UDIV(Cond cond,Reg d,Reg m,Reg n)37 bool ArmTranslatorVisitor::arm_UDIV(Cond cond, Reg d, Reg m, Reg n) {
38 return DivideOperation(*this, cond, d, m, n, &IREmitter::UnsignedDiv);
39 }
40
41 } // namespace Dynarmic::A32
42