1 /* This file is part of the dynarmic project.
2 * Copyright (c) 2016 MerryMage
3 * SPDX-License-Identifier: 0BSD
4 */
5
6 #include "common/bit_util.h"
7 #include "frontend/A32/translate/impl/translate_arm.h"
8
9 namespace Dynarmic::A32 {
10
11 // CPS<effect> <iflags>{, #<mode>}
12 // CPS #<mode>
arm_CPS()13 bool ArmTranslatorVisitor::arm_CPS() {
14 return InterpretThisInstruction();
15 }
16
17 // MRS<c> <Rd>, <spec_reg>
arm_MRS(Cond cond,Reg d)18 bool ArmTranslatorVisitor::arm_MRS(Cond cond, Reg d) {
19 if (d == Reg::PC) {
20 return UnpredictableInstruction();
21 }
22
23 if (!ConditionPassed(cond)) {
24 return true;
25 }
26
27 ir.SetRegister(d, ir.GetCpsr());
28 return true;
29 }
30
31 // MSR<c> <spec_reg>, #<const>
arm_MSR_imm(Cond cond,int mask,int rotate,Imm<8> imm8)32 bool ArmTranslatorVisitor::arm_MSR_imm(Cond cond, int mask, int rotate, Imm<8> imm8) {
33 ASSERT_MSG(mask != 0, "Decode error");
34
35 if (!ConditionPassed(cond)) {
36 return true;
37 }
38
39 const bool write_nzcvq = Common::Bit<3>(mask);
40 const bool write_g = Common::Bit<2>(mask);
41 const bool write_e = Common::Bit<1>(mask);
42 const u32 imm32 = ArmExpandImm(rotate, imm8);
43
44 if (write_nzcvq) {
45 ir.SetCpsrNZCVQ(ir.Imm32(imm32 & 0xF8000000));
46 }
47
48 if (write_g) {
49 ir.SetGEFlagsCompressed(ir.Imm32(imm32 & 0x000F0000));
50 }
51
52 if (write_e) {
53 const bool E = (imm32 & 0x00000200) != 0;
54 if (E != ir.current_location.EFlag()) {
55 ir.SetTerm(IR::Term::LinkBlock{ir.current_location.AdvancePC(4).SetEFlag(E)});
56 return false;
57 }
58 }
59
60 return true;
61 }
62
63 // MSR<c> <spec_reg>, <Rn>
arm_MSR_reg(Cond cond,int mask,Reg n)64 bool ArmTranslatorVisitor::arm_MSR_reg(Cond cond, int mask, Reg n) {
65 if (mask == 0) {
66 return UnpredictableInstruction();
67 }
68
69 if (n == Reg::PC) {
70 return UnpredictableInstruction();
71 }
72
73 if (!ConditionPassed(cond)) {
74 return true;
75 }
76
77 const bool write_nzcvq = Common::Bit<3>(mask);
78 const bool write_g = Common::Bit<2>(mask);
79 const bool write_e = Common::Bit<1>(mask);
80 const auto value = ir.GetRegister(n);
81
82 if (!write_e) {
83 if (write_nzcvq) {
84 ir.SetCpsrNZCVQ(ir.And(value, ir.Imm32(0xF8000000)));
85 }
86
87 if (write_g) {
88 ir.SetGEFlagsCompressed(ir.And(value, ir.Imm32(0x000F0000)));
89 }
90 } else {
91 const u32 cpsr_mask = (write_nzcvq ? 0xF8000000 : 0) | (write_g ? 0x000F0000 : 0) | 0x00000200;
92 const auto old_cpsr = ir.And(ir.GetCpsr(), ir.Imm32(~cpsr_mask));
93 const auto new_cpsr = ir.And(value, ir.Imm32(cpsr_mask));
94 ir.SetCpsr(ir.Or(old_cpsr, new_cpsr));
95 ir.PushRSB(ir.current_location.AdvancePC(4));
96 ir.BranchWritePC(ir.Imm32(ir.current_location.PC() + 4));
97 ir.SetTerm(IR::Term::CheckHalt{IR::Term::PopRSBHint{}});
98 return false;
99 }
100
101 return true;
102 }
103
104 // RFE{<amode>} <Rn>{!}
arm_RFE()105 bool ArmTranslatorVisitor::arm_RFE() {
106 return InterpretThisInstruction();
107 }
108
109 // SETEND <endian_specifier>
arm_SETEND(bool E)110 bool ArmTranslatorVisitor::arm_SETEND(bool E) {
111 ir.SetTerm(IR::Term::LinkBlock{ir.current_location.AdvancePC(4).SetEFlag(E)});
112 return false;
113 }
114
115 // SRS{<amode>} SP{!}, #<mode>
arm_SRS()116 bool ArmTranslatorVisitor::arm_SRS() {
117 return InterpretThisInstruction();
118 }
119
120 } // namespace Dynarmic::A32
121