1 /* 2 * CPU_emulcycle.i - SC 6510/6502 emulation core (body of 3 * EmulateCycle() function, the same for 4 * both 6510 and 6502) 5 * 6 * Frodo (C) 1994-1997,2002 Christian Bauer 7 */ 8 9 10 /* 11 * Stack macros 12 */ 13 14 // Pop processor flags from the stack 15 #define pop_flags() \ 16 read_to(sp | 0x100, data); \ 17 n_flag = data; \ 18 v_flag = data & 0x40; \ 19 d_flag = data & 0x08; \ 20 i_flag = data & 0x04; \ 21 z_flag = !(data & 0x02); \ 22 c_flag = data & 0x01; 23 24 // Push processor flags onto the stack 25 #define push_flags(b_flag) \ 26 data = 0x20 | (n_flag & 0x80); \ 27 if (v_flag) data |= 0x40; \ 28 if (b_flag) data |= 0x10; \ 29 if (d_flag) data |= 0x08; \ 30 if (i_flag) data |= 0x04; \ 31 if (!z_flag) data |= 0x02; \ 32 if (c_flag) data |= 0x01; \ 33 write_byte(sp-- | 0x100, data); 34 35 36 /* 37 * Other macros 38 */ 39 40 // Branch (cycle 1) 41 #define Branch(flag) \ 42 read_to(pc++, data); \ 43 if (flag) { \ 44 ar = pc + (int8)data; \ 45 if ((ar >> 8) != (pc >> 8)) { \ 46 if (data & 0x80) \ 47 state = O_BRANCH_BP; \ 48 else \ 49 state = O_BRANCH_FP; \ 50 } else \ 51 state = O_BRANCH_NP; \ 52 } else \ 53 state = 0; \ 54 break; 55 56 // Set N and Z flags according to byte 57 #define set_nz(x) (z_flag = n_flag = (x)) 58 59 // Address fetch of RMW instruction done, now read and write operand 60 #define DoRMW state = RMW_DO_IT; break; 61 62 // Operand fetch done, now execute opcode 63 #define Execute state = OpTab[op]; break; 64 65 // Last cycle of opcode 66 #define Last state = 0; break; 67 68 69 /* 70 * EmulCycle() function 71 */ 72 73 switch (state) { 74 75 76 // Opcode fetch (cycle 0) 77 case 0: 78 read_to(pc++, op); 79 state = ModeTab[op]; 80 break; 81 82 83 // IRQ 84 case 0x0008: 85 read_idle(pc); 86 state = 0x0009; 87 break; 88 case 0x0009: 89 read_idle(pc); 90 state = 0x000a; 91 break; 92 case 0x000a: 93 write_byte(sp-- | 0x100, pc >> 8); 94 state = 0x000b; 95 break; 96 case 0x000b: 97 write_byte(sp-- | 0x100, pc); 98 state = 0x000c; 99 break; 100 case 0x000c: 101 push_flags(false); 102 i_flag = true; 103 state = 0x000d; 104 break; 105 case 0x000d: 106 read_to(0xfffe, pc); 107 state = 0x000e; 108 break; 109 case 0x000e: 110 read_to(0xffff, data); 111 pc |= data << 8; 112 Last; 113 114 115 // NMI 116 case 0x0010: 117 read_idle(pc); 118 state = 0x0011; 119 break; 120 case 0x0011: 121 read_idle(pc); 122 state = 0x0012; 123 break; 124 case 0x0012: 125 write_byte(sp-- | 0x100, pc >> 8); 126 state = 0x0013; 127 break; 128 case 0x0013: 129 write_byte(sp-- | 0x100, pc); 130 state = 0x0014; 131 break; 132 case 0x0014: 133 push_flags(false); 134 i_flag = true; 135 state = 0x0015; 136 break; 137 case 0x0015: 138 read_to(0xfffa, pc); 139 state = 0x0016; 140 break; 141 case 0x0016: 142 read_to(0xfffb, data); 143 pc |= data << 8; 144 Last; 145 146 147 // Addressing modes: Fetch effective address, no extra cycles (-> ar) 148 case A_ZERO: 149 read_to(pc++, ar); 150 Execute; 151 152 case A_ZEROX: 153 read_to(pc++, ar); 154 state = A_ZEROX1; 155 break; 156 case A_ZEROX1: 157 read_idle(ar); 158 ar = (ar + x) & 0xff; 159 Execute; 160 161 case A_ZEROY: 162 read_to(pc++, ar); 163 state = A_ZEROY1; 164 break; 165 case A_ZEROY1: 166 read_idle(ar); 167 ar = (ar + y) & 0xff; 168 Execute; 169 170 case A_ABS: 171 read_to(pc++, ar); 172 state = A_ABS1; 173 break; 174 case A_ABS1: 175 read_to(pc++, data); 176 ar = ar | (data << 8); 177 Execute; 178 179 case A_ABSX: 180 read_to(pc++, ar); 181 state = A_ABSX1; 182 break; 183 case A_ABSX1: 184 read_to(pc++, ar2); // Note: Some undocumented opcodes rely on the value of ar2 185 if (ar+x < 0x100) 186 state = A_ABSX2; 187 else 188 state = A_ABSX3; 189 ar = (ar + x) & 0xff | (ar2 << 8); 190 break; 191 case A_ABSX2: // No page crossed 192 read_idle(ar); 193 Execute; 194 case A_ABSX3: // Page crossed 195 read_idle(ar); 196 ar += 0x100; 197 Execute; 198 199 case A_ABSY: 200 read_to(pc++, ar); 201 state = A_ABSY1; 202 break; 203 case A_ABSY1: 204 read_to(pc++, ar2); // Note: Some undocumented opcodes rely on the value of ar2 205 if (ar+y < 0x100) 206 state = A_ABSY2; 207 else 208 state = A_ABSY3; 209 ar = (ar + y) & 0xff | (ar2 << 8); 210 break; 211 case A_ABSY2: // No page crossed 212 read_idle(ar); 213 Execute; 214 case A_ABSY3: // Page crossed 215 read_idle(ar); 216 ar += 0x100; 217 Execute; 218 219 case A_INDX: 220 read_to(pc++, ar2); 221 state = A_INDX1; 222 break; 223 case A_INDX1: 224 read_idle(ar2); 225 ar2 = (ar2 + x) & 0xff; 226 state = A_INDX2; 227 break; 228 case A_INDX2: 229 read_to(ar2, ar); 230 state = A_INDX3; 231 break; 232 case A_INDX3: 233 read_to((ar2 + 1) & 0xff, data); 234 ar = ar | (data << 8); 235 Execute; 236 237 case A_INDY: 238 read_to(pc++, ar2); 239 state = A_INDY1; 240 break; 241 case A_INDY1: 242 read_to(ar2, ar); 243 state = A_INDY2; 244 break; 245 case A_INDY2: 246 read_to((ar2 + 1) & 0xff, ar2); // Note: Some undocumented opcodes rely on the value of ar2 247 if (ar+y < 0x100) 248 state = A_INDY3; 249 else 250 state = A_INDY4; 251 ar = (ar + y) & 0xff | (ar2 << 8); 252 break; 253 case A_INDY3: // No page crossed 254 read_idle(ar); 255 Execute; 256 case A_INDY4: // Page crossed 257 read_idle(ar); 258 ar += 0x100; 259 Execute; 260 261 262 // Addressing modes: Fetch effective address, extra cycle on page crossing (-> ar) 263 case AE_ABSX: 264 read_to(pc++, ar); 265 state = AE_ABSX1; 266 break; 267 case AE_ABSX1: 268 read_to(pc++, data); 269 if (ar+x < 0x100) { 270 ar = (ar + x) & 0xff | (data << 8); 271 Execute; 272 } else { 273 ar = (ar + x) & 0xff | (data << 8); 274 state = AE_ABSX2; 275 } 276 break; 277 case AE_ABSX2: // Page crossed 278 read_idle(ar); 279 ar += 0x100; 280 Execute; 281 282 case AE_ABSY: 283 read_to(pc++, ar); 284 state = AE_ABSY1; 285 break; 286 case AE_ABSY1: 287 read_to(pc++, data); 288 if (ar+y < 0x100) { 289 ar = (ar + y) & 0xff | (data << 8); 290 Execute; 291 } else { 292 ar = (ar + y) & 0xff | (data << 8); 293 state = AE_ABSY2; 294 } 295 break; 296 case AE_ABSY2: // Page crossed 297 read_idle(ar); 298 ar += 0x100; 299 Execute; 300 301 case AE_INDY: 302 read_to(pc++, ar2); 303 state = AE_INDY1; 304 break; 305 case AE_INDY1: 306 read_to(ar2, ar); 307 state = AE_INDY2; 308 break; 309 case AE_INDY2: 310 read_to((ar2 + 1) & 0xff, data); 311 if (ar+y < 0x100) { 312 ar = (ar + y) & 0xff | (data << 8); 313 Execute; 314 } else { 315 ar = (ar + y) & 0xff | (data << 8); 316 state = AE_INDY3; 317 } 318 break; 319 case AE_INDY3: // Page crossed 320 read_idle(ar); 321 ar += 0x100; 322 Execute; 323 324 325 // Addressing modes: Read operand, write it back, no extra cycles (-> ar, rdbuf) 326 case M_ZERO: 327 read_to(pc++, ar); 328 DoRMW; 329 330 case M_ZEROX: 331 read_to(pc++, ar); 332 state = M_ZEROX1; 333 break; 334 case M_ZEROX1: 335 read_idle(ar); 336 ar = (ar + x) & 0xff; 337 DoRMW; 338 339 case M_ZEROY: 340 read_to(pc++, ar); 341 state = M_ZEROY1; 342 break; 343 case M_ZEROY1: 344 read_idle(ar); 345 ar = (ar + y) & 0xff; 346 DoRMW; 347 348 case M_ABS: 349 read_to(pc++, ar); 350 state = M_ABS1; 351 break; 352 case M_ABS1: 353 read_to(pc++, data); 354 ar = ar | (data << 8); 355 DoRMW; 356 357 case M_ABSX: 358 read_to(pc++, ar); 359 state = M_ABSX1; 360 break; 361 case M_ABSX1: 362 read_to(pc++, data); 363 if (ar+x < 0x100) 364 state = M_ABSX2; 365 else 366 state = M_ABSX3; 367 ar = (ar + x) & 0xff | (data << 8); 368 break; 369 case M_ABSX2: // No page crossed 370 read_idle(ar); 371 DoRMW; 372 case M_ABSX3: // Page crossed 373 read_idle(ar); 374 ar += 0x100; 375 DoRMW; 376 377 case M_ABSY: 378 read_to(pc++, ar); 379 state = M_ABSY1; 380 break; 381 case M_ABSY1: 382 read_to(pc++, data); 383 if (ar+y < 0x100) 384 state = M_ABSY2; 385 else 386 state = M_ABSY3; 387 ar = (ar + y) & 0xff | (data << 8); 388 break; 389 case M_ABSY2: // No page crossed 390 read_idle(ar); 391 DoRMW; 392 case M_ABSY3: // Page crossed 393 read_idle(ar); 394 ar += 0x100; 395 DoRMW; 396 397 case M_INDX: 398 read_to(pc++, ar2); 399 state = M_INDX1; 400 break; 401 case M_INDX1: 402 read_idle(ar2); 403 ar2 = (ar2 + x) & 0xff; 404 state = M_INDX2; 405 break; 406 case M_INDX2: 407 read_to(ar2, ar); 408 state = M_INDX3; 409 break; 410 case M_INDX3: 411 read_to((ar2 + 1) & 0xff, data); 412 ar = ar | (data << 8); 413 DoRMW; 414 415 case M_INDY: 416 read_to(pc++, ar2); 417 state = M_INDY1; 418 break; 419 case M_INDY1: 420 read_to(ar2, ar); 421 state = M_INDY2; 422 break; 423 case M_INDY2: 424 read_to((ar2 + 1) & 0xff, data); 425 if (ar+y < 0x100) 426 state = M_INDY3; 427 else 428 state = M_INDY4; 429 ar = (ar + y) & 0xff | (data << 8); 430 break; 431 case M_INDY3: // No page crossed 432 read_idle(ar); 433 DoRMW; 434 case M_INDY4: // Page crossed 435 read_idle(ar); 436 ar += 0x100; 437 DoRMW; 438 439 case RMW_DO_IT: 440 read_to(ar, rdbuf); 441 state = RMW_DO_IT1; 442 break; 443 case RMW_DO_IT1: 444 write_byte(ar, rdbuf); 445 Execute; 446 447 448 // Load group 449 case O_LDA: 450 read_to(ar, data); 451 set_nz(a = data); 452 Last; 453 case O_LDA_I: 454 read_to(pc++, data); 455 set_nz(a = data); 456 Last; 457 458 case O_LDX: 459 read_to(ar, data); 460 set_nz(x = data); 461 Last; 462 case O_LDX_I: 463 read_to(pc++, data); 464 set_nz(x = data); 465 Last; 466 467 case O_LDY: 468 read_to(ar, data); 469 set_nz(y = data); 470 Last; 471 case O_LDY_I: 472 read_to(pc++, data); 473 set_nz(y = data); 474 Last; 475 476 477 // Store group 478 case O_STA: 479 write_byte(ar, a); 480 Last; 481 482 case O_STX: 483 write_byte(ar, x); 484 Last; 485 486 case O_STY: 487 write_byte(ar, y); 488 Last; 489 490 491 // Transfer group 492 case O_TAX: 493 read_idle(pc); 494 set_nz(x = a); 495 Last; 496 497 case O_TXA: 498 read_idle(pc); 499 set_nz(a = x); 500 Last; 501 502 case O_TAY: 503 read_idle(pc); 504 set_nz(y = a); 505 Last; 506 507 case O_TYA: 508 read_idle(pc); 509 set_nz(a = y); 510 Last; 511 512 case O_TSX: 513 read_idle(pc); 514 set_nz(x = sp); 515 Last; 516 517 case O_TXS: 518 read_idle(pc); 519 sp = x; 520 Last; 521 522 523 // Arithmetic group 524 case O_ADC: 525 read_to(ar, data); 526 do_adc(data); 527 Last; 528 case O_ADC_I: 529 read_to(pc++, data); 530 do_adc(data); 531 Last; 532 533 case O_SBC: 534 read_to(ar, data); 535 do_sbc(data); 536 Last; 537 case O_SBC_I: 538 read_to(pc++, data); 539 do_sbc(data); 540 Last; 541 542 543 // Increment/decrement group 544 case O_INX: 545 read_idle(pc); 546 set_nz(++x); 547 Last; 548 549 case O_DEX: 550 read_idle(pc); 551 set_nz(--x); 552 Last; 553 554 case O_INY: 555 read_idle(pc); 556 set_nz(++y); 557 Last; 558 559 case O_DEY: 560 read_idle(pc); 561 set_nz(--y); 562 Last; 563 564 case O_INC: 565 write_byte(ar, set_nz(rdbuf + 1)); 566 Last; 567 568 case O_DEC: 569 write_byte(ar, set_nz(rdbuf - 1)); 570 Last; 571 572 573 // Logic group 574 case O_AND: 575 read_to(ar, data); 576 set_nz(a &= data); 577 Last; 578 case O_AND_I: 579 read_to(pc++, data); 580 set_nz(a &= data); 581 Last; 582 583 case O_ORA: 584 read_to(ar, data); 585 set_nz(a |= data); 586 Last; 587 case O_ORA_I: 588 read_to(pc++, data); 589 set_nz(a |= data); 590 Last; 591 592 case O_EOR: 593 read_to(ar, data); 594 set_nz(a ^= data); 595 Last; 596 case O_EOR_I: 597 read_to(pc++, data); 598 set_nz(a ^= data); 599 Last; 600 601 // Compare group 602 case O_CMP: 603 read_to(ar, data); 604 set_nz(ar = a - data); 605 c_flag = ar < 0x100; 606 Last; 607 case O_CMP_I: 608 read_to(pc++, data); 609 set_nz(ar = a - data); 610 c_flag = ar < 0x100; 611 Last; 612 613 case O_CPX: 614 read_to(ar, data); 615 set_nz(ar = x - data); 616 c_flag = ar < 0x100; 617 Last; 618 case O_CPX_I: 619 read_to(pc++, data); 620 set_nz(ar = x - data); 621 c_flag = ar < 0x100; 622 Last; 623 624 case O_CPY: 625 read_to(ar, data); 626 set_nz(ar = y - data); 627 c_flag = ar < 0x100; 628 Last; 629 case O_CPY_I: 630 read_to(pc++, data); 631 set_nz(ar = y - data); 632 c_flag = ar < 0x100; 633 Last; 634 635 636 // Bit-test group 637 case O_BIT: 638 read_to(ar, data); 639 z_flag = a & data; 640 n_flag = data; 641 v_flag = data & 0x40; 642 Last; 643 644 645 // Shift/rotate group 646 case O_ASL: 647 c_flag = rdbuf & 0x80; 648 write_byte(ar, set_nz(rdbuf << 1)); 649 Last; 650 case O_ASL_A: 651 read_idle(pc); 652 c_flag = a & 0x80; 653 set_nz(a <<= 1); 654 Last; 655 656 case O_LSR: 657 c_flag = rdbuf & 0x01; 658 write_byte(ar, set_nz(rdbuf >> 1)); 659 Last; 660 case O_LSR_A: 661 read_idle(pc); 662 c_flag = a & 0x01; 663 set_nz(a >>= 1); 664 Last; 665 666 case O_ROL: 667 write_byte(ar, set_nz(c_flag ? (rdbuf << 1) | 0x01 : rdbuf << 1)); 668 c_flag = rdbuf & 0x80; 669 Last; 670 case O_ROL_A: 671 read_idle(pc); 672 data = a & 0x80; 673 set_nz(a = c_flag ? (a << 1) | 0x01 : a << 1); 674 c_flag = data; 675 Last; 676 677 case O_ROR: 678 write_byte(ar, set_nz(c_flag ? (rdbuf >> 1) | 0x80 : rdbuf >> 1)); 679 c_flag = rdbuf & 0x01; 680 Last; 681 case O_ROR_A: 682 read_idle(pc); 683 data = a & 0x01; 684 set_nz(a = (c_flag ? (a >> 1) | 0x80 : a >> 1)); 685 c_flag = data; 686 Last; 687 688 689 // Stack group 690 case O_PHA: 691 read_idle(pc); 692 state = O_PHA1; 693 break; 694 case O_PHA1: 695 write_byte(sp-- | 0x100, a); 696 Last; 697 698 case O_PLA: 699 read_idle(pc); 700 state = O_PLA1; 701 break; 702 case O_PLA1: 703 read_idle(sp++ | 0x100); 704 state = O_PLA2; 705 break; 706 case O_PLA2: 707 read_to(sp | 0x100, data); 708 set_nz(a = data); 709 Last; 710 711 case O_PHP: 712 read_idle(pc); 713 state = O_PHP1; 714 break; 715 case O_PHP1: 716 push_flags(true); 717 Last; 718 719 case O_PLP: 720 read_idle(pc); 721 state = O_PLP1; 722 break; 723 case O_PLP1: 724 read_idle(sp++ | 0x100); 725 state = O_PLP2; 726 break; 727 case O_PLP2: 728 pop_flags(); 729 Last; 730 731 732 // Jump/branch group 733 case O_JMP: 734 read_to(pc++, ar); 735 state = O_JMP1; 736 break; 737 case O_JMP1: 738 read_to(pc, data); 739 pc = (data << 8) | ar; 740 Last; 741 742 case O_JMP_I: 743 read_to(ar, pc); 744 state = O_JMP_I1; 745 break; 746 case O_JMP_I1: 747 read_to((ar + 1) & 0xff | ar & 0xff00, data); 748 pc |= data << 8; 749 Last; 750 751 case O_JSR: 752 read_to(pc++, ar); 753 state = O_JSR1; 754 break; 755 case O_JSR1: 756 read_idle(sp | 0x100); 757 state = O_JSR2; 758 break; 759 case O_JSR2: 760 write_byte(sp-- | 0x100, pc >> 8); 761 state = O_JSR3; 762 break; 763 case O_JSR3: 764 write_byte(sp-- | 0x100, pc); 765 state = O_JSR4; 766 break; 767 case O_JSR4: 768 read_to(pc++, data); 769 pc = ar | (data << 8); 770 Last; 771 772 case O_RTS: 773 read_idle(pc); 774 state = O_RTS1; 775 break; 776 case O_RTS1: 777 read_idle(sp++ | 0x100); 778 state = O_RTS2; 779 break; 780 case O_RTS2: 781 read_to(sp++ | 0x100, pc); 782 state = O_RTS3; 783 break; 784 case O_RTS3: 785 read_to(sp | 0x100, data); 786 pc |= data << 8; 787 state = O_RTS4; 788 break; 789 case O_RTS4: 790 read_idle(pc++); 791 Last; 792 793 case O_RTI: 794 read_idle(pc); 795 state = O_RTI1; 796 break; 797 case O_RTI1: 798 read_idle(sp++ | 0x100); 799 state = O_RTI2; 800 break; 801 case O_RTI2: 802 pop_flags(); 803 sp++; 804 state = O_RTI3; 805 break; 806 case O_RTI3: 807 read_to(sp++ | 0x100, pc); 808 state = O_RTI4; 809 break; 810 case O_RTI4: 811 read_to(sp | 0x100, data); 812 pc |= data << 8; 813 Last; 814 815 case O_BRK: 816 read_idle(pc++); 817 state = O_BRK1; 818 break; 819 case O_BRK1: 820 write_byte(sp-- | 0x100, pc >> 8); 821 state = O_BRK2; 822 break; 823 case O_BRK2: 824 write_byte(sp-- | 0x100, pc); 825 state = O_BRK3; 826 break; 827 case O_BRK3: 828 push_flags(true); 829 i_flag = true; 830 #ifndef IS_CPU_1541 831 if (interrupt.intr[INT_NMI]) { // BRK interrupted by NMI? 832 interrupt.intr[INT_NMI] = false; // Simulate an edge-triggered input 833 state = 0x0015; // Jump to NMI sequence 834 break; 835 } 836 #endif 837 state = O_BRK4; 838 break; 839 case O_BRK4: 840 #ifndef IS_CPU_1541 841 first_nmi_cycle++; // Delay NMI 842 #endif 843 read_to(0xfffe, pc); 844 state = O_BRK5; 845 break; 846 case O_BRK5: 847 read_to(0xffff, data); 848 pc |= data << 8; 849 Last; 850 851 case O_BCS: 852 Branch(c_flag); 853 854 case O_BCC: 855 Branch(!c_flag); 856 857 case O_BEQ: 858 Branch(!z_flag); 859 860 case O_BNE: 861 Branch(z_flag); 862 863 case O_BVS: 864 #ifndef IS_CPU_1541 865 Branch(v_flag); 866 #else 867 Branch((via2_pcr & 0x0e) == 0x0e ? 1 : v_flag); // GCR byte ready flag 868 #endif 869 870 case O_BVC: 871 #ifndef IS_CPU_1541 872 Branch(!v_flag); 873 #else 874 Branch(!((via2_pcr & 0x0e) == 0x0e) ? 0 : v_flag); // GCR byte ready flag 875 #endif 876 877 case O_BMI: 878 Branch(n_flag & 0x80); 879 880 case O_BPL: 881 Branch(!(n_flag & 0x80)); 882 883 case O_BRANCH_NP: // No page crossed 884 first_irq_cycle++; // Delay IRQ 885 #ifndef IS_CPU_1541 886 first_nmi_cycle++; // Delay NMI 887 #endif 888 read_idle(pc); 889 pc = ar; 890 Last; 891 case O_BRANCH_BP: // Page crossed, branch backwards 892 read_idle(pc); 893 pc = ar; 894 state = O_BRANCH_BP1; 895 break; 896 case O_BRANCH_BP1: 897 read_idle(pc + 0x100); 898 Last; 899 case O_BRANCH_FP: // Page crossed, branch forwards 900 read_idle(pc); 901 pc = ar; 902 state = O_BRANCH_FP1; 903 break; 904 case O_BRANCH_FP1: 905 read_idle(pc - 0x100); 906 Last; 907 908 909 // Flag group 910 case O_SEC: 911 read_idle(pc); 912 c_flag = true; 913 Last; 914 915 case O_CLC: 916 read_idle(pc); 917 c_flag = false; 918 Last; 919 920 case O_SED: 921 read_idle(pc); 922 d_flag = true; 923 Last; 924 925 case O_CLD: 926 read_idle(pc); 927 d_flag = false; 928 Last; 929 930 case O_SEI: 931 read_idle(pc); 932 i_flag = true; 933 Last; 934 935 case O_CLI: 936 read_idle(pc); 937 i_flag = false; 938 Last; 939 940 case O_CLV: 941 read_idle(pc); 942 v_flag = false; 943 Last; 944 945 946 // NOP group 947 case O_NOP: 948 read_idle(pc); 949 Last; 950 951 952 /* 953 * Undocumented opcodes start here 954 */ 955 956 // NOP group 957 case O_NOP_I: 958 read_idle(pc++); 959 Last; 960 961 case O_NOP_A: 962 read_idle(ar); 963 Last; 964 965 966 // Load A/X group 967 case O_LAX: 968 read_to(ar, data); 969 set_nz(a = x = data); 970 Last; 971 972 973 // Store A/X group 974 case O_SAX: 975 write_byte(ar, a & x); 976 Last; 977 978 979 // ASL/ORA group 980 case O_SLO: 981 c_flag = rdbuf & 0x80; 982 rdbuf <<= 1; 983 write_byte(ar, rdbuf); 984 set_nz(a |= rdbuf); 985 Last; 986 987 988 // ROL/AND group 989 case O_RLA: 990 tmp = rdbuf & 0x80; 991 rdbuf = c_flag ? (rdbuf << 1) | 0x01 : rdbuf << 1; 992 c_flag = tmp; 993 write_byte(ar, rdbuf); 994 set_nz(a &= rdbuf); 995 Last; 996 997 998 // LSR/EOR group 999 case O_SRE: 1000 c_flag = rdbuf & 0x01; 1001 rdbuf >>= 1; 1002 write_byte(ar, rdbuf); 1003 set_nz(a ^= rdbuf); 1004 Last; 1005 1006 1007 // ROR/ADC group 1008 case O_RRA: 1009 tmp = rdbuf & 0x01; 1010 rdbuf = c_flag ? (rdbuf >> 1) | 0x80 : rdbuf >> 1; 1011 c_flag = tmp; 1012 write_byte(ar, rdbuf); 1013 do_adc(rdbuf); 1014 Last; 1015 1016 1017 // DEC/CMP group 1018 case O_DCP: 1019 write_byte(ar, --rdbuf); 1020 set_nz(ar = a - rdbuf); 1021 c_flag = ar < 0x100; 1022 Last; 1023 1024 1025 // INC/SBC group 1026 case O_ISB: 1027 write_byte(ar, ++rdbuf); 1028 do_sbc(rdbuf); 1029 Last; 1030 1031 1032 // Complex functions 1033 case O_ANC_I: 1034 read_to(pc++, data); 1035 set_nz(a &= data); 1036 c_flag = n_flag & 0x80; 1037 Last; 1038 1039 case O_ASR_I: 1040 read_to(pc++, data); 1041 a &= data; 1042 c_flag = a & 0x01; 1043 set_nz(a >>= 1); 1044 Last; 1045 1046 case O_ARR_I: 1047 read_to(pc++, data); 1048 data &= a; 1049 a = (c_flag ? (data >> 1) | 0x80 : data >> 1); 1050 if (!d_flag) { 1051 set_nz(a); 1052 c_flag = a & 0x40; 1053 v_flag = (a & 0x40) ^ ((a & 0x20) << 1); 1054 } else { 1055 n_flag = c_flag ? 0x80 : 0; 1056 z_flag = a; 1057 v_flag = (data ^ a) & 0x40; 1058 if ((data & 0x0f) + (data & 0x01) > 5) 1059 a = a & 0xf0 | (a + 6) & 0x0f; 1060 if (c_flag = ((data + (data & 0x10)) & 0x1f0) > 0x50) 1061 a += 0x60; 1062 } 1063 Last; 1064 1065 case O_ANE_I: 1066 read_to(pc++, data); 1067 set_nz(a = (a | 0xee) & x & data); 1068 Last; 1069 1070 case O_LXA_I: 1071 read_to(pc++, data); 1072 set_nz(a = x = (a | 0xee) & data); 1073 Last; 1074 1075 case O_SBX_I: 1076 read_to(pc++, data); 1077 set_nz(x = ar = (x & a) - data); 1078 c_flag = ar < 0x100; 1079 Last; 1080 1081 case O_LAS: 1082 read_to(ar, data); 1083 set_nz(a = x = sp = data & sp); 1084 Last; 1085 1086 case O_SHS: // ar2 contains the high byte of the operand address 1087 write_byte(ar, (ar2+1) & (sp = a & x)); 1088 Last; 1089 1090 case O_SHY: // ar2 contains the high byte of the operand address 1091 write_byte(ar, y & (ar2+1)); 1092 Last; 1093 1094 case O_SHX: // ar2 contains the high byte of the operand address 1095 write_byte(ar, x & (ar2+1)); 1096 Last; 1097 1098 case O_SHA: // ar2 contains the high byte of the operand address 1099 write_byte(ar, a & x & (ar2+1)); 1100 Last; 1101