1 /*
2 * Copyright (C) 2007-2009 Anders Gavare. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. The name of the author may not be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 *
28 * COMMENT: Generic IRQ controller for the test machines
29 */
30
31 #include <stdio.h>
32 #include <stdlib.h>
33 #include <string.h>
34
35 #include "cpu.h"
36 #include "device.h"
37 #include "interrupt.h"
38 #include "machine.h"
39 #include "memory.h"
40 #include "misc.h"
41
42 #include "testmachine/dev_irqc.h"
43
44
45 #define N_IRQC_INTERRUPTS 32
46
47 struct irqc_data {
48 struct interrupt irq; /* Connected to the CPU */
49
50 int asserted; /* Current CPU irq assertion */
51
52 uint32_t status; /* Interrupt Status register */
53 uint32_t enabled; /* Interrupt Enable register */
54 };
55
56
irqc_interrupt_assert(struct interrupt * interrupt)57 void irqc_interrupt_assert(struct interrupt *interrupt)
58 {
59 struct irqc_data *d = (struct irqc_data *) interrupt->extra;
60 d->status |= interrupt->line;
61
62 if ((d->status & d->enabled) && !d->asserted) {
63 INTERRUPT_ASSERT(d->irq);
64 d->asserted = 1;
65 }
66 }
67
68
irqc_interrupt_deassert(struct interrupt * interrupt)69 void irqc_interrupt_deassert(struct interrupt *interrupt)
70 {
71 struct irqc_data *d = (struct irqc_data *) interrupt->extra;
72 d->status &= ~interrupt->line;
73
74 if (!(d->status & d->enabled) && d->asserted) {
75 INTERRUPT_DEASSERT(d->irq);
76 d->asserted = 0;
77 }
78 }
79
80
DEVICE_ACCESS(irqc)81 DEVICE_ACCESS(irqc)
82 {
83 struct irqc_data *d = (struct irqc_data *) extra;
84 uint64_t idata = 0, odata = 0;
85
86 if (writeflag == MEM_WRITE)
87 idata = memory_readmax64(cpu, data, len);
88
89 switch (relative_addr) {
90
91 case DEV_IRQC_IRQ:
92 /* Status register: */
93 if (writeflag == MEM_READ) {
94 odata = d->status;
95 } else {
96 fatal("[ irqc: WARNING! write to DEV_IRQC_IRQ ]\n");
97 }
98 break;
99
100 case DEV_IRQC_MASK:
101 /* Mask interrupts by clearing Enable bits: */
102 if (writeflag == MEM_READ) {
103 fatal("[ irqc: WARNING! read from DEV_IRQC_MASK ]\n");
104 } else {
105 int old_assert = d->status & d->enabled;
106 int new_assert;
107
108 d->enabled &= ~(1 << idata);
109
110 new_assert = d->status & d->enabled;
111
112 if (!old_assert && new_assert)
113 INTERRUPT_ASSERT(d->irq);
114 else if (old_assert && !new_assert)
115 INTERRUPT_DEASSERT(d->irq);
116 }
117 break;
118
119 case DEV_IRQC_UNMASK:
120 /* Unmask interrupts by setting Enable bits: */
121 if (writeflag == MEM_READ) {
122 fatal("[ irqc: WARNING! read from DEV_IRQC_UNMASK ]\n");
123 } else {
124 int old_assert = d->status & d->enabled;
125 int new_assert;
126
127 d->enabled |= (1 << idata);
128
129 new_assert = d->status & d->enabled;
130
131 if (!old_assert && new_assert)
132 INTERRUPT_ASSERT(d->irq);
133 else if (old_assert && !new_assert)
134 INTERRUPT_DEASSERT(d->irq);
135 }
136 break;
137
138 default:if (writeflag == MEM_WRITE) {
139 fatal("[ irqc: unimplemented write to "
140 "offset 0x%x: data=0x%x ]\n", (int)
141 relative_addr, (int)idata);
142 } else {
143 fatal("[ irqc: unimplemented read from "
144 "offset 0x%x ]\n", (int)relative_addr);
145 }
146 }
147
148 if (writeflag == MEM_READ)
149 memory_writemax64(cpu, data, len, odata);
150
151 return 1;
152 }
153
154
DEVINIT(irqc)155 DEVINIT(irqc)
156 {
157 struct irqc_data *d;
158 char n[300];
159 int i;
160
161 CHECK_ALLOCATION(d = (struct irqc_data *) malloc(sizeof(struct irqc_data)));
162 memset(d, 0, sizeof(struct irqc_data));
163
164 /* Connect to the CPU's interrupt pin: */
165 INTERRUPT_CONNECT(devinit->interrupt_path, d->irq);
166
167 /* Register the interrupts: */
168 for (i=0; i<N_IRQC_INTERRUPTS; i++) {
169 struct interrupt templ;
170
171 snprintf(n, sizeof(n), "%s.irqc.%i",
172 devinit->interrupt_path, i);
173
174 memset(&templ, 0, sizeof(templ));
175 templ.line = 1 << i; /* Note: line contains the
176 _mask_, not line number. */
177 templ.name = n;
178 templ.extra = d;
179 templ.interrupt_assert = irqc_interrupt_assert;
180 templ.interrupt_deassert = irqc_interrupt_deassert;
181 interrupt_handler_register(&templ);
182 }
183
184 /* Default to all interrupts enabled: */
185 d->enabled = 0xffffffff;
186
187 memory_device_register(devinit->machine->memory, devinit->name,
188 devinit->addr, DEV_IRQC_LENGTH, dev_irqc_access, d,
189 DM_DEFAULT, NULL);
190
191 return 1;
192 }
193
194